JP2002057462A - Multilayered printed circuit board - Google Patents

Multilayered printed circuit board

Info

Publication number
JP2002057462A
JP2002057462A JP2000240985A JP2000240985A JP2002057462A JP 2002057462 A JP2002057462 A JP 2002057462A JP 2000240985 A JP2000240985 A JP 2000240985A JP 2000240985 A JP2000240985 A JP 2000240985A JP 2002057462 A JP2002057462 A JP 2002057462A
Authority
JP
Japan
Prior art keywords
wiring
wirings
group
parallel
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000240985A
Other languages
Japanese (ja)
Inventor
Ryuji Mori
隆二 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000240985A priority Critical patent/JP2002057462A/en
Publication of JP2002057462A publication Critical patent/JP2002057462A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally a crosswalk noise is generated between adjacent signal wirings when a wiring interval is narrowed in a multilayered circuit board, having a parallel wiring a group. SOLUTION: In the multilayered printed circuit board, a second insulating layer I2, having a second parallel wiring group L2 perpendicular to a first parallel wiring group L1, is laminated on a first insulating layer I1 having the first group L1. The first and second groups L1 and L2 are connected via a feedthrough conductor group T. The groups L1 and L2 respectively have a plurality of signal wirings S1 and S2 and power wirings P1 and P2 adjacent to the wirings S1 and S2 or ground wirings G1 and G2. The thickness of the wiring conductor of each of the wirings P1 and P2, adjacent to the wirings S1 and S2 or the wirings G1 and G2, is set larger than that of each of the wirings S1 and S2. Crosswalks between the wirings S1 and between the wirings S2 can be reduced effectively.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電子回路基板等に使
用される多層配線基板に関し、より詳細には高速で作動
する半導体素子を搭載する多層配線基板における配線構
造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board used for an electronic circuit board or the like, and more particularly to a wiring structure in a multilayer wiring board on which a semiconductor element operating at a high speed is mounted.

【0002】[0002]

【従来の技術】従来、半導体集積回路素子等の半導体素
子が搭載され、電子回路基板等に使用される多層配線基
板においては、内部配線用の配線導体の形成にあたっ
て、アルミナ等のセラミックスから成る絶縁層とタング
ステン(W)等の高融点金属から成る配線導体とを交互
に積層して多層配線基板を形成していた。
2. Description of the Related Art Conventionally, in a multilayer wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted and which is used for an electronic circuit board or the like, an insulating material made of ceramics such as alumina is used for forming a wiring conductor for internal wiring. Layers and wiring conductors made of a refractory metal such as tungsten (W) are alternately stacked to form a multilayer wiring board.

【0003】従来の多層配線基板においては、内部配線
用配線導体のうち信号配線は通常はストリップ線路構造
とされており、信号配線として形成された配線導体の上
下に絶縁層を介していわゆるベタパターン形状の広面積
の接地(グランド)層または電源層が形成されていた。
In a conventional multilayer wiring board, signal wirings of internal wiring wiring conductors usually have a strip line structure, and a so-called solid pattern is formed above and below wiring conductors formed as signal wirings via insulating layers. A ground (ground) layer or a power supply layer having a wide area of the shape was formed.

【0004】また、多層配線基板が取り扱う電気信号の
高速化に伴い、絶縁層を比誘電率が10程度であるアルミ
ナセラミックスに代えて比誘電率が3.5 〜5と比較的小
さいポリイミド樹脂やエポキシ樹脂を用いて形成し、こ
の絶縁層上に蒸着法やスパッタリング法等の気相成長法
による薄膜形成技術を用いて銅(Cu)からなる内部配
線用導体層を形成し、フォトリソグラフィ法により微細
なパターンの配線導体を形成して、この絶縁層と配線導
体とを多層化することにより高密度・高機能でかつ半導
体素子の高速作動が可能となる多層配線基板を得ること
も行なわれていた。
Further, with the increase in the speed of electric signals handled by the multilayer wiring board, the insulating layer is replaced with alumina ceramics having a relative dielectric constant of about 10, and a polyimide resin or epoxy resin having a relatively small relative dielectric constant of 3.5 to 5 is used. And a conductive layer for internal wiring made of copper (Cu) is formed on the insulating layer by using a thin film forming technique such as a vapor deposition method such as a vapor deposition method or a sputtering method. By forming a wiring conductor in a pattern and multiplying the insulating layer and the wiring conductor into layers, a multilayer wiring board having a high density, a high function and a high speed operation of a semiconductor element has been obtained.

【0005】一方、多層配線基板の内部配線の配線構造
として、配線のインピーダンスの低減や信号配線間のク
ロストークの低減等を図り、しかも高密度配線を実現す
るために、各絶縁層の上面に平行配線群を形成し、これ
を多層化して各層の配線群のうち所定の配線同士をビア
導体やスルーホール導体等の貫通導体を介して電気的に
接続する構造が提案されている。
On the other hand, the wiring structure of the internal wiring of the multilayer wiring board is designed to reduce the impedance of the wiring, reduce the crosstalk between signal wirings, etc. A structure has been proposed in which a group of parallel wirings is formed, which is multi-layered, and predetermined wirings in the wiring group of each layer are electrically connected to each other via through conductors such as via conductors and through-hole conductors.

【0006】このような平行配線群を有する多層配線基
板においては、この多層配線基板に搭載される半導体素
子等の電子部品とこの多層配線基板が実装される実装ボ
ードとを電気的に接続するために、多層配線基板内で各
平行配線群のうちから適当な配線を選択し、異なる配線
層間における配線同士の接続はビア導体等の貫通導体を
介して行なわれる。
In a multilayer wiring board having such parallel wiring groups, an electronic component such as a semiconductor element mounted on the multilayer wiring board is electrically connected to a mounting board on which the multilayer wiring board is mounted. Then, an appropriate wiring is selected from each parallel wiring group in the multilayer wiring board, and the connection between the wirings between different wiring layers is performed via a through conductor such as a via conductor.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、従来の
多層配線基板において各配線層を構成する平行配線群の
高密度化を図って各配線の間隔を狭く設定し、配線のい
わゆる狭ピッチ化を行なった場合には、信号配線の間隔
も狭くなって異なる高周波信号を伝送する信号配線同士
が近接することとなり、これら信号配線間における電磁
気的な結合力が強まり、その結果、平行配線群内におい
て信号配線間でクロストークが発生し、クロストークノ
イズが増大してしまうという問題点があった。
However, in the conventional multilayer wiring board, the spacing between the wirings is set to be narrow by increasing the density of the parallel wiring group constituting each wiring layer, and the so-called narrow pitch of the wirings is performed. In this case, the distance between the signal wirings is also narrowed, and the signal wirings for transmitting different high-frequency signals are close to each other, so that the electromagnetic coupling force between these signal wirings is strengthened. There is a problem that crosstalk occurs between wirings and crosstalk noise increases.

【0008】本発明は上記問題点に鑑み案出されたもの
であり、その目的は、交互に直交配置して積層され貫通
導体群で電気的に接続された平行配線群から成る積層配
線体を具備する多層配線基板において、平行配線群の配
線間隔を狭くして高密度化を図った場合であっても信号
配線間のクロストークを低減してクロストークノイズの
発生を抑制することができる、高速で作動する半導体集
積回路素子等の半導体素子を搭載する電子回路基板やパ
ッケージ等に好適な多層配線基板を提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a laminated wiring body composed of a group of parallel wirings which are alternately arranged in a stack and electrically connected by a group of through conductors. In the multi-layer wiring board provided, even when the wiring interval of the parallel wiring group is narrowed to increase the density, the crosstalk between the signal wirings can be reduced and the generation of crosstalk noise can be suppressed. An object of the present invention is to provide a multilayer wiring board suitable for an electronic circuit board or a package on which a semiconductor element such as a semiconductor integrated circuit element operating at a high speed is mounted.

【0009】[0009]

【課題を解決するための手段】本発明の多層配線基板
は、第1の平行配線群を有する第1の絶縁層上に、前記
第1の平行配線群と直交する第2の平行配線群を有する
第2の絶縁層を積層し、前記第1および第2の平行配線
群を貫通導体群で電気的に接続して成る積層配線体を具
備して成り、前記第1および第2の平行配線群はそれぞ
れ複数の信号配線と、各信号配線に隣接する電源配線ま
たは接地配線とを有するとともに、これら信号配線に隣
接する電源配線または接地配線の配線導体の厚みを前記
信号配線より厚くしたことを特徴とするものである。
According to the present invention, there is provided a multilayer wiring board comprising a second parallel wiring group orthogonal to the first parallel wiring group on a first insulating layer having the first parallel wiring group. A first insulating layer having a first insulating layer, a first insulating layer, a first insulating layer, and a second insulating layer. Each of the groups has a plurality of signal wirings, a power supply wiring or a ground wiring adjacent to each signal wiring, and a wiring conductor of the power supply wiring or the ground wiring adjacent to these signal wirings is thicker than the signal wiring. It is a feature.

【0010】本発明の多層配線基板によれば、第1およ
び第2の平行配線群がそれぞれ複数の信号配線と、各信
号配線に隣接する電源配線または接地配線とを有すると
ともに、これら信号配線に隣接する電源配線または接地
配線の配線導体の厚みを信号配線より厚くしたことか
ら、信号配線間に位置するこれら配線導体の厚みの厚い
電源配線または接地配線によって信号配線間の電磁気的
な結合力が弱められるため、平行配線群内の信号配線間
におけるクロストークを低減してクロストークノイズの
発生を抑制することができる。
According to the multilayer wiring board of the present invention, the first and second parallel wiring groups each have a plurality of signal wirings, a power supply wiring or a ground wiring adjacent to each signal wiring, and the signal wirings Since the thickness of the wiring conductor of the adjacent power supply wiring or ground wiring is made thicker than that of the signal wiring, the thicker power supply wiring or ground wiring located between the signal wirings reduces the electromagnetic coupling force between the signal wirings. Since it is weakened, it is possible to reduce crosstalk between signal wirings in the parallel wiring group and suppress occurrence of crosstalk noise.

【0011】これにより、本発明の多層配線基板によれ
ば、交互に直交配置して積層され貫通導体群で電気的に
接続された平行配線群から成る積層配線体を具備する多
層配線基板において、平行配線群の配線間隔を狭くして
高密度化を図った場合であっても信号配線間のクロスト
ークを低減してクロストークノイズの発生を抑制するこ
とができる、高速で作動する半導体集積回路素子等の半
導体素子を搭載する電子回路基板やパッケージ等に好適
な多層配線基板となる。
Thus, according to the multilayer wiring board of the present invention, there is provided a multilayer wiring board having a multilayer wiring body composed of a group of parallel wirings alternately arranged orthogonally and stacked and electrically connected by a group of through conductors. A high-speed semiconductor integrated circuit that can reduce the crosstalk between signal wirings and suppress the occurrence of crosstalk noise even when the density of the parallel wiring groups is reduced by reducing the wiring interval. A multilayer wiring board suitable for an electronic circuit board, a package, or the like on which a semiconductor element such as an element is mounted.

【0012】[0012]

【発明の実施の形態】以下、本発明の多層配線基板につ
いて添付図面に示す実施例に基づき詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

【0013】図1は本発明の多層配線基板に係る積層配
線体の実施の形態の一例を示すものであり、同図(a)
は第1の絶縁層の、(b)は第2の絶縁層の要部平面図
をそれぞれ示している。また、図2はこれらを積層して
成る積層配線体を含む本発明の多層配線基板の実施の形
態の一例を示す要部平面図である。さらに、図3は図2
に示す多層配線基板のA−A’線断面図である。
FIG. 1 shows an example of an embodiment of a laminated wiring body according to the multilayer wiring board of the present invention.
3B is a plan view of a main part of the first insulating layer, and FIG. 3B is a plan view of a main part of the second insulating layer. FIG. 2 is a plan view of an essential part showing an example of an embodiment of a multilayer wiring board of the present invention including a laminated wiring body obtained by laminating them. Further, FIG.
FIG. 3 is a sectional view taken along line AA ′ of the multilayer wiring board shown in FIG.

【0014】これらの図において、I1〜I3はそれぞ
れ第1〜第3の絶縁層であり、L1およびL2はそれぞ
れ第1および第2の絶縁層I1・I2の上面に略平行に
配設された第1および第2の平行配線群である。第2の
平行配線群L2は第1の平行配線群L1に対して各配線
導体が直交するように配設されている。
In these figures, I1 to I3 are first to third insulating layers, respectively, and L1 and L2 are disposed substantially parallel to the upper surfaces of the first and second insulating layers I1 and I2, respectively. These are the first and second parallel wiring groups. The second parallel wiring group L2 is arranged such that each wiring conductor is orthogonal to the first parallel wiring group L1.

【0015】P1・P2はそれぞれ第1・第2の平行配
線群L1・L2中の電源配線、G1・G2はそれぞれ第
1・第2の平行配線群L1・L2中の接地配線、S1・
S2はそれぞれ第1・第2の平行配線群L1・L2中の
信号配線を示している。
P1 and P2 are power supply wirings in the first and second parallel wiring groups L1 and L2, respectively, G1 and G2 are ground wirings in the first and second parallel wiring groups L1 and L2, respectively.
S2 indicates a signal wiring in the first and second parallel wiring groups L1 and L2, respectively.

【0016】また、Tは第1の平行配線群L1と第2の
平行配線群L2とを所定の箇所で電気的に接続する貫通
導体群である。
T is a through conductor group for electrically connecting the first parallel wiring group L1 and the second parallel wiring group L2 at a predetermined location.

【0017】このように、本発明の多層配線基板の積層
配線体においては、信号配線S1およびそれに隣接した
電源配線P1または接地配線G1を含む第1の平行配線
群L1は第1の方向に略平行に配線され、この上に積層
される同じく信号配線S2およびそれに隣接した電源配
線P2または接地配線G2を含む第2の平行配線群L2
は第1の方向と直交する第2の方向に略平行に配設され
ており、これらの各配線がそれぞれ第2の絶縁層I2を
貫通する貫通導体群Tで電気的に接続されて、積層配線
体を構成している。
As described above, in the laminated wiring body of the multilayer wiring board of the present invention, the first parallel wiring group L1 including the signal wiring S1 and the power supply wiring P1 or the ground wiring G1 adjacent thereto is substantially in the first direction. A second parallel wiring group L2 including a signal wiring S2 and a power supply wiring P2 or a ground wiring G2 adjacent to the signal wiring S2 stacked in parallel and stacked thereon.
Are disposed substantially parallel to a second direction orthogonal to the first direction, and these wirings are electrically connected to each other by a through conductor group T penetrating through the second insulating layer I2 to form a laminate. It constitutes a wiring body.

【0018】このような積層配線体によれば、第1の平
行配線群L1と第2の平行配線群L2とが直交するよう
に積層されていることから、それら平行配線群L1・L
2の配線間におけるクロストークノイズを減少させて最
小とすることができる。
According to such a stacked wiring body, since the first parallel wiring group L1 and the second parallel wiring group L2 are stacked so as to be orthogonal to each other, the parallel wiring groups L1 and L
Crosstalk noise between the two wirings can be reduced to a minimum.

【0019】なお、同じ平面に配設された複数の信号配
線S1・S2はそれぞれ異なる信号を伝送するものとし
てもよく、同じ平面に配設された複数の電源配線P1・
P2はそれぞれ異なる電源を供給するものとしてもよ
い。
The plurality of signal lines S1 and S2 arranged on the same plane may transmit different signals, respectively, and the plurality of power lines P1 and S1 arranged on the same plane may be used.
P2 may supply different powers.

【0020】I3は第2の絶縁層I2の上に積層され、
多層配線基板の表面層となる第3の絶縁層である。この
第3の絶縁層I3は必要に応じて形成されるものであ
り、例えば第2の平行配線群L2が第2の絶縁層I2中
に配設される場合等には必ずしも形成する必要はない。
I3 is laminated on the second insulating layer I2,
This is a third insulating layer to be a surface layer of the multilayer wiring board. The third insulating layer I3 is formed as needed. For example, when the second parallel wiring group L2 is provided in the second insulating layer I2, the third insulating layer I3 is not necessarily formed. .

【0021】このような多層配線基板には、例えばその
表面にMPU(Micro Processing Unit)・ASIC(A
pplication Specific Integrated Circuit)・DSP
(Digital Signal Processor)のような半導体集積回路
素子等の半導体素子が搭載される。そして、半導体素子
収納用パッケージや半導体素子搭載用基板、多数の半導
体集積回路素子が搭載されるいわゆるマルチチップモジ
ュールやマルチチップパッケージ、マザーボード等とし
て使用される。これらの半導体素子は、例えばいわゆる
バンプ電極によりこの多層配線基板の表面に実装され
て、あるいは接着剤・ろう材等により搭載部に取着され
るとともにボンディングワイヤ等を介して、貫通導体等
により例えば第2の平行配線群L2と電気的に接続され
る。なお、外部電気回路との接続部ならびに搭載される
半導体素子との接続部は図示していない。
In such a multilayer wiring board, for example, an MPU (Micro Processing Unit) / ASIC (A
pplication Specific Integrated Circuit) ・ DSP
A semiconductor device such as a semiconductor integrated circuit device such as a digital signal processor (Digital Signal Processor) is mounted. Then, it is used as a package for storing semiconductor elements, a substrate for mounting semiconductor elements, a so-called multi-chip module or multi-chip package on which a large number of semiconductor integrated circuit elements are mounted, a motherboard, or the like. These semiconductor elements are mounted on the surface of the multilayer wiring board by, for example, so-called bump electrodes, or are attached to a mounting portion by an adhesive, a brazing material, or the like, and are connected to the mounting portion via a bonding wire, for example, by a through conductor. It is electrically connected to the second parallel wiring group L2. A connection portion with an external electric circuit and a connection portion with a mounted semiconductor element are not shown.

【0022】貫通導体群Tは、第2の絶縁層I2を貫通
して上下の配線同士を電気的に接続するものであり、通
常はスルーホール導体やビア導体等が用いられ、接続に
必要な箇所に形成される。同様の貫通導体群は、各平行
配線群L1・L2の配線と電子部品または多層配線基板
の表面に取着された外部接続端子等とを電気的に接続す
る場合にも用いられる。
The through conductor group T penetrates through the second insulating layer I2 to electrically connect the upper and lower wirings. Usually, a through-hole conductor, a via conductor, or the like is used, and the necessary conductors for the connection are used. Formed at the location. A similar through conductor group is also used to electrically connect the wiring of each of the parallel wiring groups L1 and L2 to an electronic component or an external connection terminal attached to the surface of the multilayer wiring board.

【0023】そして、本発明の多層配線基板において
は、図1〜図3に示すように、第1および第2の平行配
線群L1・L2はそれぞれ複数の信号配線S1・S2
と、各信号配線S1・S2に隣接する電源配線P1・P
2または接地配線G1・G2とを有するとともに、これ
ら信号配線S1・S2に隣接する電源配線P1・P2ま
たは接地配線G1・G2の配線導体の厚みを信号配線S
1・S2の配線導体の厚みより厚くしている。これによ
り、同じ平行配線群L1・L2内で隣接することとなる
信号配線S1間ならびにS2間の電磁気的な結合力は、
その間に位置する厚みの厚い配線導体で形成された電源
配線P1・P2または接地配線G1・G2によって弱め
られるため、これら信号配線S1間ならびにS2間のク
ロストークを低減して信号配線S1・S2において発生
するクロストークノイズを大幅に減少させることができ
る。
In the multilayer wiring board according to the present invention, as shown in FIGS. 1 to 3, the first and second parallel wiring groups L1 and L2 each include a plurality of signal wirings S1 and S2.
And power supply lines P1 and P adjacent to the signal lines S1 and S2.
2 and the ground wirings G1 and G2, and the thickness of the wiring conductors of the power wirings P1 and P2 or the ground wirings G1 and G2 adjacent to the signal wirings S1 and S2 is set to the signal wiring S.
The thickness is larger than the thickness of the wiring conductor of 1.S2. As a result, the electromagnetic coupling force between the signal lines S1 and S2 adjacent to each other in the same parallel wiring group L1 and L2 becomes
Since the power lines P1 and P2 or the ground lines G1 and G2 formed by thick wiring conductors located therebetween are weakened, crosstalk between the signal lines S1 and S2 is reduced to reduce the signal lines S1 and S2. The generated crosstalk noise can be greatly reduced.

【0024】本発明の多層配線基板においてこのように
配線導体の厚みを厚くした電源配線P1・P2または接
地配線G1・G2を配設する場合、その電源配線P1・
P2または接地配線G1・G2の配線導体の厚みは、効
率よくクロストークを低減させるためには、その幅や信
号配線S1・S2との間隔、信号配線S1・S2に対す
る長さ等は、各平行配線群L1・L2および各貫通導体
Tの各部の寸法や形状・材料に基づく電気的な特性およ
び高周波に対する電磁気的な特性等を考慮して、また信
号配線S1・S2について所望の特性インピーダンスが
得られるように考慮して適宜設定すればよい。
In the multilayer wiring board of the present invention, when the power supply wirings P1 and P2 or the grounding wirings G1 and G2 having the thicker wiring conductors are provided, the power supply wiring P1.
In order to reduce the crosstalk efficiently, the thickness of the wiring conductor of the P2 or the ground wirings G1 and G2 is set such that the width, the distance between the signal wirings S1 and S2, the length with respect to the signal wirings S1 and S2, and the like are parallel. A desired characteristic impedance is obtained for the signal lines S1 and S2 in consideration of the electrical characteristics based on the size, shape, and material of each part of the wiring groups L1 and L2 and each through conductor T, the electromagnetic characteristics for high frequencies, and the like. It may be set appropriately in consideration of the situation.

【0025】そして、これら電源配線P1・P2または
接地配線G1・G2の配線導体の厚みは、信号配線S1
間ならびにS2間のクロストークを最も効果的に低減す
る観点からは、第1および第2の平行配線群L1・L2
において対象となる隣接する信号配線S1・S2の配線
導体の厚みに対して約1.2倍から約2倍程度の厚みとす
ることが好ましい。この厚みが約1.2倍を下回ると、信
号配線S1間ならびにS2間の電磁気的な結合力がほと
んど弱められず、クロストークが充分に低減できなくな
って、クロストークノイズの大きさで5%程度未満と不
十分な程度しか低減できなくなる傾向がある。他方、信
号配線S1・S2の厚みの約2倍を大きく上回ると、多
層配線基板を構成する際に第1および第2の平行配線群
L1・L2を挟んで積層される第1および第2の絶縁層
I1・I2間の密着性が不十分となって多層配線基板の
作製が困難となる傾向がある。
The thickness of the wiring conductors of the power supply wirings P1 and P2 or the grounding wirings G1 and G2 is determined by the thickness of the signal wiring S1.
From the viewpoint of most effectively reducing the crosstalk between S1 and S2, the first and second parallel wiring groups L1 and L2
In the above, it is preferable that the thickness be about 1.2 to about 2 times the thickness of the wiring conductor of the adjacent signal wiring S1 or S2 to be targeted. If the thickness is less than about 1.2 times, the electromagnetic coupling between the signal wirings S1 and S2 is hardly weakened, so that crosstalk cannot be sufficiently reduced, and the magnitude of crosstalk noise is less than about 5%. Tends to be reduced only to an insufficient degree. On the other hand, when the thickness is much more than about twice the thickness of the signal wirings S1 and S2, the first and second stacked layers sandwiching the first and second parallel wiring groups L1 and L2 when forming the multilayer wiring board. There is a tendency that the adhesion between the insulating layers I1 and I2 becomes insufficient and the production of the multilayer wiring board becomes difficult.

【0026】本発明の多層配線基板においては、例え
ば、各絶縁層I1〜I3に比誘電率ε rが約10の同じ誘
電体材料を用いて、絶縁層の厚みを254μm、基本とな
る配線幅を100μm、信号配線の厚みを14μm、信号配
線とこれに隣接する電源配線または接地配線との間の間
隔を200μmとして図1〜図3に示す積層配線体を構成
した場合、各信号配線S1・S2に隣接する電源配線P
1・P2または接地配線G1・G2の配線導体の厚みが
信号配線S1・S2の配線導体の厚みが同じ場合には、
信号配線S1・S2のクロストークノイズは7.79mVと
なる。これに対して、各信号配線S1・S2に隣接する
電源配線P1・P2または接地配線G1・G2の配線導
体の厚みが信号配線S1・S2の配線導体の厚みの2倍
にした場合には、信号配線S1・S2のクロストークノ
イズを6.4mVに低減することができる。
In the multilayer wiring board of the present invention, for example,
For example, the relative dielectric constant ε rBut about 10 same invitations
The thickness of the insulating layer is 254 μm using
Wiring width is 100 μm, signal wiring thickness is 14 μm,
Between a wire and its adjacent power or ground wire
The stacked wiring body shown in FIGS.
In this case, the power supply wiring P adjacent to each of the signal wirings S1 and S2
The thickness of the wiring conductor of 1 · P2 or the ground wiring G1 · G2 is
When the thickness of the signal conductors S1 and S2 is the same,
The crosstalk noise of the signal lines S1 and S2 is 7.79 mV.
Become. On the other hand, adjacent to each of the signal lines S1 and S2
Wiring of power supply lines P1 and P2 or ground lines G1 and G2
The thickness of the body is twice the thickness of the wiring conductors of the signal wiring S1 and S2
, The crosstalk noise of the signal lines S1 and S2
Noise can be reduced to 6.4 mV.

【0027】なお、以上の構成は、図1〜図3に示す例
に対して第1の平行配線群L1の下方や第2の平行配線
群L2の上方にも同様の平行配線群を直交させて積層配
置し、それらと貫通導体群で電気的に接続する場合につ
いても適用することができる。
In the above configuration, similar parallel wiring groups are orthogonally arranged below the first parallel wiring group L1 and above the second parallel wiring group L2 in the example shown in FIGS. The present invention can also be applied to a case where they are stacked and arranged and are electrically connected to them by a through conductor group.

【0028】また、本発明の多層配線基板に対しては、
第1および第2の平行配線群L1・L2の上下には、種
々の配線構造の多層配線部を積層して多層配線基板を構
成することができる。例えば、積層配線体と同様に平行
配線群を直交させて積層した構成の配線構造、あるいは
ストリップ線路構造の配線構造、その他、マイクロスト
リップ線路構造・コプレーナ線路構造等を多層配線基板
に要求される仕様等に応じて適宜選択して用いることが
できる。
Further, with respect to the multilayer wiring board of the present invention,
On and under the first and second parallel wiring groups L1 and L2, multilayer wiring portions having various wiring structures can be stacked to form a multilayer wiring board. For example, a wiring structure having a structure in which parallel wiring groups are orthogonally stacked like a multilayer wiring body, a wiring structure having a strip line structure, and other specifications required for a multi-layer wiring substrate such as a microstrip line structure and a coplanar line structure. It can be appropriately selected and used according to the conditions.

【0029】さらに、第1および第2の平行配線群L1
・L2の上下には、EMIノイズ等に対する電磁シール
ドとしての機能を有する接地導体層を配設してもよい。
Further, the first and second parallel wiring groups L1
A ground conductor layer having a function as an electromagnetic shield for EMI noise or the like may be provided above and below L2.

【0030】また例えば、ポリイミド絶縁層と銅蒸着に
よる導体層といったものを積層して電子回路を構成して
もよく、チップ抵抗・薄膜抵抗・コイルインダクタ・ク
ロスコンデンサ・チップコンデンサ・電解コンデンサと
いったものを取着して半導体素子収納用パッケージを構
成してもよい。
Further, for example, an electronic circuit may be formed by laminating a polyimide insulating layer and a conductor layer formed by copper vapor deposition, such as a chip resistor, a thin film resistor, a coil inductor, a cross capacitor, a chip capacitor, and an electrolytic capacitor. It may be attached to form a semiconductor element storage package.

【0031】また、第1〜第3の絶縁層I1〜I3を始
めとする各絶縁層の形状は、要部平面図で図示したよう
な略正方形状のものに限られるものではなく、長方形状
や菱形状・多角形状等の形状であってもよい。
The shape of each insulating layer including the first to third insulating layers I1 to I3 is not limited to a substantially square shape as shown in a plan view of a main part, but is a rectangular shape. Or a shape such as a rhombus or a polygon.

【0032】なお、第1および第2の平行配線群L1・
L2は、第1および第2の絶縁層I1・I2の表面に形
成するものに限られず、それぞれの絶縁層I1・I2の
内部に形成したものであってもよい。
Note that the first and second parallel wiring groups L1.
L2 is not limited to those formed on the surfaces of the first and second insulating layers I1 and I2, and may be formed inside the respective insulating layers I1 and I2.

【0033】また、図3あるいは図6に示す例に対し
て、第3の絶縁層I3を積層せず、第2の平行配線群L
2を第2の絶縁層I2の表面に形成して多層配線基板の
表面に露出させるようにしてもよい。
Further, as compared with the example shown in FIG. 3 or FIG. 6, the third insulating layer I3 is not laminated and the second parallel wiring group L
2 may be formed on the surface of the second insulating layer I2 to be exposed on the surface of the multilayer wiring board.

【0034】本発明の多層配線基板において、第1〜第
3の絶縁層I1〜I3の各絶縁層は、例えばセラミック
グリーンシート積層法によって、酸化アルミニウム質焼
結体や窒化アルミニウム質焼結体・炭化珪素質焼結体・
窒化珪素質焼結体・ムライト質焼結体・ガラスセラミッ
クス等の無機絶縁材料を使用して、あるいはポリイミド
・エポキシ樹脂・フッ素樹脂・ポリノルボルネン・ベン
ゾシクロブテン等の有機絶縁材料を使用して、あるいは
セラミックス粉末等の無機絶縁物粉末をエポキシ系樹脂
等の熱硬化性樹脂で結合して成る複合絶縁材料などの電
気絶縁材料を使用して形成される。
In the multilayer wiring board of the present invention, each of the first to third insulating layers I1 to I3 is formed of an aluminum oxide sintered body or an aluminum nitride sintered body by, for example, a ceramic green sheet laminating method. Silicon carbide sintered body
Using inorganic insulating materials such as silicon nitride sintered body, mullite sintered body, glass ceramics, or organic insulating materials such as polyimide, epoxy resin, fluororesin, polynorbornene, benzocyclobutene, Alternatively, it is formed using an electrical insulating material such as a composite insulating material formed by bonding an inorganic insulating powder such as a ceramic powder with a thermosetting resin such as an epoxy resin.

【0035】これら絶縁層は、例えば酸化アルミニウム
質焼結体から成る場合であれば、酸化アルミニウム・酸
化珪素・酸化カルシウム・酸化マグネシウム等の原料粉
末に適当な有機バインダ・溶剤等を添加混合して泥漿状
となすとともに、これを従来周知のドクターブレード法
を採用してシート状となすことによってセラミックグリ
ーンシートを得て、しかる後、これらのセラミックグリ
ーンシートに適当な打ち抜き加工を施すとともに各平行
配線群および各貫通導体群ならびに導体層となる金属ペ
ーストを所定のパターンに印刷塗布して上下に積層し、
最後にこの積層体を還元雰囲気中、約1600℃の温度で焼
成することによって製作される。
When these insulating layers are made of, for example, an aluminum oxide sintered body, a suitable organic binder, a solvent, etc. are added to a raw material powder of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide or the like and mixed. A ceramic green sheet was obtained by forming the sheet into a sheet shape by employing a well-known doctor blade method, and thereafter, the ceramic green sheet was subjected to an appropriate punching process and each parallel wiring was formed. The group and each through conductor group and the metal paste to be the conductor layer are printed and applied in a predetermined pattern and laminated vertically,
Finally, the laminate is manufactured by firing at a temperature of about 1600 ° C. in a reducing atmosphere.

【0036】これら絶縁層の厚みとしては、使用する材
料の特性に応じて、要求される仕様に対応する機械的強
度や電気的特性・貫通導体群の形成の容易さ等の条件を
満たすように適宜設定される。
The thickness of these insulating layers is determined in accordance with the characteristics of the material to be used, so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications and the ease of forming the through conductor group. It is set appropriately.

【0037】また、第1および第2の平行配線群L1・
L2やその他の配線層および接地導体層GLならびに貫
通導体群等は、例えばタングステンやモリブデン・モリ
ブデン−マンガン・銅・銀・銀−パラジウム等の金属粉
末メタライズ、あるいは銅・銀・ニッケル・クロム・チ
タン・金・ニオブやそれらの合金等の金属材料の薄膜な
どから成る。
The first and second parallel wiring groups L1.
L2 and other wiring layers, ground conductor layers GL, through conductor groups, and the like are made of metal powder metallized, for example, tungsten, molybdenum, molybdenum-manganese, copper, silver, silver-palladium, or copper, silver, nickel, chrome, titanium. -It is composed of a thin film of a metal material such as gold, niobium, or an alloy thereof.

【0038】例えば、タングステンの金属粉末メタライ
ズから成る場合であれば、タングステン粉末に適当な有
機バインダ・溶剤等を添加混合して得た金属ペーストを
絶縁層となるセラミックグリーンシートに所定のパター
ンに印刷塗布し、これをセラミックグリーンシートの積
層体とともに焼成することによって、各絶縁層の上面に
配設される。
For example, in the case of metallization of metal powder of tungsten, a metal paste obtained by adding and mixing an appropriate organic binder, solvent and the like to the tungsten powder is printed in a predetermined pattern on a ceramic green sheet serving as an insulating layer. By applying and firing this together with the ceramic green sheet laminate, it is disposed on the upper surface of each insulating layer.

【0039】また、金属材料の薄膜から成る場合であれ
ば、例えばスパッタリング法・真空蒸着法またはメッキ
法により金属層を形成した後、フォトリソグラフィ法に
より所定の配線パターンに形成される。
In the case of a thin film of a metal material, a metal layer is formed by, for example, a sputtering method, a vacuum evaporation method, or a plating method, and then a predetermined wiring pattern is formed by a photolithography method.

【0040】第1および第2の平行配線群L1・L2の
各配線の幅および配線間の間隔、あるいは貫通導体群T
の形状や寸法・配設位置等は、使用する材料の特性に応
じて、要求される仕様に対応する電気的特性や絶縁層I
1・I2への配設の容易さ等の条件を満たすように適宜
設定される。
The width and the interval between the wirings of the first and second parallel wiring groups L1 and L2, or the through conductor group T
The shape, dimensions, arrangement position, etc. of the insulation layer I and the electrical characteristics corresponding to the required specifications depend on the characteristics of the material used.
It is set appropriately so as to satisfy conditions such as ease of disposition in 1.I2.

【0041】なお、各平行配線群L1・L2の厚みは1
〜20μm程度とすることが好ましい。この厚みが1μm
未満となると配線の抵抗が大きくなるため、配線群によ
る半導体素子への良好な電源供給や安定したグランドの
確保・良好な信号の伝搬が困難となる傾向が見られる。
他方、20μmを超えるとその上に積層される絶縁層によ
る被覆が不十分となって絶縁不良となる場合がある。
The thickness of each of the parallel wiring groups L1 and L2 is 1
It is preferably about 20 μm. This thickness is 1 μm
When the value is less than the above, the resistance of the wiring increases, and it tends to be difficult to provide a good power supply to the semiconductor element by the wiring group, secure a stable ground, and propagate a good signal.
On the other hand, if it exceeds 20 μm, the insulation layer laminated thereon may be insufficiently covered, resulting in poor insulation.

【0042】貫通導体群Tの各貫通導体は、横断面形状
が円形のものの他にも楕円形や正方形・長方形等の矩
形、その他の異形状のものを用いてもよい。その位置や
大きさは、使用する材料の特性に応じて、要求される仕
様に対応する電気的特性や絶縁層への形成・配設の容易
さ等の条件を満たすように適宜設定される。
Each of the through conductors in the through conductor group T may have a rectangular cross section other than a circular cross section, a rectangular shape such as an elliptical shape, a square or a rectangular shape, or any other shape. The position and size are appropriately set according to the characteristics of the material to be used so as to satisfy conditions such as electrical characteristics corresponding to required specifications and easiness of formation and arrangement on the insulating layer.

【0043】例えば、絶縁層に酸化アルミニウム質焼結
体を用い、平行配線群にタングステンの金属メタライズ
を用いた場合であれば、絶縁層の厚みを200μmとし、
配線の線幅を100μm、配線間の間隔を150μm、貫通導
体の大きさを100μmとすることによって、信号配線の
インピーダンスを50Ωとし、上下の平行配線群間を高周
波信号の反射を抑えつつ電気的に接続することができ
る。
For example, when the aluminum oxide sintered body is used for the insulating layer and the metallization of tungsten is used for the parallel wiring group, the thickness of the insulating layer is set to 200 μm.
By setting the line width of the wiring to 100 μm, the spacing between the wirings to 150 μm, and the size of the through conductor to 100 μm, the impedance of the signal wiring is set to 50Ω, and the electrical connection between the upper and lower parallel wiring groups is suppressed while suppressing the reflection of high-frequency signals. Can be connected to

【0044】なお、本発明は以上の実施の形態の例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
で種々の変更を加えることは何ら差し支えない。例え
ば、上述の実施例では本発明を半導体素子を搭載する多
層配線基板として説明したが、これを半導体素子を収容
する半導体素子収納用パッケージや、あるいはマルチチ
ップモジュールに適用するものとしてもよい。また、放
熱を考慮した窒化アルミニウム質焼結体・炭化珪素質焼
結体や、低誘電率を考慮したガラスセラミックス質焼結
体を用いたものとしてもよい。
It should be noted that the present invention is not limited to the above-described embodiments, and that various changes may be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the present invention has been described as a multilayer wiring board on which a semiconductor element is mounted. However, the present invention may be applied to a semiconductor element housing package for housing a semiconductor element or a multi-chip module. Further, an aluminum nitride-based sintered body / silicon carbide-based sintered body considering heat dissipation or a glass ceramics-based sintered body considering low dielectric constant may be used.

【0045】[0045]

【発明の効果】本発明の多層回路基板によれば、第1お
よび第2の平行配線群がそれぞれ複数の信号配線と、各
信号配線に隣接する電源配線または接地配線とを有する
とともに、これら信号配線に隣接する電源配線または接
地配線の配線導体の厚みを信号配線より厚くしたことか
ら、信号配線間に位置するこれら配線導体の厚みの厚い
電源配線または接地配線によって信号配線間の電磁気的
な結合力が弱められるため、平行配線群内の信号配線間
におけるクロストークを低減してクロストークノイズの
発生を抑制することができる。
According to the multilayer circuit board of the present invention, each of the first and second parallel wiring groups has a plurality of signal wirings and a power supply wiring or a ground wiring adjacent to each signal wiring. Since the thickness of the wiring conductor of the power supply wiring or the ground wiring adjacent to the wiring is thicker than that of the signal wiring, the electromagnetic coupling between the signal wirings is provided by the thick power supply wiring or the ground wiring located between the signal wirings. Since the force is weakened, it is possible to reduce the crosstalk between the signal wirings in the parallel wiring group and suppress the generation of crosstalk noise.

【0046】以上により、本発明の多層配線基板によれ
ば、交互に直交配置して積層され貫通導体群で電気的に
接続された平行配線群から成る積層配線体を具備する多
層配線基板において、平行配線群の配線間隔を狭くして
高密度化を図った場合であっても信号配線間のクロスト
ークを低減してクロストークノイズの発生を抑制するこ
とができる、高速で作動する半導体集積回路素子等の半
導体素子を搭載する電子回路基板やパッケージ等に好適
な多層配線基板となる。
As described above, according to the multilayer wiring board of the present invention, there is provided a multilayer wiring board having a multilayer wiring body composed of a group of parallel wirings which are alternately arranged and stacked orthogonally and are electrically connected by a group of through conductors. A high-speed semiconductor integrated circuit that can reduce the crosstalk between signal wirings and suppress the occurrence of crosstalk noise even when the density of the parallel wiring groups is reduced by reducing the wiring interval. A multilayer wiring board suitable for an electronic circuit board, a package, or the like on which a semiconductor element such as an element is mounted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板に係る積層配線体の実施
の形態の一例を示すものであり、(a)は第1の絶縁層
の、(b)は第2の絶縁層の要部平面図を示す。
FIGS. 1A and 1B show an example of an embodiment of a multilayer wiring body according to a multilayer wiring board of the present invention, wherein FIG. 1A shows a first insulating layer, and FIG. 1B shows a main part of a second insulating layer. FIG.

【図2】本発明の多層配線基板の実施の形態の一例を示
す要部平面図である。
FIG. 2 is a main part plan view showing an example of an embodiment of a multilayer wiring board of the present invention.

【図3】図2に示す多層配線基板のA−A’線断面図で
ある。
FIG. 3 is a sectional view taken along line AA ′ of the multilayer wiring board shown in FIG. 2;

【符号の説明】[Explanation of symbols]

I1〜I3・・・・絶縁層 L1、L2・・・・平行配線群 P1、P2・・・・電源配線 G1、G2・・・・接地配線 S1、S2・・・・信号配線 T・・・・・・・・貫通導体群 ... I1 to I3... Insulating layer L1, L2... Parallel wiring group P1, P2... Power supply wiring G1, G2... Ground wiring S1, S2. ..... Groups of through conductors

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1の平行配線群を有する第1の絶縁層
上に、前記第1の平行配線群と直交する第2の平行配線
群を有する第2の絶縁層を積層し、前記第1および第2
の平行配線群を貫通導体群で電気的に接続して成る積層
配線体を具備して成り、前記第1および第2の平行配線
群はそれぞれ複数の信号配線と、各信号配線に隣接する
電源配線または接地配線とを有するとともに、これら信
号配線に隣接する電源配線または接地配線の配線導体の
厚みを前記信号配線より厚くしたことを特徴とする多層
配線基板。
1. A second insulating layer having a second parallel wiring group orthogonal to the first parallel wiring group is laminated on a first insulating layer having a first parallel wiring group. 1st and 2nd
And a plurality of signal wirings, and a power supply adjacent to each signal wiring. The first and second parallel wiring groups each include a plurality of signal wirings. A multilayer wiring board having a wiring or a ground wiring, wherein the thickness of a wiring conductor of a power supply wiring or a ground wiring adjacent to the signal wiring is larger than that of the signal wiring.
JP2000240985A 2000-08-09 2000-08-09 Multilayered printed circuit board Pending JP2002057462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000240985A JP2002057462A (en) 2000-08-09 2000-08-09 Multilayered printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000240985A JP2002057462A (en) 2000-08-09 2000-08-09 Multilayered printed circuit board

Publications (1)

Publication Number Publication Date
JP2002057462A true JP2002057462A (en) 2002-02-22

Family

ID=18732255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000240985A Pending JP2002057462A (en) 2000-08-09 2000-08-09 Multilayered printed circuit board

Country Status (1)

Country Link
JP (1) JP2002057462A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340578A (en) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd Circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340578A (en) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd Circuit device
JP4511245B2 (en) * 2004-05-28 2010-07-28 三洋電機株式会社 Circuit equipment

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