JP2002057461A - Multilayered printed circuit board - Google Patents

Multilayered printed circuit board

Info

Publication number
JP2002057461A
JP2002057461A JP2000240984A JP2000240984A JP2002057461A JP 2002057461 A JP2002057461 A JP 2002057461A JP 2000240984 A JP2000240984 A JP 2000240984A JP 2000240984 A JP2000240984 A JP 2000240984A JP 2002057461 A JP2002057461 A JP 2002057461A
Authority
JP
Japan
Prior art keywords
wiring
signal
conductor
conductors
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000240984A
Other languages
Japanese (ja)
Inventor
Ryuji Mori
隆二 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000240984A priority Critical patent/JP2002057461A/en
Publication of JP2002057461A publication Critical patent/JP2002057461A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally crosswalk noise larger than that between signal wirings of a parallel wiring group is generated between feedthrough adjacent conductors for signals in a multilayer printed circuit board, having the parallel wiring group. SOLUTION: In the multilayered printed circuit board, a second insulating layer I2, having a second parallel wiring group L2 perpendicular to a first parallel wiring group L1, is laminated on a first insulating layer I1 having the first group L1. The first and second groups L1 and L2 are connected via a feedthrough conductor group T. The groups L1 and L2 respectively have signal wirings S1 and S2 and power wirings P1 and P2 or ground wirings G1 and G2. An auxiliary feedthrough conductor Ts, connected at one end to the wiring G1 interposed between conductors T1 for the signals and opened at he other end, is arranged between the conductors T1 for respectively connecting the two adjacent signal wirings S1 via the wiring G1 to corresponding signal wiring S2. Thus, crosswalks between the conductors T1 can be reduced effectively.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電子回路基板等に使
用される多層配線基板に関し、より詳細には高速で作動
する半導体素子を搭載する多層配線基板における配線構
造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board used for an electronic circuit board or the like, and more particularly to a wiring structure in a multilayer wiring board on which a semiconductor element operating at a high speed is mounted.

【0002】[0002]

【従来の技術】従来、半導体集積回路素子等の半導体素
子が搭載され、電子回路基板等に使用される多層配線基
板においては、内部配線用の配線導体の形成にあたっ
て、アルミナ等のセラミックスから成る絶縁層とタング
ステン(W)等の高融点金属から成る配線導体とを交互
に積層して多層配線基板を形成していた。
2. Description of the Related Art Conventionally, in a multilayer wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted and which is used for an electronic circuit board or the like, an insulating material made of ceramics such as alumina is used for forming a wiring conductor for internal wiring. Layers and wiring conductors made of a refractory metal such as tungsten (W) are alternately stacked to form a multilayer wiring board.

【0003】従来の多層配線基板においては、内部配線
用配線導体のうち信号配線は通常はストリップ線路構造
とされており、信号配線として形成された配線導体の上
下に絶縁層を介していわゆるベタパターン形状の広面積
の接地(グランド)層または電源層が形成されていた。
In a conventional multilayer wiring board, signal wirings of internal wiring wiring conductors usually have a strip line structure, and a so-called solid pattern is formed above and below wiring conductors formed as signal wirings via insulating layers. A ground (ground) layer or a power supply layer having a wide area of the shape was formed.

【0004】また、多層配線基板が取り扱う電気信号の
高速化に伴い、絶縁層を比誘電率が10程度であるアルミ
ナセラミックスに代えて比誘電率が3.5 〜5と比較的小
さいポリイミド樹脂やエポキシ樹脂を用いて形成し、こ
の絶縁層上に蒸着法やスパッタリング法等の気相成長法
による薄膜形成技術を用いて銅(Cu)からなる内部配
線用導体層を形成し、フォトリソグラフィ法により微細
なパターンの配線導体を形成して、この絶縁層と配線導
体とを多層化することにより高密度・高機能でかつ半導
体素子の高速作動が可能となる多層配線基板を得ること
も行なわれていた。
Further, with the increase in the speed of electric signals handled by the multilayer wiring board, the insulating layer is replaced with alumina ceramics having a relative dielectric constant of about 10, and a polyimide resin or epoxy resin having a relatively small relative dielectric constant of 3.5 to 5 is used. And a conductive layer for internal wiring made of copper (Cu) is formed on the insulating layer by using a thin film forming technique such as a vapor deposition method such as a vapor deposition method or a sputtering method. By forming a wiring conductor in a pattern and multiplying the insulating layer and the wiring conductor into layers, a multilayer wiring board having a high density, a high function and a high speed operation of a semiconductor element has been obtained.

【0005】一方、多層配線基板の内部配線の配線構造
として、配線のインピーダンスの低減や信号配線間のク
ロストークの低減等を図り、しかも高密度配線を実現す
るために、各絶縁層の上面に平行配線群を形成し、これ
を多層化して各層の配線群のうち所定の配線同士をビア
導体やスルーホール導体等の貫通導体を介して電気的に
接続する構造が提案されている。
On the other hand, the wiring structure of the internal wiring of the multilayer wiring board is designed to reduce the impedance of the wiring, reduce the crosstalk between signal wirings, etc. A structure has been proposed in which a group of parallel wirings is formed, which is multi-layered, and predetermined wirings in the wiring group of each layer are electrically connected to each other via through conductors such as via conductors and through-hole conductors.

【0006】このような平行配線群を有する多層配線基
板においては、この多層配線基板に搭載される半導体素
子等の電子部品とこの多層配線基板が実装される実装ボ
ードとを電気的に接続するために、多層配線基板内で各
平行配線群のうちから適当な配線を選択し、異なる配線
層間における配線同士の接続はビア導体等の貫通導体を
介して行なわれる。
In a multilayer wiring board having such parallel wiring groups, an electronic component such as a semiconductor element mounted on the multilayer wiring board is electrically connected to a mounting board on which the multilayer wiring board is mounted. Then, an appropriate wiring is selected from each parallel wiring group in the multilayer wiring board, and the connection between the wirings between different wiring layers is performed via a through conductor such as a via conductor.

【0007】[0007]

【発明が解決しようとする課題】従来の多層配線基板に
おいて上下の配線層の信号配線同士を貫通導体を介して
電気的に接続する場合には、異なる高周波信号を伝送す
る多数の信号配線同士をそれぞれ信号用貫通導体でもっ
て接続して配線回路網が形成されることとなる。
In the conventional multilayer wiring board, when the signal wirings of the upper and lower wiring layers are electrically connected to each other via the through conductor, a large number of signal wirings transmitting different high-frequency signals are connected to each other. The wiring circuit network is formed by being connected by the signal through conductors.

【0008】しかしながら、以上のような直交させた平
行配線群を有する多層配線基板においては、上下の平行
配線群間で信号配線同士を貫通導体により電気的に接続
する場合に、その信号用貫通導体同士が近接して配設さ
れるとその隣接する信号用貫通導体同士の電磁的な結合
力が強まり、その結果、平行配線群内における信号配線
同士に比べて信号用貫通導体間におけるクロストークが
大きくなってしまい、クロストークノイズが増大してし
まうという問題点があった。
However, in the multilayer wiring board having the above-described orthogonal wiring groups, when the signal wirings are electrically connected to each other by the through-conductors between the upper and lower parallel wiring groups, the signal through-conductors are not used. When they are arranged close to each other, the electromagnetic coupling force between the adjacent signal through conductors increases, and as a result, crosstalk between the signal through conductors as compared with the signal wires in the parallel wiring group increases. However, there is a problem that the crosstalk noise increases.

【0009】本発明は上記問題点に鑑み案出されたもの
であり、その目的は、交互に積層された平行配線群で上
下の平行配線群で信号配線同士を貫通導体により電気的
に接続する場合に、その近傍に所定の貫通導体を配設す
ることによってそれら信号用貫通導体間におけるクロス
トークを低減してクロストークノイズの発生を抑制する
ことができる、高速で作動する半導体集積回路素子等の
半導体素子を搭載する電子回路基板やパッケージ等に好
適な多層配線基板を提供することにある。
The present invention has been devised in view of the above problems, and has as its object to electrically connect signal wires to each other by through conductors in upper and lower parallel wiring groups of alternately stacked parallel wiring groups. In such a case, by arranging a predetermined through conductor in the vicinity thereof, it is possible to reduce crosstalk between the signal through conductors and suppress occurrence of crosstalk noise, and to operate a high speed semiconductor integrated circuit element. Another object of the present invention is to provide a multilayer wiring board suitable for an electronic circuit board, a package, and the like on which the semiconductor element is mounted.

【0010】[0010]

【課題を解決するための手段】本発明の多層配線基板
は、第1の平行配線群を有する第1の絶縁層上に、前記
第1の平行配線群と直交する第2の平行配線群を有する
第2の絶縁層を積層し、前記第1および第2の平行配線
群を貫通導体群で電気的に接続して成る積層配線体を具
備して成り、前記第1および第2の平行配線群はそれぞ
れ複数の信号配線と、各信号配線に隣接する電源配線ま
たは接地配線とを有するとともに、一方の平行配線群に
おいて前記電源配線または接地配線を挟んで隣接する2
つの前記信号配線を他方の平行配線群の対応する前記信
号配線にそれぞれ電気的に接続する信号用貫通導体間
に、これら信号用貫通導体間に挟まれた前記電源配線ま
たは接地配線に一端が電気的に接続され、他端が開放さ
れた補助貫通導体を前記第1および第2の平行配線群間
に配設したことを特徴とするものである。
According to the present invention, there is provided a multilayer wiring board comprising a second parallel wiring group orthogonal to the first parallel wiring group on a first insulating layer having the first parallel wiring group. A first insulating layer having a first insulating layer, a first insulating layer, a first insulating layer, and a second insulating layer. Each of the groups includes a plurality of signal wirings and a power supply wiring or a ground wiring adjacent to each signal wiring, and two parallel wiring groups adjacent to each other with the power supply wiring or the ground wiring interposed therebetween.
One end is electrically connected to the power supply wiring or the ground wiring interposed between the signal through conductors that electrically connect one of the signal wirings to the corresponding signal wiring of the other parallel wiring group. An auxiliary through conductor, which is electrically connected and the other end of which is open, is disposed between the first and second parallel wiring groups.

【0011】また、本発明の多層配線基板は、上記構成
において、前記補助貫通導体の大きさを、前記信号用貫
通導体より大きくしたことを特徴とするものである。
Further, in the multilayer wiring board according to the present invention, in the above structure, the size of the auxiliary through conductor is larger than that of the signal through conductor.

【0012】本発明の多層配線基板によれば、第1およ
び第2の平行配線群の信号配線同士であって、一方の平
行配線群において電源配線または接地配線を挟んで隣接
する2つの信号配線同士を他方の平行配線群の対応する
信号配線にそれぞれ電気的に接続する信号用貫通導体間
に、これら信号用貫通導体間に挟まれたその電源配線ま
たは接地配線に一端が電気的に接続され、他端が開放さ
れた補助貫通導体を前記第1および第2の平行配線群間
に配設したことから、これら信号用貫通導体間に配置さ
れたこれら信号用貫通導体に電気的に導通のない補助貫
通導体によって信号用貫通導体間の電磁気的な結合力が
弱められるため、信号用貫通導体間におけるクロストー
クを低減してクロストークノイズの発生を抑制すること
ができる。
According to the multilayer wiring board of the present invention, two signal wirings of the first and second parallel wiring groups adjacent to each other with the power supply wiring or the ground wiring interposed therebetween in one of the parallel wiring groups. One end is electrically connected to the power supply wiring or the ground wiring interposed between the signal through conductors, which are electrically connected to the corresponding signal wirings of the other parallel wiring group. Since the auxiliary through conductor having the other end opened is disposed between the first and second parallel wiring groups, the auxiliary through conductor is electrically connected to the signal through conductors disposed between the signal through conductors. Since the electromagnetic coupling force between the signal through conductors is weakened by the non-auxiliary through conductors, the crosstalk between the signal through conductors can be reduced and the generation of crosstalk noise can be suppressed.

【0013】これにより、本発明の多層配線基板によれ
ば、交互に積層された平行配線群について上下の平行配
線群間で信号配線同士を信号用貫通導体により電気的に
接続する場合に、その近傍に所定の位置関係で一方の平
行配線群の電源配線または接地配線に接続された他端開
放の補助貫通導体を配設したことで、それら信号用貫通
導体間におけるクロストークを低減してクロストークノ
イズの発生を抑制することができる、高速で作動する半
導体集積回路素子等の半導体素子を搭載する電子回路基
板やパッケージ等に好適な多層配線基板となる。
According to the multilayer wiring board of the present invention, when the signal wirings are electrically connected to each other by the signal through conductor between the upper and lower parallel wiring groups in the alternately stacked parallel wiring groups, By arranging an auxiliary through conductor open at the other end connected to the power supply wiring or the ground wiring of one of the parallel wiring groups in a predetermined positional relationship in the vicinity, crosstalk between these signal through conductors is reduced to reduce the crosstalk. A multilayer wiring board suitable for an electronic circuit board, a package, or the like on which a semiconductor element such as a semiconductor integrated circuit element operating at a high speed, which can suppress occurrence of talk noise, is provided.

【0014】[0014]

【発明の実施の形態】以下、本発明の多層配線基板につ
いて添付図面に示す実施例に基づき詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

【0015】図1は本発明の多層配線基板に係る積層配
線体の実施の形態の一例を示すものであり、同図(a)
は第1の絶縁層の、(b)は第2の絶縁層の要部平面図
をそれぞれ示している。また、図2はこれらを積層して
成る積層配線体を含む本発明の多層配線基板の実施の形
態の一例を示す要部平面図である。さらに、図3は図2
に示す多層配線基板のA−A’線断面図である。
FIG. 1 shows an example of an embodiment of a laminated wiring body according to the multilayer wiring board of the present invention, and FIG.
3B is a plan view of a main part of the first insulating layer, and FIG. 3B is a plan view of a main part of the second insulating layer. FIG. 2 is a plan view of an essential part showing an example of an embodiment of a multilayer wiring board of the present invention including a laminated wiring body obtained by laminating them. Further, FIG.
FIG. 3 is a sectional view taken along line AA ′ of the multilayer wiring board shown in FIG.

【0016】これらの図において、I1〜I3はそれぞ
れ第1〜第3の絶縁層であり、L1およびL2はそれぞ
れ第1および第2の絶縁層I1・I2の上面に略平行に
配設された第1および第2の平行配線群である。第2の
平行配線群L2は第1の平行配線群L1に対して各配線
導体が直交するように配設されている。
In these figures, I1 to I3 are first to third insulating layers, respectively, and L1 and L2 are disposed substantially parallel to the upper surfaces of the first and second insulating layers I1 and I2, respectively. These are the first and second parallel wiring groups. The second parallel wiring group L2 is arranged such that each wiring conductor is orthogonal to the first parallel wiring group L1.

【0017】P1・P2はそれぞれ第1・第2の平行配
線群L1・L2中の電源配線、G1・G2はそれぞれ第
1・第2の平行配線群L1・L2中の接地配線、S1・
S2はそれぞれ第1・第2の平行配線群L1・L2中の
信号配線を示している。
P1 and P2 are power supply wirings in the first and second parallel wiring groups L1 and L2, respectively, G1 and G2 are ground wirings in the first and second parallel wiring groups L1 and L2, respectively.
S2 indicates a signal wiring in the first and second parallel wiring groups L1 and L2, respectively.

【0018】また、Tは第1の平行配線群L1と第2の
平行配線群L2とを所定の箇所で電気的に接続する貫通
導体群であり、T1は信号配線S1とS2とを接続する
信号用貫通導体、T2は電源配線P1とP2とを、また
は接地配線G1とG2とを接続する電源/接地用貫通導
体を示している。
T is a through conductor group that electrically connects the first parallel wiring group L1 and the second parallel wiring group L2 at a predetermined location, and T1 connects the signal wirings S1 and S2. The signal through conductor T2 indicates a power / ground through conductor that connects the power lines P1 and P2 or the ground lines G1 and G2.

【0019】このように、本発明の多層配線基板の積層
配線体においては、信号配線S1およびそれに隣接した
電源配線P1または接地配線G1を含む第1の平行配線
群L1は第1の方向に略平行に配線され、この上に積層
される同じく信号配線S2およびそれに隣接した電源配
線P2または接地配線G2を含む第2の平行配線群L2
は第1の方向と直交する第2の方向に略平行に配設され
ており、これらの各配線がそれぞれ第2の絶縁層I2を
貫通する信号用貫通導体群T1ならびに電源/接地用貫
通導体群T2で電気的に接続されて、積層配線体を構成
している。
As described above, in the multilayer wiring body of the multilayer wiring board of the present invention, the first parallel wiring group L1 including the signal wiring S1 and the power supply wiring P1 or the ground wiring G1 adjacent thereto is substantially in the first direction. A second parallel wiring group L2 including a signal wiring S2 and a power supply wiring P2 or a ground wiring G2 adjacent to the signal wiring S2 stacked in parallel and stacked thereon.
Are disposed substantially parallel to a second direction orthogonal to the first direction, and each of these wirings penetrates through the second insulating layer I2, and includes a signal through conductor group T1 and a power / ground through conductor. They are electrically connected by the group T2 to form a laminated wiring body.

【0020】このような積層配線体によれば、第1の平
行配線群L1と第2の平行配線群L2とが直交するよう
に積層されていることから、それら平行配線群L1・L
2の配線間におけるクロストークノイズを減少させて最
小とすることができる。
According to such a stacked wiring body, since the first parallel wiring group L1 and the second parallel wiring group L2 are stacked so as to be orthogonal to each other, the parallel wiring groups L1 and L
Crosstalk noise between the two wirings can be reduced to a minimum.

【0021】なお、同じ平面に配設された複数の信号配
線S1・S2はそれぞれ異なる信号を伝送するものとし
てもよく、同じ平面に配設された複数の電源配線P1・
P2はそれぞれ異なる電源を供給するものとしてもよ
い。
The plurality of signal lines S1 and S2 arranged on the same plane may transmit different signals, respectively, and the plurality of power lines P1 and S1 arranged on the same plane may be used.
P2 may supply different powers.

【0022】I3は第2の絶縁層I2の上に積層され、
多層配線基板の表面層となる第3の絶縁層である。この
第3の絶縁層I3は必要に応じて形成されるものであ
り、例えば第2の平行配線群L2が第2の絶縁層I2中
に配設される場合等には必ずしも形成する必要はない。
I3 is laminated on the second insulating layer I2,
This is a third insulating layer to be a surface layer of the multilayer wiring board. The third insulating layer I3 is formed as needed. For example, when the second parallel wiring group L2 is provided in the second insulating layer I2, the third insulating layer I3 is not necessarily formed. .

【0023】このような多層配線基板には、例えばその
表面にMPU(Micro Processing Unit)・ASIC(A
pplication Specific Integrated Circuit)・DSP
(Digital Signal Processor)のような半導体集積回路
素子等の半導体素子が搭載される。そして、半導体素子
収納用パッケージや半導体素子搭載用基板、多数の半導
体集積回路素子が搭載されるいわゆるマルチチップモジ
ュールやマルチチップパッケージ、マザーボード等とし
て使用される。これらの半導体素子は、例えばいわゆる
バンプ電極によりこの多層配線基板の表面に実装され
て、あるいは接着剤・ろう材等により搭載部に取着され
るとともにボンディングワイヤ等を介して、貫通導体等
により例えば第2の平行配線群L2と電気的に接続され
る。なお、外部電気回路との接続部ならびに搭載される
半導体素子との接続部は図示していない。
In such a multilayer wiring board, for example, an MPU (Micro Processing Unit) / ASIC (A
pplication Specific Integrated Circuit) ・ DSP
A semiconductor device such as a semiconductor integrated circuit device such as a digital signal processor (Digital Signal Processor) is mounted. Then, it is used as a package for storing semiconductor elements, a substrate for mounting semiconductor elements, a so-called multi-chip module or multi-chip package on which a large number of semiconductor integrated circuit elements are mounted, a motherboard, or the like. These semiconductor elements are mounted on the surface of the multilayer wiring board by, for example, so-called bump electrodes, or are attached to a mounting portion by an adhesive, a brazing material, or the like, and are connected to the mounting portion via a bonding wire, for example, by a through conductor. It is electrically connected to the second parallel wiring group L2. A connection portion with an external electric circuit and a connection portion with a mounted semiconductor element are not shown.

【0024】貫通導体群Tは、第2の絶縁層I2を貫通
して上下の配線同士を電気的に接続するものであり、通
常はスルーホール導体やビア導体等が用いられ、接続に
必要な箇所に形成される。同様の貫通導体群は、各平行
配線群L1・L2の配線と電子部品または多層配線基板
の表面に取着された外部接続端子等とを電気的に接続す
る場合にも用いられる。
The through conductor group T penetrates through the second insulating layer I2 and electrically connects the upper and lower wirings. Usually, a through-hole conductor or a via conductor is used, and the through conductor group T is used for connection. Formed at the location. A similar through conductor group is also used to electrically connect the wiring of each of the parallel wiring groups L1 and L2 to an electronic component or an external connection terminal attached to the surface of the multilayer wiring board.

【0025】そして、本発明の多層配線基板において
は、図1〜図3に示すように、一方の平行配線群、ここ
では第1の平行配線群L1において接地配線G1を挟ん
で隣接する2つの信号配線S1を、他の平行配線群、こ
こでは第2の平行配線群L2の対応する信号配線S2に
それぞれ電気的に接続する信号用貫通導体T1間に、こ
れら信号用貫通導体T1間に挟まれた接地配線G1に一
端が接続され、他端が開放された補助貫通導体Tsを、
第1および第2の平行配線群L1・L2間、この例では
第2の絶縁層I2内にその信号用貫通導体T1に対して
略平行に配設している。これにより、隣接する信号用貫
通導体T1間の電磁気的な結合力は、その間に位置する
補助貫通導体Tsによって弱められるため、信号用貫通
導体T1間のクロストークを低減して信号用貫通導体T
1において発生するクロストークノイズを大幅に減少さ
せることができる。
In the multilayer wiring board of the present invention, as shown in FIG. 1 to FIG. 3, two parallel wiring groups, here, a first parallel wiring group L1, two adjacent wiring groups sandwiching the ground wiring G1 therebetween. The signal wiring S1 is sandwiched between the signal penetrating conductors T1 electrically connected to the corresponding signal wirings S2 of the other parallel wiring group, here, the second parallel wiring group L2, between these signal penetrating conductors T1. The auxiliary through conductor Ts, one end of which is connected to the ground wiring G1 and the other end of which is open,
Between the first and second parallel wiring groups L1 and L2, in this example, in the second insulating layer I2, they are arranged substantially parallel to the signal through conductor T1. Thereby, the electromagnetic coupling force between the adjacent signal through conductors T1 is weakened by the auxiliary through conductors Ts located therebetween, so that the crosstalk between the signal through conductors T1 is reduced and the signal through conductors T1 are reduced.
1 can significantly reduce crosstalk noise.

【0026】なお、補助貫通導体Tsは、第1の平行配
線群L1の2つの信号配線S1が電源配線P1を挟んで
隣接している場合であればその電源配線P1に一端が電
気的に接続されたものとすればよい。また、第2の平行
配線群L2の信号配線S2および接地配線G2・電源配
線P2に対しても同様の構成として配設すればよい。
One end of the auxiliary through conductor Ts is electrically connected to the power supply wiring P1 if the two signal wirings S1 of the first parallel wiring group L1 are adjacent to each other across the power supply wiring P1. What should have been done. Further, the signal wiring S2, the ground wiring G2, and the power supply wiring P2 of the second parallel wiring group L2 may be provided in a similar configuration.

【0027】本発明の多層配線基板においてこのように
補助貫通導体Tsを配設する場合、その電源配線P1・
P2または接地配線G1・G2に接続する位置は、効率
よくクロストークを低減させるためには、隣接する信号
用貫通導体S1間またはS2間において、これら信号用
貫通導体S1またはS2間を結ぶ直線上に位置するよう
に配設することが好ましい。そして、その位置は、各平
行配線群L1・L2および各貫通導体Tの各部の寸法や
形状・材料に基づく電気的な特性および高周波に対する
電磁気的な特性等を考慮して、また信号用貫通導体T1
について所望の特性インピーダンスが得られるように考
慮して適宜設定すればよい。
When the auxiliary through conductor Ts is provided in the multilayer wiring board of the present invention in this manner, the power supply wiring P1.
In order to reduce crosstalk efficiently, the position connected to P2 or the ground wirings G1 and G2 is on a straight line connecting between adjacent signal through conductors S1 or S2 or between these signal through conductors S1 or S2. It is preferable to dispose so that The position is determined in consideration of electrical characteristics based on dimensions, shapes and materials of the respective portions of the parallel wiring groups L1 and L2 and the respective through conductors T, electromagnetic characteristics with respect to high frequencies, and the like, and through signal conductors. T1
May be appropriately set in consideration of obtaining a desired characteristic impedance.

【0028】また、補助貫通導体Tsの長さは、信号用
貫通導体T1間のクロストークを最も効果的に低減する
観点からは、第1および第2の平行配線群L1・L2間
において対象となる信号用貫通導体T1の長さの約10分
の1からほぼ同じとすることが好ましい。この長さが約
10分の1を下回ると、信号用貫通導体T1間の電磁気的
な結合力がほとんど弱められず、クロストークが充分に
低減できなくなってクロストークノイズの大きさで5%
程度未満と不十分な程度しか低減できなくなる傾向があ
る。他方、信号用貫通導体T1の長さを上回ると、多層
配線基板を構成する際に第1および第2の平行配線群L
1・L2間に安定に精度よく配設するのが困難となる傾
向がある。
Further, the length of the auxiliary through conductor Ts is an object between the first and second parallel wiring groups L1 and L2 from the viewpoint of most effectively reducing the crosstalk between the signal through conductors T1. It is preferable that the length of the through-signal conductor T1 be about 1/10 to about the same. This length is about
If it is less than one-tenth, the electromagnetic coupling force between the signal through conductors T1 is hardly weakened, and the crosstalk cannot be sufficiently reduced, resulting in a crosstalk noise of 5%.
When the degree is less than the degree, the degree of reduction tends to be insufficient. On the other hand, if the length exceeds the length of the signal through conductor T1, the first and second parallel wiring groups L
There is a tendency that it is difficult to stably and accurately arrange between 1 and L2.

【0029】さらに、補助貫通導体Tsの大きさ(通常
は太さ)は、信号用貫通導体T1と同じ太さを中心とし
て、信号用貫通導体T1間の電磁気的な結合力の大きさ
に応じて適宜大きく(太く)あるいは小さく(細く)す
ればよい。具体的には、信号用貫通導体T1の大きさ
(太さ)の約4分の1から約3倍、好ましくは約2分の
1以上、約2倍以下の大きさ(太さ)とすればよい。こ
の大きさが約4分の1を下回ると、補助貫通導体を構成
する際に安定に精度よく配設するのが困難となる傾向が
ある。他方、約3倍を超える大きさとすると、隣接する
配線とショートするおそれが大きくなり、配線の高密度
化も困難になる傾向がある。
Further, the size (usually the thickness) of the auxiliary through conductor Ts depends on the magnitude of the electromagnetic coupling force between the signal through conductors T1 around the same thickness as the signal through conductor T1. The size may be increased (thick) or decreased (thin) as appropriate. Specifically, the size (thickness) of about 1/4 to about 3 times, preferably about 1/2 or more and about 2 times or less of the size (thickness) of the signal through conductor T1 is reduced. Just fine. If this size is less than about one-quarter, it tends to be difficult to stably and accurately arrange the auxiliary through conductor when configuring the auxiliary through conductor. On the other hand, when the size exceeds about three times, the possibility of short-circuiting with the adjacent wiring increases, and it tends to be difficult to increase the density of the wiring.

【0030】中でも、図4〜図6にそれぞれ図1〜図3
と同様の図で示した本発明の多層配線基板に係る積層配
線体の実施の形態の他の例におけるように、補助貫通導
体Tsの大きさを信号用貫通導体T1より大きくする
と、より効果的にクロストークノイズが低減できるとと
もに補助貫通導体と電気的に接続する電源配線または接
地配線との電気的な結合、つまりキャパシタンスが大き
くなるために、安定した電源供給が可能なものとなる。
4 to 6 show FIGS. 1 to 3 respectively.
When the size of the auxiliary through conductor Ts is larger than that of the signal through conductor T1, as in another example of the embodiment of the multilayer wiring body according to the multilayer wiring board of the present invention shown in the same drawing as in FIG. In addition, since the crosstalk noise can be reduced and the electrical connection with the power supply wiring or the ground wiring electrically connected to the auxiliary through conductor, that is, the capacitance increases, stable power supply can be performed.

【0031】本発明の多層配線基板においては、例え
ば、各絶縁層I1〜I3に比誘電率ε rが約10の同じ誘
電体材料を用いて、絶縁層の厚みを254μm、信号用貫
通導体の間隔は1.27mm、断面サイズを0.1mm×0.1m
mとして構成した場合、各配線の交差点に図2に示すよ
うに信号用貫通導体T1を配設して補助貫通導体Tsが
無い場合には、信号用貫通導体T1のクロストークノイ
ズは14.7mVとなる。これに対して、図2に示すように
補助貫通導体Tsを信号用貫通導体T1間に隣接するよ
うに配設することにより、信号用貫通導体T1のクロス
トークノイズを4.0mVに低減することができる。
In the multilayer wiring board of the present invention, for example,
For example, the relative dielectric constant ε rBut about 10 same invitations
Using a dielectric material, the thickness of the insulating layer is 254 μm,
The distance between conductors is 1.27mm, cross-sectional size is 0.1mm x 0.1m
When the configuration is made as m, as shown in FIG.
The auxiliary through conductor Ts is provided by arranging the signal through conductor T1 as shown in FIG.
If there is no crosstalk noise in the signal through conductor T1
Is 14.7 mV. On the other hand, as shown in FIG.
The auxiliary through conductor Ts is located between the signal through conductors T1.
The crossing of the signal through conductor T1
Talk noise can be reduced to 4.0 mV.

【0032】なお、以上の構成は、図1〜図3あるいは
図4〜図6に示す例に対して第1の平行配線群L1の下
方や第2の平行配線群L2の上方にも同様の平行配線群
を直交させて積層配置し、それらと貫通導体群で電気的
に接続する場合についても適用することができる。
The above configuration is similar to the example shown in FIGS. 1 to 3 or FIGS. 4 to 6 below the first parallel wiring group L1 and above the second parallel wiring group L2. The present invention can also be applied to a case where the parallel wiring groups are stacked so as to be orthogonal to each other and are electrically connected to the parallel wiring groups by the through conductor group.

【0033】また、本発明の多層配線基板に対しては、
第1および第2の平行配線群L1・L2の上下には、種
々の配線構造の多層配線部を積層して多層配線基板を構
成することができる。例えば、積層配線体と同様に平行
配線群を直交させて積層した構成の配線構造、あるいは
ストリップ線路構造の配線構造、その他、マイクロスト
リップ線路構造・コプレーナ線路構造等を多層配線基板
に要求される仕様等に応じて適宜選択して用いることが
できる。
Further, with respect to the multilayer wiring board of the present invention,
On and under the first and second parallel wiring groups L1 and L2, multilayer wiring portions having various wiring structures can be stacked to form a multilayer wiring board. For example, a wiring structure having a structure in which parallel wiring groups are orthogonally stacked like a multilayer wiring body, a wiring structure having a strip line structure, and other specifications required for a multi-layer wiring substrate such as a microstrip line structure and a coplanar line structure. It can be appropriately selected and used according to the conditions.

【0034】さらに、第1および第2の平行配線群L1
・L2の上下には、EMIノイズ等に対する電磁シール
ドとしての機能を有する接地導体層を配設してもよい。
Further, the first and second parallel wiring groups L1
A ground conductor layer having a function as an electromagnetic shield for EMI noise or the like may be provided above and below L2.

【0035】また例えば、ポリイミド絶縁層と銅蒸着に
よる導体層といったものを積層して電子回路を構成して
もよく、チップ抵抗・薄膜抵抗・コイルインダクタ・ク
ロスコンデンサ・チップコンデンサ・電解コンデンサと
いったものを取着して半導体素子収納用パッケージを構
成してもよい。
Further, for example, an electronic circuit may be formed by laminating a polyimide insulating layer and a conductor layer formed by vapor deposition of copper, such as a chip resistor, a thin film resistor, a coil inductor, a cross capacitor, a chip capacitor, and an electrolytic capacitor. It may be attached to form a semiconductor element storage package.

【0036】また、第1〜第3の絶縁層I1〜I3を始
めとする各絶縁層の形状は、要部平面図で図示したよう
な略正方形状のものに限られるものではなく、長方形状
や菱形状・多角形状等の形状であってもよい。
The shape of each of the insulating layers including the first to third insulating layers I1 to I3 is not limited to a substantially square shape as shown in a plan view of a main part, but is a rectangular shape. Or a shape such as a rhombus or a polygon.

【0037】なお、第1および第2の平行配線群L1・
L2は、第1および第2の絶縁層I1・I2の表面に形
成するものに限られず、それぞれの絶縁層I1・I2の
内部に形成したものであってもよい。
The first and second parallel wiring groups L1.
L2 is not limited to those formed on the surfaces of the first and second insulating layers I1 and I2, and may be formed inside the respective insulating layers I1 and I2.

【0038】また、図3あるいは図6に示す例に対し
て、第3の絶縁層I3を積層せず、第2の平行配線群L
2を第2の絶縁層I2の表面に形成して多層配線基板の
表面に露出させるようにしてもよい。
Further, in the example shown in FIG. 3 or FIG. 6, the third insulating layer I3 is not laminated, and the second parallel wiring group L
2 may be formed on the surface of the second insulating layer I2 to be exposed on the surface of the multilayer wiring board.

【0039】本発明の多層配線基板において、第1〜第
3の絶縁層I1〜I3の各絶縁層は、例えばセラミック
グリーンシート積層法によって、酸化アルミニウム質焼
結体や窒化アルミニウム質焼結体・炭化珪素質焼結体・
窒化珪素質焼結体・ムライト質焼結体・ガラスセラミッ
クス等の無機絶縁材料を使用して、あるいはポリイミド
・エポキシ樹脂・フッ素樹脂・ポリノルボルネン・ベン
ゾシクロブテン等の有機絶縁材料を使用して、あるいは
セラミックス粉末等の無機絶縁物粉末をエポキシ系樹脂
等の熱硬化性樹脂で結合して成る複合絶縁材料などの電
気絶縁材料を使用して形成される。
In the multilayer wiring board of the present invention, each of the first to third insulating layers I1 to I3 is made of an aluminum oxide sintered body or an aluminum nitride sintered body by, for example, a ceramic green sheet laminating method. Silicon carbide sintered body
Using inorganic insulating materials such as silicon nitride sintered body, mullite sintered body, glass ceramics, or organic insulating materials such as polyimide, epoxy resin, fluororesin, polynorbornene, benzocyclobutene, Alternatively, it is formed using an electrical insulating material such as a composite insulating material formed by bonding an inorganic insulating powder such as a ceramic powder with a thermosetting resin such as an epoxy resin.

【0040】これら絶縁層は、例えば酸化アルミニウム
質焼結体から成る場合であれば、酸化アルミニウム・酸
化珪素・酸化カルシウム・酸化マグネシウム等の原料粉
末に適当な有機バインダ・溶剤等を添加混合して泥漿状
となすとともに、これを従来周知のドクターブレード法
を採用してシート状となすことによってセラミックグリ
ーンシートを得て、しかる後、これらのセラミックグリ
ーンシートに適当な打ち抜き加工を施すとともに各平行
配線群および各貫通導体群ならびに導体層となる金属ペ
ーストを所定のパターンに印刷塗布して上下に積層し、
最後にこの積層体を還元雰囲気中、約1600℃の温度で焼
成することによって製作される。
If these insulating layers are made of, for example, an aluminum oxide sintered body, a suitable organic binder, a solvent, etc. are added to a raw material powder of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide, etc. and mixed. A ceramic green sheet was obtained by forming the sheet into a sheet shape by employing a well-known doctor blade method, and thereafter, the ceramic green sheet was subjected to an appropriate punching process and each parallel wiring was formed. The group and each through conductor group and the metal paste to be the conductor layer are printed and applied in a predetermined pattern and laminated vertically,
Finally, the laminate is manufactured by firing at a temperature of about 1600 ° C. in a reducing atmosphere.

【0041】これら絶縁層の厚みとしては、使用する材
料の特性に応じて、要求される仕様に対応する機械的強
度や電気的特性・貫通導体群の形成の容易さ等の条件を
満たすように適宜設定される。
The thickness of these insulating layers is determined so as to satisfy the conditions such as mechanical strength and electric characteristics corresponding to the required specifications and ease of forming the through conductor group according to the characteristics of the material to be used. It is set appropriately.

【0042】また、第1および第2の平行配線群L1・
L2やその他の配線層および接地導体層GLならびに貫
通導体群等は、例えばタングステンやモリブデン・モリ
ブデン−マンガン・銅・銀・銀−パラジウム等の金属粉
末メタライズ、あるいは銅・銀・ニッケル・クロム・チ
タン・金・ニオブやそれらの合金等の金属材料の薄膜な
どから成る。
The first and second parallel wiring groups L1.
L2 and other wiring layers, ground conductor layers GL, through conductor groups, and the like are made of metal powder metallized, for example, tungsten, molybdenum, molybdenum-manganese, copper, silver, silver-palladium, or copper, silver, nickel, chrome, titanium. -It is composed of a thin film of a metal material such as gold, niobium, or an alloy thereof.

【0043】例えば、タングステンの金属粉末メタライ
ズから成る場合であれば、タングステン粉末に適当な有
機バインダ・溶剤等を添加混合して得た金属ペーストを
絶縁層となるセラミックグリーンシートに所定のパター
ンに印刷塗布し、これをセラミックグリーンシートの積
層体とともに焼成することによって、各絶縁層の上面に
配設される。
For example, in the case of metallization of metal powder of tungsten, a metal paste obtained by adding and mixing an appropriate organic binder and solvent to the tungsten powder is printed in a predetermined pattern on a ceramic green sheet serving as an insulating layer. By applying and firing this together with the ceramic green sheet laminate, it is disposed on the upper surface of each insulating layer.

【0044】また、金属材料の薄膜から成る場合であれ
ば、例えばスパッタリング法・真空蒸着法またはメッキ
法により金属層を形成した後、フォトリソグラフィ法に
より所定の配線パターンに形成される。
In the case of a thin film of a metal material, a metal layer is formed by, for example, a sputtering method, a vacuum evaporation method, or a plating method, and then a predetermined wiring pattern is formed by a photolithography method.

【0045】第1および第2の平行配線群L1・L2の
各配線の幅および配線間の間隔、あるいは貫通導体群T
の形状や寸法・配設位置等は、使用する材料の特性に応
じて、要求される仕様に対応する電気的特性や絶縁層I
1・I2への配設の容易さ等の条件を満たすように適宜
設定される。
The widths and the intervals between the wirings of the first and second parallel wiring groups L1 and L2, or the through conductor group T
The shape, dimensions, arrangement position, etc. of the insulation layer I and the electrical characteristics corresponding to the required specifications depend on the characteristics of the material used.
It is set appropriately so as to satisfy conditions such as ease of disposition in 1.I2.

【0046】なお、各平行配線群L1・L2の厚みは1
〜20μm程度とすることが好ましい。この厚みが1μm
未満となると配線の抵抗が大きくなるため、配線群によ
る半導体素子への良好な電源供給や安定したグランドの
確保・良好な信号の伝搬が困難となる傾向が見られる。
他方、20μmを超えるとその上に積層される絶縁層によ
る被覆が不十分となって絶縁不良となる場合がある。
The thickness of each of the parallel wiring groups L1 and L2 is 1
It is preferably about 20 μm. This thickness is 1 μm
When the value is less than the above, the resistance of the wiring increases, and it tends to be difficult to provide a good power supply to the semiconductor element by the wiring group, secure a stable ground, and propagate a good signal.
On the other hand, if it exceeds 20 μm, the insulation layer laminated thereon may be insufficiently covered, resulting in poor insulation.

【0047】貫通導体群Tの各貫通導体T1・T2なら
びに補助貫通導体Tsは、横断面形状が円形のものの他
にも楕円形や正方形・長方形等の矩形、その他の異形状
のものを用いてもよい。その位置や大きさは、使用する
材料の特性に応じて、要求される仕様に対応する電気的
特性や絶縁層への形成・配設の容易さ等の条件を満たす
ように適宜設定される。
Each of the through conductors T1 and T2 of the through conductor group T and the auxiliary through conductor Ts may have a cross-sectional shape other than a circle, such as an ellipse, a rectangle such as a square or a rectangle, or any other shape. Is also good. The position and size are appropriately set according to the characteristics of the material to be used so as to satisfy conditions such as electrical characteristics corresponding to required specifications and easiness of formation and arrangement on the insulating layer.

【0048】例えば、絶縁層に酸化アルミニウム質焼結
体を用い、平行配線群にタングステンの金属メタライズ
を用いた場合であれば、絶縁層の厚みを200μmとし、
配線の線幅を100μm、配線間の間隔を150μm、貫通導
体の大きさを100μmとすることによって、信号配線の
インピーダンスを50Ωとし、上下の平行配線群間を高周
波信号の反射を抑えつつ電気的に接続することができ
る。
For example, when the aluminum oxide sintered body is used for the insulating layer and the metallization of tungsten is used for the parallel wiring group, the thickness of the insulating layer is set to 200 μm.
By setting the line width of the wiring to 100 μm, the spacing between the wirings to 150 μm, and the size of the through conductor to 100 μm, the impedance of the signal wiring is set to 50Ω, and the electrical connection between the upper and lower parallel wiring groups is suppressed while suppressing the reflection of high-frequency signals. Can be connected to

【0049】なお、本発明は以上の実施の形態の例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
で種々の変更を加えることは何ら差し支えない。例え
ば、上述の実施例では本発明を半導体素子を搭載する多
層配線基板として説明したが、これを半導体素子を収容
する半導体素子収納用パッケージや、あるいはマルチチ
ップモジュールに適用するものとしてもよい。また、放
熱を考慮した窒化アルミニウム質焼結体・炭化珪素質焼
結体や、低誘電率を考慮したガラスセラミックス質焼結
体を用いたものとしてもよい。
It should be noted that the present invention is not limited to the above-described embodiments, and that various changes may be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the present invention has been described as a multilayer wiring board on which a semiconductor element is mounted. However, the present invention may be applied to a semiconductor element housing package for housing a semiconductor element or a multi-chip module. Further, an aluminum nitride-based sintered body / silicon carbide-based sintered body considering heat dissipation or a glass ceramics-based sintered body considering low dielectric constant may be used.

【0050】[0050]

【発明の効果】本発明の多層回路基板によれば、第1お
よび第2の平行配線群の信号配線同士であって、一方の
平行配線群において電源配線または接地配線を挟んで隣
接する2つの信号配線同士を他方の平行配線群の対応す
る信号配線にそれぞれ電気的に接続する信号用貫通導体
間に、これら信号用貫通導体間に挟まれたその電源配線
または接地配線に一端が電気的に接続され、他端が開放
された補助貫通導体を前記第1および第2の平行配線群
間に配設したことから、これら信号用貫通導体間に配置
されたこれら信号用貫通導体に電気的に導通のない補助
貫通導体によって信号用貫通導体間の電磁気的な結合力
が弱められるため、信号用貫通導体間におけるクロスト
ークを低減してクロストークノイズの発生を抑制するこ
とができる。
According to the multilayer circuit board of the present invention, two signal wirings of the first and second parallel wiring groups adjacent to each other with the power supply wiring or the ground wiring interposed therebetween in one of the parallel wiring groups. One end is electrically connected to the power supply wiring or the ground wiring which is interposed between the signal through conductors for electrically connecting the signal wirings to the corresponding signal wirings of the other parallel wiring group. Since the auxiliary penetrating conductor which is connected and whose other end is open is disposed between the first and second parallel wiring groups, the signal penetrating conductor disposed between these signal penetrating conductors is electrically connected. Since the electromagnetic coupling force between the signal through conductors is weakened by the non-conductive auxiliary through conductors, crosstalk between the signal through conductors can be reduced and the generation of crosstalk noise can be suppressed.

【0051】また、補助貫通導体の大きさを信号用貫通
導体より大きくしたときには、補助貫通導体と電気的に
接続する電源配線または接地配線との電気的な結合、つ
まりキャパシタンスが大きくなるために安定した電源供
給が可能なものとなる。
Further, when the size of the auxiliary through conductor is made larger than that of the signal through conductor, electric coupling between the auxiliary through conductor and the power supply wiring or the ground wiring electrically connected to the auxiliary through conductor becomes large, that is, the capacitance becomes large. Power can be supplied.

【0052】これにより、本発明の多層配線基板によれ
ば、交互に積層された平行配線群について上下の平行配
線群間で信号配線同士を信号用貫通導体により電気的に
接続する場合に、その近傍に所定の位置関係で一方の平
行配線群の電源配線または接地配線に接続された他端開
放の補助貫通導体を配設したことで、それら信号用貫通
導体間におけるクロストークを低減してクロストークノ
イズの発生を抑制することができる、高速で作動する半
導体集積回路素子等の半導体素子を搭載する電子回路基
板やパッケージ等に好適な多層配線基板となる。
Thus, according to the multilayer wiring board of the present invention, when the signal wirings are electrically connected by the signal through conductor between the upper and lower parallel wiring groups in the alternately stacked parallel wiring groups, By arranging an auxiliary through conductor open at the other end connected to the power supply wiring or the ground wiring of one of the parallel wiring groups in a predetermined positional relationship in the vicinity, crosstalk between these signal through conductors is reduced to reduce the crosstalk. A multilayer wiring board suitable for an electronic circuit board, a package, or the like on which a semiconductor element such as a semiconductor integrated circuit element operating at a high speed, which can suppress occurrence of talk noise, is provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板に係る積層配線体の実施
の形態の一例を示すものであり、(a)は第1の絶縁層
の、(b)は第2の絶縁層の要部平面図を示す。
FIGS. 1A and 1B show an example of an embodiment of a multilayer wiring body according to a multilayer wiring board of the present invention, wherein FIG. 1A shows a first insulating layer, and FIG. 1B shows a main part of a second insulating layer. FIG.

【図2】本発明の多層配線基板の実施の形態の一例を示
す要部平面図である。
FIG. 2 is a main part plan view showing an example of an embodiment of a multilayer wiring board of the present invention.

【図3】図2に示す多層配線基板のA−A’線断面図で
ある。
FIG. 3 is a sectional view taken along line AA ′ of the multilayer wiring board shown in FIG. 2;

【図4】本発明の多層配線基板に係る積層配線体の実施
の形態の他の例を示すものであり、(a)は第1の絶縁
層の、(b)は第2の絶縁層の要部平面図を示す。
4A and 4B show another example of the embodiment of the multilayer wiring body according to the multilayer wiring board of the present invention, wherein FIG. 4A shows the first insulating layer, and FIG. 4B shows the second insulating layer. FIG.

【図5】本発明の多層配線基板の実施の形態の他の例を
示す要部平面図である。
FIG. 5 is a main part plan view showing another example of the embodiment of the multilayer wiring board of the present invention.

【図6】図5に示す多層配線基板のA−A’線断面図で
ある。
FIG. 6 is a sectional view taken along line AA ′ of the multilayer wiring board shown in FIG. 5;

【符号の説明】[Explanation of symbols]

I1〜I3・・・・絶縁層 L1、L2・・・・平行配線群 P1、P2・・・・電源配線 G1、G2・・・・接地配線 S1、S2・・・・信号配線 T・・・・・・・・貫通導体群 T1・・・・・・・信号用貫通導体 T2・・・・・・・電源/接地用貫通導体 Ts・・・・・・・補助貫通導体 ... I1 to I3... Insulating layer L1, L2... Parallel wiring group P1, P2... Power supply wiring G1, G2. ······ Thru-conductor group T1 ············································· Power supply / grounding through-conductor Ts ·····························

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1の平行配線群を有する第1の絶縁層
上に、前記第1の平行配線群と直交する第2の平行配線
群を有する第2の絶縁層を積層し、前記第1および第2
の平行配線群を貫通導体群で電気的に接続して成る積層
配線体を具備して成り、前記第1および第2の平行配線
群はそれぞれ複数の信号配線と、各信号配線に隣接する
電源配線または接地配線とを有するとともに、一方の平
行配線群において前記電源配線または接地配線を挟んで
隣接する2つの前記信号配線を他方の平行配線群の対応
する前記信号配線にそれぞれ電気的に接続する信号用貫
通導体間に、これら信号用貫通導体間に挟まれた前記電
源配線または接地配線に一端が電気的に接続され、他端
が開放された補助貫通導体を前記第1および第2の平行
配線群間に配設したことを特徴とする多層配線基板。
1. A second insulating layer having a second parallel wiring group orthogonal to the first parallel wiring group is laminated on a first insulating layer having a first parallel wiring group. 1st and 2nd
And a plurality of signal wirings, and a power supply adjacent to each signal wiring. The first and second parallel wiring groups each include a plurality of signal wirings. A wiring or a ground wiring, and electrically connects two signal wirings adjacent to each other across the power supply wiring or the ground wiring in one of the parallel wiring groups to the corresponding signal wiring in the other parallel wiring group. Between the signal through conductors, an auxiliary through conductor having one end electrically connected to the power supply wiring or the ground wiring sandwiched between the signal through conductors and having the other end opened is connected to the first and second parallel through conductors. A multilayer wiring board, which is provided between wiring groups.
【請求項2】 前記補助貫通導体の大きさを、前記信号
用貫通導体より大きくしたことを特徴とする請求項1記
載の多層配線基板。
2. The multilayer wiring board according to claim 1, wherein the size of the auxiliary through conductor is larger than that of the signal through conductor.
JP2000240984A 2000-08-09 2000-08-09 Multilayered printed circuit board Pending JP2002057461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000240984A JP2002057461A (en) 2000-08-09 2000-08-09 Multilayered printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000240984A JP2002057461A (en) 2000-08-09 2000-08-09 Multilayered printed circuit board

Publications (1)

Publication Number Publication Date
JP2002057461A true JP2002057461A (en) 2002-02-22

Family

ID=18732254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000240984A Pending JP2002057461A (en) 2000-08-09 2000-08-09 Multilayered printed circuit board

Country Status (1)

Country Link
JP (1) JP2002057461A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019149502A (en) * 2018-02-28 2019-09-05 京セラ株式会社 Printed-circuit board

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343601A (en) * 1992-02-03 1993-12-24 Ncr Internatl Inc Connection system for integrated circuit
JPH0637416A (en) * 1992-07-14 1994-02-10 Fujitsu Ltd Printed wiring board
JPH07221512A (en) * 1994-02-04 1995-08-18 Sony Corp High frequency connection line
JPH0918156A (en) * 1995-06-27 1997-01-17 Mitsubishi Electric Corp Multilayer printed wiring board
JPH11112142A (en) * 1997-10-01 1999-04-23 Kyocera Corp Multilayered wiring board
JPH11150371A (en) * 1997-11-19 1999-06-02 Matsushita Electric Ind Co Ltd Multilayer circuit board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343601A (en) * 1992-02-03 1993-12-24 Ncr Internatl Inc Connection system for integrated circuit
JPH0637416A (en) * 1992-07-14 1994-02-10 Fujitsu Ltd Printed wiring board
JPH07221512A (en) * 1994-02-04 1995-08-18 Sony Corp High frequency connection line
JPH0918156A (en) * 1995-06-27 1997-01-17 Mitsubishi Electric Corp Multilayer printed wiring board
JPH11112142A (en) * 1997-10-01 1999-04-23 Kyocera Corp Multilayered wiring board
JPH11150371A (en) * 1997-11-19 1999-06-02 Matsushita Electric Ind Co Ltd Multilayer circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019149502A (en) * 2018-02-28 2019-09-05 京セラ株式会社 Printed-circuit board

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