JP7099341B2 - Semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device.

In an IC that operates at high speed, the wavelength of the signal propagating in the circuit may be about the same as the size of one side of the capacitor provided in the IC. In this case, a resonance phenomenon occurs at the signal wavelength corresponding to one side of the capacitor, and the circuit operation may become unstable. In the semiconductor device described in Patent Document 1, the resonance frequency is continuously changed by forming the shape in which the opposite sides of the MIM (Metal-Insulator-Metal) capacitor do not have parallel portions, and a specific frequency is specified. It suppresses the occurrence of resonance phenomenon.

Japanese Unexamined Patent Publication No. 2004-172245

Here, in a monolithic microwave integrated circuit (MMIC) that adopts WLCSP (Wafer levelChip Size Package), which is a package format suitable for miniaturization, the width of the pad continuous with the electrode portion constituting the MIM capacitor. For example, the width of the wiring continuous to the electrode portion is as small as about 10 μm, while it is as large as about 100 μm. When a pad and wiring having greatly different widths (that is, greatly different impedances) are connected in this way, signal reflection occurs due to the difference in width, and the configuration of Patent Document 1 described above also causes Circuit operation may become unstable. For example, the reflection of the above-mentioned signal is reduced by forming the electrode portion of the MIM capacitor in a tapered shape so that the width gradually decreases from the side continuous with the pad to the side continuous with the wiring. be able to. However, in the configuration in which the electrode portion of the MIM capacitor is formed in a tapered shape, the facing area is reduced as compared with the case where the electrode portion of the MIM capacitor is rectangular, and the capacitance value of the MIM capacitor is reduced, resulting in a decrease. As a result, the loss and bandwidth will deteriorate.

Therefore, one aspect of the present invention is to provide an MMIC that realizes miniaturization, low loss, and a wide band.

The semiconductor device according to one aspect of the present invention is a semiconductor device provided with a first wiring layer, a second wiring layer, and a third wiring layer in order from the substrate side, and the first wiring layer has a first electrode portion. The second wiring layer has a second electrode portion and a land portion that are electrically independent of each other, the second electrode portion is continuous with the wiring structure of the semiconductor device, and the third wiring layer has. It has a third electrode portion and a pad portion continuous with the third electrode portion, and is formed by a second electrode portion and a first electrode portion, and a first interlayer film interposed between the second wiring layer and the first wiring layer. A 1 MIM capacitor is formed, and a second MIM capacitor overlapping with the first MIM capacitor is formed by the second electrode portion and the third electrode portion and the second interlayer film interposed between the second wiring layer and the third wiring layer, and the first MIM is formed. When viewed in plan view, the capacitor and the second MIM capacitor are formed in a trapezoidal shape with the side on the pad portion side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion, and the third electrode portion is the first electrode on the lower bottom portion. It has a first via connected to the portion.

The semiconductor device according to another aspect of the present invention is a semiconductor device provided with a first wiring layer, a second wiring layer, and a third wiring layer in order from the substrate side, and the first wiring layer is a first electrode portion. And has a wiring portion independent of the first electrode portion and continuous with the wiring structure of the semiconductor device, and the second wiring layer has a second electrode portion and a land portion electrically independent of each other, and is a third wiring layer. Has a third electrode portion and a pad portion continuous with the third electrode portion, and is formed by a second electrode portion and a first electrode portion, and a first interlayer film interposed between the second wiring layer and the first wiring layer. , A first MIM capacitor is formed, and a second MIM capacitor overlapping with the first MIM capacitor is formed by the second electrode portion and the third electrode portion and the second interlayer film interposed between the second wiring layer and the third wiring layer. When viewed in plan view, the first MIM capacitor and the second MIM capacitor are formed in a trapezoidal shape with the side on the pad portion side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion, and the third electrode portion is formed in the lower bottom portion. It has a first via connected to one electrode portion.

According to the above, it is possible to provide an MMIC that realizes miniaturization, low loss, and a wide band.

It is a figure which shows the MMIC which concerns on one aspect of this invention, (a) is a plan view, (b) is a sectional view along the bb line of (a), (c) is cc of (a). A cross-sectional view taken along the line, (d) is a cross-sectional view taken along the dd line of (a). It is a figure which shows typically the electrode structure of each wiring layer in MMIC shown in FIG. It is a figure which shows the MMIC which concerns on the comparative example schematically, (a) is a plan view, (b) is a sectional view along line bb (a). It is a figure explaining the problem of MMIC which concerns on the comparative example, (a) is a figure explaining the decrease of the facing area, (b) is a figure explaining that an end function as an open stub. It is a graph which shows the band improvement and loss improvement effect of MMIC which concerns on one aspect of this invention. It is a figure which shows the MMIC which concerns on the modification of this invention, (a) is a plan view, (b) is a sectional view along the bb line of (a), (c) is cc of (a). A cross-sectional view taken along the line, (d) is a cross-sectional view taken along the dd line of (a).

A specific example of a monolithic microwave integrated circuit (MMIC) according to an embodiment of the present invention will be described below with reference to the drawings. In the description, the same code will be used for the same element or the element having the same function, and duplicate description will be omitted. The present invention is not limited to the following examples, but is shown by the scope of claims, and is intended to include all modifications within the scope and intent equivalent to the scope of claims.

1A and 1B are views showing MMIC1 (semiconductor device) according to the present embodiment, FIG. 1A is a plan view, FIG. 1B is a sectional view taken along line bb of FIG. A is a cross-sectional view taken along the line cc, and (d) is a cross-sectional view taken along the line dd of (a). MMIC1 is a kind of microwave integrated circuit, which is an integrated circuit in which a microwave circuit (functions such as microwave band mixer, amplification, switching, etc.) is formed on a single semiconductor substrate by microfabrication technology. Further, the MMIC 1 is formed of, for example, a WLCSP (Wafer level Chip Size Package), which is a package format suitable for miniaturization. WLCSP is a package type in which terminals are formed, wiring, and the like are performed before cutting out a wafer on which a semiconductor element is formed.

In the MMIC 1 shown in FIGS. 1 (a) to 1 (d), the first wiring layer 11, the insulator layer 21 (first interlayer film, see FIG. 1 (c)), and the second in order from the substrate (not shown) side. It has a structure (three-layer structure) in which a wiring layer 12, an insulator layer 22 (second interlayer film, see FIG. 1C), and a third wiring layer 13 are laminated. When the substrate is an insulating substrate, the first wiring layer 11 may be formed directly on the substrate.

The first wiring layer 11 is, for example, a metal layer having a thickness of 1 μm made of gold. The second wiring layer 12 is, for example, a metal layer having a thickness of 1 μm made of gold. The third wiring layer 13 is, for example, a metal layer having a thickness of 1 μm made of gold. For the formation of each wiring layer, a well-known thin-film deposition method and a subsequent lift-off method, or a method such as an ion milling method after forming a gold layer by a sputtering method can be used. As the insulator layers 21 and 22, for example, polyimide or the like can be used. Each of the insulator layers 21 and 22 is formed with a film thickness thicker than that of the metal layer, for example, a thickness of 2 μm. A method such as a plasma CVD method or a spin coating method can be used to form the insulator layers 21 and 22.

FIG. 2 is a diagram schematically showing an electrode structure of each wiring layer in MMIC1 shown in FIG. In FIG. 2, the configuration related to the first wiring layer 11 is shown by a two-dot chain line, the configuration related to the second wiring layer 12 is shown by a broken line, and the configuration related to the third wiring layer 13 is shown by a solid line. As shown in FIG. 2, the third wiring layer 13 has a third electrode portion 13a and a pad portion 13b continuous with the third electrode portion 13a. The pad portion 13b has a substantially rectangular shape in a plan view, and the length in the width direction (the direction in which the pad portion 13b and the third electrode portion 13a intersect the continuous direction) is, for example, about 100 μm to 200 μm. A solder ball 13x is provided on the pad portion 13b, and the pad portion 13b and an external configuration (printed wiring board or the like) are connected by the solder ball 13x. The third electrode portion 13a is continuous with the pad portion 13b and is a planar viewing table-shaped electrode portion. More specifically, the third electrode portion 13a is formed in a trapezoidal shape in which the side continuous with the pad portion 13b is the lower bottom portion 13v and the side separated from the pad portion 13b is the upper bottom portion 13w when viewed in a plan view. The lower bottom 13v is longer than the upper bottom 13w. As a result, the third electrode portion 13a is formed in a tapered shape from the lower bottom portion 13v toward the upper bottom portion 13w when viewed in a plan view.

The first wiring layer 11 has a first electrode portion 11a and a wiring portion 11b. The first electrode portion 11a is an electrode portion formed in a plan view table shape, and when viewed in a plan view, the first electrode portion 11a has the same shape as the third electrode portion 13a of the third wiring layer 13, and the third electrode portion 13a and the formed region are formed. It almost overlaps. That is, the first electrode portion 11a is formed in a trapezoidal shape in which the side on the pad portion 13b side is the lower bottom portion 11v and the side separated from the pad portion 13b is the upper bottom portion 11w when viewed in a plan view. In the first electrode portion 11a, the lower bottom portion 11v is longer than the upper bottom portion 11w, and is formed in a tapered shape from the lower bottom portion 11v toward the upper bottom portion 11w when viewed in a plan view. The wiring portion 11b is provided independently (separated from) from the first electrode portion 11a, and is continuous with the wiring structure (for example, a wiring structure of 50Ω) in the MMIC 1. The length of the wiring portion 11b in the width direction (direction intersecting the longitudinal direction of the wiring portion 11b) is about the same as that of the wiring structure, and is, for example, about 10 μm.

The second wiring layer 12 has a second electrode portion 12a and a plurality of land portions 12b, 12b, 12c, 12c. The plurality of land portions 12b, 12b, 12c, and 12c are provided independently of each other, and are also provided independently of the second electrode portion 12a. The land portions 12b and 12b (first land portions) are provided at both ends in the width direction on the lower bottom portion 11v side of the third electrode portion 13a when viewed in a plan view. The land portions 12c and 12c (second land portions) are provided at both ends in the width direction on the upper bottom portion 11w side of the third electrode portion 13a when viewed in a plan view. The second electrode portion 12a is a second portion that is continuous with the first portion 12d formed in a substantially trapezoidal shape in a plan view and is electrically connected to the wiring portion 11b of the first wiring layer 11. It has 12f. The first portion 12d is formed in a substantially trapezoidal shape so that the formed region substantially overlaps with the third electrode portion 13a when viewed in a plan view, but the plurality of land portions 12b, 12b, 12c, 12c described above are formed. It is not formed in the area. That is, the first portion 12d is not formed at both ends in the width direction on the lower bottom side where the land portions 12b and 12b are formed and at both ends in the width direction on the upper bottom portion side where the land portions 12c and 12c are formed. .. More specifically, the first portion 12d is formed slightly inside the third electrode portion 13a and the first electrode portion 11a when viewed in a plan view. The second portion 12f is continuously provided on the upper bottom portion side of the first portion 12d. The second portion 12f is provided so as to overlap the wiring portion 11b of the first wiring layer 11 in the stacking direction. The second portion 12f is connected to the wiring portion 11b of the first wiring layer 11 via the via 12x (see FIG. 1C).

As shown in FIGS. 1B and 1C, the third electrode portion 13a of the third wiring layer 13 is further connected to the first electrode portion 11a of the first wiring layer 11 at the lower bottom portion 13v. It has first vias 131 and 131, and second vias 132 and 132 connected to the first electrode portion 11a of the first wiring layer 11 at the upper bottom portion 13w. The first vias 131, 131 and the second vias 132, 132 are holes (via holes) for the purpose of conduction between the third electrode portion 13a and the first electrode portion 11a, and penetrate the insulator layers 21 and 22. Is formed in. The first vias 131 and 131 extend from both ends in the width direction of the lower bottom portion 13v toward the first electrode portion 11a and are connected to the lower bottom portion 11v of the first electrode portion 11a via the land portions 12b and 12b, respectively. ing. The second vias 132 and 132 extend from both ends in the width direction of the upper bottom portion 13w toward the first electrode portion 11a, and are connected to the upper bottom portion 11w of the first electrode portion 11a via the land portions 12c and 12c, respectively. ing.

In the MMIC 1 having such a configuration, as shown in FIG. 1 (c), an insulator interposed between the second electrode portion 12a and the first electrode portion 11a and the second wiring layer 12 and the first wiring layer 11. The first MIM capacitor 101 is formed by the layer 21, and the first MIM is formed by the second electrode portion 12a and the third electrode portion 13a, and the insulator layer 22 interposed between the second wiring layer 12 and the third wiring layer 13. A second MIM capacitor 102 that overlaps the capacitor 101 in the stacking direction is formed. Since the first electrode portion 11a, the second electrode portion 12a, and the third electrode portion 13a all have a planar viewing table shape (or substantially trapezoidal shape), the first MIM capacitor 101 and the second MIM capacitor 102 are viewed in a plan view. Both are formed in a trapezoidal shape with the side on the pad portion 13b side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion.

Next, the action and effect of MMIC1 according to this embodiment will be described in comparison with a comparative example.

3A and 3B are views schematically showing MMIC501 according to a comparative example, where FIG. 3A is a plan view and FIG. 3B is a sectional view taken along line bb of FIG. 3A. As shown in FIG. 3B, the MMIC 501 has a structure (two-layer structure) in which a first wiring layer 511, an insulator layer 521, and a second wiring layer 513 are laminated in this order from the substrate (not shown) side. have. The second wiring layer 513 has a planar viewing table-shaped electrode portion 513a and a pad portion 513b continuous with the electrode portion 513a. Further, the first wiring layer 511 has an electrode portion 511a having a plan view table shape and a wiring portion 511b continuous with the wiring structure. Then, in the MMIC 501, as shown in FIG. 3B, the electrode portion 511a, the electrode portion 513a, and the insulator layer 521 form a planar viewing platform-shaped MIM capacitor 601.

The MMIC 501 is formed by, for example, WLCSP. In the MMIC 501 formed by WLCSP, the width of the pad portion 513b is as large as about 100 μm, while the width of the wiring portion 511b and the wiring structure is as small as about 10 μm. When the pad portion 513b whose widths are significantly different from each other (that is, the impedances are significantly different) and the wiring structure are connected in this way, signal reflection due to the difference in width occurs and the circuit operation becomes unstable. There is a risk. In the MMIC 501, the electrode portions 511a and 513a of the MIM capacitor 601 are formed in a tapered shape from the lower bottom portion to the upper bottom portion, and the width thereof is gradually increased from the side continuous with the pad portion 513b to the side continuous with the wiring portion 511b. The reflection of the above-mentioned signal is reduced by forming the capacitor so as to be small. However, in such a configuration in which the electrode portion of the MIM capacitor is formed in a tapered shape, the facing area is reduced as compared with the case where the electrode portion of the MIM capacitor is rectangular. That is, as shown in FIG. 4A, the planar viewing table-shaped MIM capacitor 601 has a facing area only in the region RE (region partitioned by the alternate long and short dash line) as compared with the planar viewing rectangular MIM capacitor. It will decrease. As a result, the capacitance value of the MIM capacitor 601 is reduced, and as a result, the loss and the bandwidth are deteriorated.

On the other hand, the MMIC 1 according to the present embodiment is a semiconductor device including the first wiring layer 11, the second wiring layer 12, and the third wiring layer 13 in order from the substrate side, and the first wiring layer 11 is The first electrode portion 11a and the wiring portion 11b independent of the first electrode portion 11a and continuous with the wiring structure are provided, and the second wiring layer 12 is electrically independent of the second electrode portion 12a and the land portion 12b. It has 12b, 12c, 12c, and the third wiring layer 13 has a third electrode portion 13a and a pad portion 13b continuous with the third electrode portion 13a, and has a second electrode portion 12a and a first electrode portion 11a. The first MIM capacitor 101 is formed by the insulator layer 21 interposed between the second wiring layer 12 and the first wiring layer 11, the second electrode portion 12a and the third electrode portion 13a, the second wiring layer 12 and the like. A second MIM capacitor 102 that overlaps with the first MIM capacitor 101 is formed by the insulator layer 22 interposed between the third wiring layers 13, and the first MIM capacitor 101 and the second MIM capacitor 102 are on the pad portion 13b side when viewed in a plan view. It is formed in a trapezoidal shape with the side as the lower bottom and the side on the wiring structure side as the upper bottom, and the third electrode portion 13a has the first vias 131 and 131 connected to the first electrode portion 11a in the lower bottom portion 13v. Have.

In the MMIC 501 according to the comparative example, the wiring layer has a two-layer structure, whereas in the MMIC 1 according to the present embodiment, the wiring layer has a three-layer structure, and the first electrode portion 11a of the first wiring layer 11 has a structure. The first MIM capacitor 101 is formed by including the second electrode portion 12a of the second wiring layer 12, and includes the third electrode portion 13a of the third wiring layer 13 and the second electrode portion 12a of the second wiring layer 12. The 2MIM capacitor 102 is formed, and the third electrode portion 13a and the first electrode portion 11a are connected by the first vias 131 and 131 on the lower bottom portions 13v and 11v sides. Since the wiring layer has a three-layer structure and two MIM capacitors are formed, the capacitance value can be increased as compared with the MMIC 501 having one MIM capacitor. That is, in the MMIC1 that adopts WLCSP, which is a package type suitable for miniaturization, MIM capacitors (first MIM capacitor 101 and second MIM capacitor) are used to reduce signal reflection caused by the difference in width between the pad portion 13b and the wiring structure. Even in a configuration in which 102) is formed in a tapered shape (in a plan view trapezoidal shape), the capacitance value can be secured by forming two MIM capacitors. By guaranteeing the capacity value, it is possible to suppress the loss and the deterioration of the band in MMIC1. From the above, according to the configuration according to the present embodiment, it is possible to provide the MMIC 1 that realizes miniaturization, low loss, and a wide band.

Further, in the MMIC 1 according to the present embodiment, the third electrode portion 13a has the second vias 132 and 132 connected to the first electrode portion 11a at the upper bottom portion 13w. In the configuration in which the first vias 131 and 131 are formed on the lower bottom 13v and 11v sides, when the vias are not formed on the upper bottom 13w and 11w sides, the ends on the upper bottom 13w and 11w sides are open stubs. It will function as 300 (see FIG. 4 (b)), and the effective facing area of the MIM capacitor will be reduced. In this regard, by connecting the third electrode portion 13a and the first electrode portion 11a on the upper bottom portions 13w and 11w side by the second vias 132 and 132, the end portions on the upper bottom portions 13w and 11w side function as open stubs. This eliminates the problem, and it is possible to suppress a decrease in the effective facing area of the MIM capacitors (first MIM capacitor 101 and second MIM capacitor 102).

The effect of suppressing the decrease in the facing area and securing the capacity value will be described with reference to FIG. FIG. 5 is a graph showing the band improvement and loss improvement effects of MMIC1. In FIG. 5, the horizontal axis is the band (GHz) and the vertical axis is the S parameter (dB). Further, the graph shown by the solid line in FIG. 5 is a graph of the MMIC 501 (MMIC having a two-layer structure) according to the comparative example, and the graph shown by the broken line is a graph of the MMIC having a three-layer structure and without the second vias 132 and 132. The graph shown by the alternate long and short dash line is a graph of MMIC1 (three-layer structure and with second vias 132 and 132) according to this embodiment. As shown in FIG. 5, the three-layer structure MMIC has a band improvement particularly in the low frequency band as compared with the two-layer structure MMIC. Further, when comparing the MMICs having a three-layer structure, the MMICs having the second vias 132 and 132 did not have open stubs at the ends, so that the band was improved especially in the high frequency band.

Further, in the MMIC 1 according to the present embodiment, the second wiring layer 12 has land portions 12b, 12b and land portions 12c, 12c electrically independent of each other as land portions, and the first vias 131, 131 are land portions. The second vias 132 and 132 are connected to the first electrode portion 11a via the land portions 12c and 12c, and are connected to the first electrode portion 11a via the portions 12b and 12b. The first via 131, 131 and the second via 132, 132 are connected to the first electrode portion 11a via the land portions 12b, 12b, 12c, 12c, so that the first via 131, 131 and the second via are respectively. 132 and 132 can be provided more reliably.

Further, in the MMIC 1 according to the present embodiment, the pad portion 13b has a solder ball 13x. As a result, the external configuration such as a printed circuit board and the MMIC 1 can be appropriately connected.

Although the MMIC according to the present embodiment has been described above, the present invention is not limited to these, and various modifications can be applied. It should also be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is indicated by the scope of claims, not the above-mentioned meaning, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims. For example, in the above-mentioned MMIC 1, it has been described that the wiring portion of the first wiring layer 11 is continuous with the wiring structure, that is, the wiring structure is drawn from the first wiring layer 11, but the wiring structure is not limited to this, and FIG. The wiring structure may be drawn out from the second wiring layer 212 as in the MMIC 201 shown in (d).

6A and 6B are views showing MMIC 201 according to a modification of the present invention, where FIG. 6A is a plan view, FIG. 6B is a sectional view taken along line bb of FIG. 6A, and FIG. 6C is FIG. 6A. Is a cross-sectional view taken along the line cc, and (d) is a cross-sectional view taken along the line dd of (a). The MMIC 201 has a first wiring layer 211, an insulator layer 221 (first interlayer film, see FIG. 6C), a second wiring layer 212, and an insulator layer 222 (second interlayer) in this order from the substrate (not shown) side. The film has a structure (three-layer structure) in which the third wiring layer 213 is laminated (see FIG. 6 (c)). The third wiring layer 213 has a third electrode portion 213a having a plan view table shape and a pad portion 213b continuous with the third electrode portion 213a. The first wiring layer 211 has a first electrode portion 211a having a plan view table shape. The second wiring layer 212 has a second electrode portion 212a and a land portion 212b, 212b, 212c, 212c that are electrically independent of each other. The land portions 212b and 212b (first land portions) are provided at both ends in the width direction on the lower bottom side when viewed in a plan view. The land portions 212c and 212c (second land portions) are provided at both ends in the width direction on the upper bottom portion 11w side when viewed in a plan view. The second electrode portion 212a is continuous with the wiring structure and is formed in a substantially trapezoidal shape when viewed in a plan view. However, the second electrode portion 212a is not formed in the region where the plurality of land portions 212b, 212b, 212c, 212c described above are formed.

As shown in FIGS. 6 (b) and 6 (c), the third electrode portion 213a of the third wiring layer 213 is further connected to the first electrode portion 211a of the first wiring layer 211 at the lower bottom portion. It has first vias 231,231 and second vias 232,232 connected to the first electrode portion 211a of the first wiring layer 211 at the upper bottom portion. The first vias 231,231 and the second vias 232,232 are holes (via holes) for the purpose of conduction between the third electrode portion 213a and the first electrode portion 211a, and penetrate the insulator layers 221,222. Is formed in. The first vias 231,231 extend from both ends in the width direction of the lower bottom portion in the direction of the first electrode portion 211a, and are connected to the lower bottom portion of the first electrode portion 211a via the land portions 212b and 212b, respectively. .. The second vias 232 and 232 extend from both ends in the width direction of the upper bottom portion in the direction of the first electrode portion 211a, and are connected to the upper bottom portion of the first electrode portion 211a via the land portions 212c and 212c, respectively. ..

In the MMIC 201 having such a configuration, as shown in FIG. 6D, an insulator interposed between the second electrode portion 212a and the first electrode portion 211a and the second wiring layer 212 and the first wiring layer 211. The first MIM capacitor 251 is formed by the layer 221, and the first MIM is formed by the second electrode portion 212a and the third electrode portion 213a, and the insulator layer 222 interposed between the second wiring layer 212 and the third wiring layer 213. A second MIM capacitor 252 that overlaps the capacitor 251 in the stacking direction is formed. Since the first electrode portion 211a, the second electrode portion 212a, and the third electrode portion 213a all have a planar viewing table shape (or substantially trapezoidal shape), the first MIM capacitor 251 and the second MIM capacitor 252 are viewed in a plan view. Both are formed in a trapezoidal shape with the side on the pad portion 213b side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion.

1,201 ... MMIC (semiconductor device) 11,211 ... 1st wiring layer, 11a, 211a ... 1st electrode section, 11b ... Wiring section, 12,212 ... 2nd wiring layer, 12a, 212a ... 2nd electrode section , 12b, 212b ... Land portion (first land portion), 12c, 212c ... Land portion (second land portion), 13, 213 ... Third wiring layer, 13a, 213a ... Third electrode portion, 13b, 213b ... Pad Unit, 13x ... Solder ball, 21,221 ... Insulator layer (first interlayer film), 22,222 ... Insulator layer (second interlayer film), 101, 251 ... First MIM capacitor, 102, 252 ... Second MIM capacitor , 131,231 ... 1st via, 132,232 ... 2nd via.

Claims (5)

A semiconductor device provided with a first wiring layer, a second wiring layer, and a third wiring layer in order from the substrate side.
The first wiring layer has a first electrode portion and has a first electrode portion.
The second wiring layer has a second electrode portion and a land portion that are electrically independent of each other, and the second electrode portion is continuous with the wiring structure of the semiconductor device.
The third wiring layer has a third electrode portion and a pad portion continuous with the third electrode portion.
A first MIM capacitor is formed by the second electrode portion and the first electrode portion, and the first interlayer film interposed between the second wiring layer and the first wiring layer.
A second MIM capacitor that overlaps with the first MIM capacitor is formed by the second electrode portion and the third electrode portion, and the second interlayer film interposed between the second wiring layer and the third wiring layer.
The first MIM capacitor and the second MIM capacitor are formed in a trapezoidal shape with the side on the pad portion side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion when viewed in a plan view.
The third electrode portion is a semiconductor device having a first via connected to the first electrode portion at the lower bottom portion. A semiconductor device provided with a first wiring layer, a second wiring layer, and a third wiring layer in order from the substrate side.
The first wiring layer has a first electrode portion and a wiring portion independent of the first electrode portion and continuous with the wiring structure of the semiconductor device.
The second wiring layer has a second electrode portion and a land portion that are electrically independent of each other.
The third wiring layer has a third electrode portion and a pad portion continuous with the third electrode portion.
A first MIM capacitor is formed by the second electrode portion and the first electrode portion, and the first interlayer film interposed between the second wiring layer and the first wiring layer.
A second MIM capacitor that overlaps with the first MIM capacitor is formed by the second electrode portion and the third electrode portion, and the second interlayer film interposed between the second wiring layer and the third wiring layer.
The first MIM capacitor and the second MIM capacitor are formed in a trapezoidal shape with the side on the pad portion side as the lower bottom portion and the side on the wiring structure side as the upper bottom portion when viewed in a plan view.
The third electrode portion is a semiconductor device having a first via connected to the first electrode portion at the lower bottom portion. The semiconductor device according to claim 1 or 2, wherein the third electrode portion has a second via connected to the first electrode portion at the upper bottom portion. The second wiring layer has a first land portion and a second land portion that are electrically independent of each other as the land portion.
3. The first via is connected to the first electrode portion via the first land portion, and the second via is connected to the first electrode portion via the second land portion. The semiconductor device described. The semiconductor device according to any one of claims 1 to 4, wherein the pad portion has a solder ball.

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