JP2018137296A - High frequency device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency device suppressed in deterioration of high frequency characteristics due to a pad.SOLUTION: A high frequency device includes: a semiconductor substrate 12 on which a semiconductor element 10 is formed; a reference layer 32 which is provided on an insulating layer 14 provided on the semiconductor substrate and to which a reference potential is supplied; signal wiring 34 provided in the insulting layer to face the reference layer, electrically connected to the semiconductor element, and constituting a transmission line together with the reference layer; and a pad 36 that includes a first region 37a which is provided on the insulating layer to be separated from the reference layer and which is used for mounting, and a second region 37b which is used for a test and which is provided between the first region and the signal wiring 44, the pad being electrically connected to the signal wiring.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a high frequency device, for example, a high frequency device having a transmission line.

  A transmission line such as a microstrip line is used to transmit a high-frequency signal in the high-frequency device. A pad is used for electrical connection between the transmission line and the external circuit. The pad is electrically connected to an external circuit by bonding wires or bumps. It is known to measure a high-frequency characteristic by bringing a probe into contact with a pad (for example, Patent Document 1).

JP-A-8-160084

  If the mounting pad on which the bonding wire or bump is provided and the test pad on which the probe is brought into contact are made common, the trace of the probe becomes an obstacle to providing the bonding wire or bump. If a mounting area and a test area are provided in the pad, the high frequency characteristics deteriorate.

  The present high-frequency device is intended to suppress deterioration of high-frequency characteristics in the pad.

  One embodiment of the present invention includes a semiconductor substrate on which a semiconductor element is formed, a reference layer provided on an insulating layer provided on the semiconductor substrate, to which a reference potential is supplied, and the reference in the insulating layer. A signal wiring that is provided opposite to the layer, is electrically connected to the semiconductor element and forms a transmission line together with the reference layer, and is provided on the insulating layer and spaced apart from the reference layer for mounting. A first region used, and a second region used for testing and provided between the first region and the signal wiring, and a pad electrically connected to the signal wiring. It is a high frequency device.

  According to the high frequency device, it is possible to suppress deterioration of the high frequency characteristics in the pad.

FIG. 1 is a plan view of the high-frequency device according to the first embodiment. FIG. 2 is a cross-sectional view of the vicinity of a pad in which the high-frequency device according to the first embodiment is mounted on a mounting substrate. FIG. 3A and FIG. 3B are plan views of the high frequency device according to the first embodiment as viewed from the bump side. FIG. 4 is a plan view of the mounting substrate in Example 1 as viewed from the bump side. 5A and 5C are plan views of the high-frequency device according to Comparative Example 1 as viewed from the bump side, and FIG. 5B is a cross-sectional view taken along the line AA in FIG. FIG. 6 is a plan view of the high-frequency device according to Comparative Example 1 as viewed from the bump side. FIG. 7A to FIG. 7C are diagrams showing equivalent circuits used in simulations in Example 1 and Comparative Examples 1 and 2, respectively. FIG. 8A is a Smith chart showing S11 in Example 1 and Comparative Examples 1 and 2, and FIG. 8B is a diagram showing S21 with respect to frequency. FIG. 9A is a plan view of the high-frequency device according to the second embodiment as viewed from the bump side. FIG.9 (b) is AA sectional drawing of Fig.9 (a). FIG. 10A is a plan view of the high-frequency device according to Comparative Example 3 as viewed from the bump side, and FIG. 10B is a cross-sectional view taken along line AA of FIG. FIG. 11 is a plan view of the high-frequency device according to Comparative Example 4 as viewed from the bump side. FIG. 12A is a Smith chart showing S11 in Example 2 and Comparative Examples 3 and 4, and FIG. 12B is a diagram showing S21 with respect to frequency.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
(1) In one embodiment of the present invention, a semiconductor substrate on which a semiconductor element is formed, a reference layer provided on an insulating layer provided on the semiconductor substrate, to which a reference potential is supplied, and in the insulating layer And a signal wiring that is electrically connected to the semiconductor element and that constitutes a transmission line together with the reference layer, and is provided on the insulating layer and spaced apart from the reference layer. A pad that includes a first region used for mounting and a second region provided between the first region and the signal wiring used for testing, and is electrically connected to the signal wiring; Is a high-frequency device.
As a result, it is possible to prevent the trace of the test needle from remaining in the pad mounting area and causing a mounting failure. Since the 2nd field used for a test is provided between the 1st field used for mounting, and signal wiring, degradation of the high frequency characteristic in a pad can be controlled.
(2) The width of the second region is preferably larger than the width of the signal wiring. Thereby, deterioration of a high frequency characteristic can be suppressed more.
(3) It is preferable that the pad is provided in an opening formed in the reference layer. This further improves the function of the reference layer as a shield.
(4) It is preferable that the reference layer is provided on both sides of the second region. Thereby, it can test using a coplanar type probe.
(5) Provided in the insulating layer facing the reference layer, one end electrically connected to the first region, the other end electrically connected to the reference layer, and transmitted by the transmission line It is preferable to provide an additional line having a length of less than λ / 4 where λ is the wavelength of the signal to be transmitted. Thereby, deterioration of a high frequency characteristic can be suppressed more.

[Details of the embodiment of the present invention]
Specific examples of the semiconductor device according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to a claim are included.

  FIG. 1 is a plan view of the high-frequency device according to the first embodiment. As shown in FIG. 1, a reference layer 32 is provided on the upper surface of a semiconductor chip 10 that is a high-frequency device. Openings 35 a and 35 b are provided in the reference layer 32. Pads 36a and 36b are provided in the openings 35a and 35b. A semiconductor element 54 is provided on the semiconductor chip 10. Signal wirings 34 a and 34 b are provided facing the reference layer 32. Pads 36a and 36b are connected to semiconductor element 54 through signal wirings 34a and 34b. The high frequency signal input from the pad 36 a is transmitted through the signal wiring 34 a and input to the semiconductor element 54. The high frequency signal output from the semiconductor element 54 is transmitted through the signal wiring 34b and output from the pad 36b.

  The semiconductor chip 10 is, for example, an MMIC (Monolithic Microwave Integrated Circuit). The semiconductor element 54 is, for example, an amplifier using a HEMT (High Electron Mobility Transistor) having an InGaAs layer as a channel layer and AlGaAs as an electron supply layer. The semiconductor element 54 may be a transistor such as an FET (Field Effect Transistor). Also, an electronic circuit other than an amplifier may be used. The semiconductor substrate 12 may have a semiconductor layer (for example, a GaN layer) formed on an insulating substrate (for example, a sapphire substrate) in addition to a semiconductor layer having a semiconductor layer formed on the semiconductor substrate.

  FIG. 2 is a cross-sectional view of the vicinity of a pad in which the high-frequency device according to the first embodiment is mounted on a mounting substrate. As shown in FIG. 2, the semiconductor chip 10 is mounted on the mounting substrate 20 using bumps 30. The extending direction of the signal wiring 34 is the X direction, the width direction of the signal wiring 34 is the Y direction, and the direction in which the semiconductor chip 10 is mounted on the mounting substrate 20 is the Z direction. In the semiconductor chip 10, an FET 11 is formed as a semiconductor element on a semiconductor substrate 12 (lower in FIG. 2, the same applies hereinafter). The FET 11 has a source 11a, a gate 11b, and a drain 11c. An insulating layer 14 is provided on the semiconductor substrate 12. Wiring layers 16 a to 16 c are provided in the insulating layer 14. A metal layer 18 is formed on the semiconductor substrate 12 via an insulating layer 14. Through electrodes 15 a to 15 c are provided that penetrate part of the insulating layer 14 in the vertical direction and electrically connect the wiring layers 16 a to 16 c and the metal layer 18. The insulating layer 14 is a resin layer such as polyimide or BCB (Benzocyclobutene). The through electrodes 15a to 15c, the wiring layers 16a to 16c, and the metal layer 18 are metal layers such as gold, copper, or aluminum.

  The wiring layer 16 a includes a signal wiring 34. The signal wiring 34 is electrically connected to a semiconductor element (such as the semiconductor element 54 and the FET 11 in FIG. 1) formed on the semiconductor substrate 12. The metal layer 18 includes a reference layer 32 and a pad 36. The reference layer 32 is supplied with a reference potential (eg, a DC potential) such as a ground potential. The reference layer 32 and the signal wiring 34 are provided to face each other and form a transmission line 33. The transmission line 33 is a microstrip line. The pad 36 includes a mounting area 37a where the bumps 30 are provided and a test area 37b where the probe contacts. The wiring 17a includes through electrodes 15a to 15c and wiring layers 16b and 16c, and electrically connects the signal wiring 34 and the pad 36.

  A metal layer 28 is formed on the insulating substrate 22. A reference layer 26 is formed on the lower surface of the substrate 22. The metal layer 28 includes a reference layer 42, a pad 46 and a signal wiring 44. A via hole 25 penetrating the substrate 22 is provided. Metal is embedded in the via hole 25. The via hole 25 electrically connects the reference layer 42 and the reference layer 26. A resist 24 is formed on the metal layer 28 as a protective film. The signal wiring 44 and the reference layer 26 form a transmission line 43. The substrate 22 is an insulating layer such as Teflon (registered trademark), resin, or ceramics. The via hole 25, the reference layer 26, and the metal layer 28 are metal layers such as gold or copper. The bumps 30 are metal bumps such as solder, gold or copper.

  The film thicknesses T12, T14, T18, T22, T24, and T28 are the film thicknesses of the semiconductor substrate 12, the insulating layer 14, the metal layer 18, the substrate 22, the resist 24, and the metal layer 28, respectively.

  FIG. 3A and FIG. 3B are plan views of the high frequency device according to the first embodiment as viewed from the bump side. FIG. 2 corresponds to the AA cross section of FIG. The signal wiring 34 in the insulating layer 14 is indicated by a broken line. A reference layer 32 is formed on the upper surface of the semiconductor chip 10 (the lower surface in FIG. 2, the same applies hereinafter). An opening 35 is formed in the reference layer 32. A pad 36 is formed in the opening 35. A signal wiring 34 is formed so as to face the reference layer 32. The pad 36 includes a mounting area 37a and a test area 37b. The test area 37 b is electrically connected between the mounting area 37 a and the signal wiring 34.

  The widths W30, W34, W35a, W35b, W37a, W37b and W37c are respectively the width of the bump 30, the width of the signal wiring 34, the width in the Y direction of the opening 35 around the mounting area 37a, and the area around the test area 37b. The width of the opening 35 in the Y direction, the width of the mounting region 37a, the width of the test region 37b in the Y direction, and the width of the test region 37b in the X direction.

  As shown in FIG. 3B, the test probe head 50 has a ground needle 52b and a signal needle 52a. The ground needle 52b is provided on both sides of the signal needle 52a. When testing the high frequency signal of the high frequency device, the signal needle 52a of the probe head 50 is in contact with the test region 37b, and the ground needle 52b is in contact with the reference layers 32 on both sides of the mounting region 37a. Thus, the probe head 50 is a coplanar type.

  FIG. 4 is a plan view of the mounting substrate in Example 1 as viewed from the bump side. The bumps 30, the via holes 25, and the semiconductor chip 10 are indicated by broken lines. FIG. 2 corresponds to the AA cross section of FIG. As shown in FIG. 4, a reference layer 42 is formed so as to face the reference layer 32 of the semiconductor chip 10. A cut 45 is formed in the reference layer 42. The pad 46 is formed in the notch 45. The signal wiring 44 is electrically connected to the pad 46. Bumps 30 are connected on pads 46 and on reference layer 42. A via hole 25 is connected to the reference layer 42.

  The widths W25, W30, W31, W44, W45, and W46 are the width of the via hole 25, the width of the bump 30, the pitch width of the bump 30, the width of the signal wiring 44, the width of the cut 45, and the width of the pad 46, respectively.

[Comparative Example 1]
A comparative example for explaining the effect of the first embodiment will be described. 5A and 5C are plan views of the high-frequency device according to Comparative Example 1 as viewed from the bump side, and FIG. 5B is a cross-sectional view taken along the line AA in FIG. As shown in FIGS. 5A and 5B, the mounting area 37 a of the pad 36 is provided between the test area 37 b and the signal wiring 34. A wide wiring 34 c is provided between the signal wiring 34 and the pad 36. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  As shown in FIG. 5C, when testing a high frequency signal of the high frequency device, the signal needle 52a of the probe head 50 is in contact with the test region 37b, and the ground needle 52b is a reference on both sides of the mounting region 37a. Contact layer 32.

[Comparative Example 2]
FIG. 6 is a plan view of the high-frequency device according to Comparative Example 1 as viewed from the bump side. As shown in FIG. 6, the test area 37 b is not provided in the pad 36. A wide wiring 34 c is provided between the signal wiring 34 and the pad 36. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  The test region 37b of Example 1 and the wide wiring 34c of Comparative Examples 1 and 2 function as a capacitance component for matching the impedance between the transmission line 33 and the mounting region 37a (the pad 36 in Comparative Example 2). . Since the mounting region 37a functions as a capacitor, if the test region 37b of Example 1 and the wide wiring 34c of Comparative Examples 1 and 2 are provided, the capacitance component further increases and the impedance between the transmission line 33 and the mounting region 37a. It may be difficult to align.

  In the above consideration, the mounting region 37a and the wide wiring 34c are regarded as a lumped constant circuit. However, at a high frequency (for example, millimeter wave) such as 60 GHz or more, the pad 36 functions as a distributed constant circuit, not as a lumped constant circuit. Therefore, the mounting region 37 a is considered separately on the transmission line 33 side and the opposite side of the transmission line 33. The transmission line 33 side of the mounting region 37a functions as a capacitor for impedance matching between the transmission line 33 and the mounting region 37a. However, unless the test region 37b or the wide wiring 34c is provided on the transmission line 33 side, the capacitance on the transmission line 33 side of the mounting region 37a is not sufficient. Therefore, a test region 37b or a wide wiring 34c is provided on the transmission line 33 side. As a result, the capacitance of the test region 37b or the wide wiring 34c is added to the capacitance of the mounting region 37a on the transmission line 33 side. Therefore, impedance matching between the transmission line 33 and the mounting region 37a is improved. The capacitance component on the opposite side of the transmission line 33 in the mounting region 37a makes impedance matching between the transmission line 33 and the mounting region 37a difficult. This point will be described in the second embodiment.

  For Example 1 and Comparative Examples 1 and 2, the reflection characteristics and transmission characteristics of the transmission line 43 viewed from the transmission line 43 were simulated using the electromagnetic field analysis method. FIG. 7A to FIG. 7C are diagrams showing equivalent circuits used in simulations in Example 1 and Comparative Examples 1 and 2, respectively. As shown in FIG. 7A, in the first embodiment, the bump 30 is equivalently represented by an inductor L1, an inductor L2, and a capacitor C1. The inductor L1 and the inductor L2 are connected in series between the mounting region 37a and the pad 46. The capacitor C1 is connected between a node between the inductor L1 and the inductor L2 and a reference potential. The inductance of the inductor L1 and the inductor L2 was 5 pH, respectively, and the capacitance of the capacitor C1 was 15 pF.

  The mounting region 37a and the pad 46 are equivalently represented by using the transmission line L3 and the transmission line L4, respectively. The test region 37b is a transmission line L6 provided between the mounting region 37a and the transmission line 33 and equivalently functioning as a shunt capacitor. The transmission line 33 is a transmission line L5 and is terminated with a resistor R1. The resistance value of the resistor R1 was 50Ω. The resistor R1 is a resistor formed in the semiconductor substrate 12. The lengths of the transmission lines L4 to L6 were set so as to represent the pads 36 and 46 equivalently. The transmission line 43 formed on the mounting substrate 20 was used as the terminal T1, and S11 in which the bump 30 was seen from the terminal T1 was simulated.

  As shown in FIG. 7B, in Comparative Example 1, the test area 37b is connected to the mounting area 37a as an open stub. The wide wiring 34c is provided between the mounting region 37a and the transmission line 33, and is equivalent to a transmission line L7 that functions as a shunt capacitor. Other equivalent circuits are the same as those in the first embodiment.

  As shown in FIG. 7C, in Comparative Example 2, the test region 37b is not provided. Other equivalent circuits are the same as those in Comparative Example 1.

The simulation conditions are shown below.
Semiconductor substrate 12: GaAs substrate, film thickness H12 = 250 μm
Insulating layer 14: polyimide, relative dielectric constant 3.5, film thickness H14 = 8 μm
Metal layer 18: gold, film thickness H18 = 2 μm
Bump 30: Solder: Film thickness H30 = 100 μm, width W30 = 150 μm, pitch width W31 = 400 μm
Signal wiring 34: characteristic impedance 50Ω, width W34 = 10 μm
Wide wiring 34c: width W34c = 100 μm, W34d = 30 μm
Opening 35: width W35a = 250 μm, W35b = 180 μm
Mounting area 37a: width W37a = 150 μm
Test area 37b: width W37a = 100 μm, W37c = 57 μm
Substrate 22: Teflon (registered trademark), film thickness H22 = 101 μm
Resist 24: Film thickness H24 = 30 μm
Via hole 25: copper, width W25 = 100 μm
Metal layer 28: Copper, film thickness H24 = 30 μm
Signal wiring 44: characteristic impedance 50Ω, width W44 = 190 μm
Cut 45: width W45 = 100 μm
Pad 46: Width W46 = 250 μm

  FIG. 8A is a Smith chart showing S11 in Example 1 and Comparative Examples 1 and 2, and FIG. 8B is a diagram showing S21 with respect to frequency. In Comparative Example 2, the width of the wide wiring 34c is set so that the input impedance viewed from the transmission line 43 approaches 50Ω, which is the characteristic impedance of the transmission line 33 (that is, the transmission line 33 and the pad 36 approach impedance matching). It was adjusted.

  In Comparative Example 2, when the high frequency characteristics of the semiconductor chip 10 are to be measured before the semiconductor chip 10 is mounted on the mounting substrate 20, the needle 52a (see FIG. 3B) of the probe head 50 for measurement is applied to the pad 36. Make contact. A trace of the needle 52a remains on the surface of the pad 36. This trace becomes an obstacle for providing the bump 30. Therefore, in Comparative Example 1, a mounting region 37a and a test region 37b are provided in the pad 36. The mounting region 37a is a region to which the bumps 30 or the like (or bonding wires) are connected. The test area 37b is an area where the needle 52a of the probe head 50 contacts. Thereby, it can suppress that the trace of the needle | hook 52a becomes the obstruction which provides the bump 30 (or bonding wire).

  As shown in FIG. 8A, in Comparative Examples 1 and 2, S11 is located at the same level from the center of the Smith chart. This indicates that the comparative examples 1 and 2 have the same input impedance. As shown in FIG. 8B, S21 is smaller in Comparative Example 1 than in Comparative Example 2. This indicates that Comparative Example 1 has a larger passage loss from transmission line 43 to 33 than Comparative Example 2. The reason why the loss increases in Comparative Example 1 is considered that the test region 37b functions as an open stub. As described above, in Comparative Example 1, it is possible to suppress the trace of the needle 52a of the probe head 50 from becoming an obstacle to the bump 30, but the high frequency characteristics are deteriorated.

  In the first embodiment, a test region 37b is provided instead of the wide wiring 34c. The dimensions of the test region 37b were adjusted so that the input impedance approached 50Ω. As shown in FIG. 8A, in Example 1, S11 is closer to the center of the Smith chart than in Comparative Examples 1 and 2. This indicates that the input impedance is closer to 50Ω in the first embodiment than in the first and second comparative examples. As shown in FIG. 8B, S21 is larger in the second embodiment than in the first comparative example. This indicates that the loss in Example 2 is smaller than that in Comparative Example 1. At 86 GHz, the loss of Example 2 is 0.2 dB smaller than Comparative Example 1.

  According to the first embodiment, the pad 36 includes a mounting region 37a (first region) used for mounting and a testing region 37b (second region) used for testing. Thereby, it can suppress that the trace of the needle | hook 52a becomes the obstruction which provides the bump 30 (or bonding wire). The test area 37 b is provided between the mounting area 37 a and the signal wiring 34. Thereby, deterioration of high frequency characteristics, such as deterioration of passage loss property by the test area | region 37b like the comparative example 1 functioning as an open stub, can be suppressed. The test region 37b adds a capacitance component to the mounting region 37a on the transmission line 33 side. Therefore, the impedances of the transmission line 33 and the mounting area 37a on the transmission line 33 side are more matched.

  Further, the width W37c of the test region 37b is larger than the width W34 of the signal wiring 34. Thereby, the capacitance component of the test region 37b is increased, and impedance matching between the transmission line 33 and the mounting region 37a can be facilitated. The width W37c of the test region 37b is preferably smaller than the width W37a of the mounting region 37a. Thereby, it can suppress that the capacitance component of the area | region 37b for a test becomes large too much.

  The reference layer 32 may be provided to face the signal wiring 34, but the pad 36 is preferably provided in the opening 35 formed in the reference layer 32. Thereby, the reference layer 32 can be provided on almost the entire surface other than the pad 36, and the function of the reference layer 32 as a shield is further improved.

  It is preferable that the reference layer 32 is provided on both sides of the test region 37b. Thereby, a coplanar type probe head 50 can be used as shown in FIG.

  The high frequency signal transmitted through the transmission line 33 may be 60 GHz or less. As the frequency increases (for example, 60 GHz or more), the influence of the test area 37b increases. Therefore, by providing the test region 37b between the mounting region 37a and the transmission line 33, the high frequency characteristics can be further improved. The improvement effect becomes more conspicuous for high-frequency signals of 80 GHz or higher.

  It is preferable that the mounting region 37a and the transmission line 33 are disposed on the opposite sides of the test region 37b. Thereby, the impedance of the mounting area | region 37a and the transmission line 33 can be matched more by the test area | region 37b.

  By making the mounting region 37a circular, the area of the mounting region 37a can be reduced. By making the test region 37b rectangular, the impedance of the transmission line 33 and the mounting region 37a can be matched more.

  FIG. 9A is a plan view of the high-frequency device according to the second embodiment as viewed from the bump side. FIG.9 (b) is AA sectional drawing of Fig.9 (a). As shown in FIGS. 9A and 9B, the wiring layer 16 a includes the additional wiring 38. One end of the additional wiring 38 is electrically connected to the mounting region 37a of the pad 36 through the wiring 17b. The other end of the additional wiring 38 is electrically connected to the reference layer 32 through the wiring 17c. The reference layer 32 and the additional wiring 38 are provided to face each other with the insulating layer 14 interposed therebetween. The additional wiring 38 and the reference layer 32 function as a transmission line such as a microstrip line. The length of the additional wiring 38 is L38. Other configurations are the same as those of the first embodiment.

  A line from the mounting region 37a including the additional wiring 38 and the wirings 17b and 17c to the reference layer 32 functions as a short stub. However, since the wirings 17b and 17c are much shorter than the additional wiring 38, the length of the additional wiring 38 is substantially the length of the short stub. The additional wiring 38 has a length of less than λ / 4, where λ is the wavelength of the high-frequency signal transmitted through the transmission line 33. As a result, the additional wiring 38 appears as an inductor to the high-frequency signal.

  As described above, the mounting area 37a of the pad 36 is divided into the transmission line 33 side and the opposite side. The opposite side of the pad 36 from the transmission line 33 functions as a shunt capacitor added to the line between the transmission lines 33 and 43. Thereby, the impedances of the transmission lines 33 and 44 are not matched, and the reflection characteristics of the high-frequency signal are deteriorated. Therefore, the additional wiring 38 functioning as an inductor is connected to the mounting region 37a. Thereby, the capacitance component on the opposite side to the transmission line 33 in the mounting region 37a is compensated. Therefore, reflection of the high frequency signal by the mounting region 37a can be suppressed.

  The short stub may be formed of the metal layer 18 on the surface of the semiconductor chip 10 or the metal layer 28 on the surface of the mounting substrate 20. However, the distance between the pad 36 and the reference layer 32 and the distance between the pad 46 and the reference layer 42 cannot be changed greatly. For this reason, the electrical length of the short stub cannot be arbitrarily set. In the second embodiment, the short stub is formed including the additional wiring 38 facing the reference layer 32. For this reason, the electrical length of the short stub can be arbitrarily set by adjusting the length of the additional wiring 38. Therefore, the electrical length of the short stub can be designed according to the frequency of the high frequency signal. A short stub is formed using the wiring layer 16 formed on the semiconductor substrate 12. Thereby, a short stub can be formed with a sufficient size accuracy. Therefore, compared with the case where the short stub is formed on the mounting substrate 20, it is possible to suppress the influence of the variation in the high frequency characteristics.

[Comparative Example 3]
10A is a plan view of the high-frequency device according to Comparative Example 3 as viewed from the bump side, and FIG. 10B is a cross-sectional view taken along line AA of FIG. As shown in FIGS. 10A and 10B, the additional wiring 38 is connected to the bumps 36 as compared with the first comparative example. Other configurations are the same as those of the second embodiment and the first comparative example, and the description thereof is omitted.

[Comparative Example 4]
FIG. 11 is a plan view of the high-frequency device according to Comparative Example 4 as viewed from the bump side. As shown in FIG. 11, the additional wiring 38 is connected to the pad 36 of the second comparative example. Other configurations are the same as those of the second embodiment and the second comparative example, and the description thereof is omitted.

  With respect to Example 2 and Comparative Examples 3 and 4, the reflection characteristics and transmission characteristics viewed from the signal wiring 44 were simulated using an electromagnetic field analysis method. The equivalent circuit used for the simulation of Example 2 and Comparative Examples 3 and 4 is obtained by connecting a short stub to the pad 36 in the equivalent circuit of Example 1 and Comparative Examples 1 and 2.

The simulation conditions were the same as in Example 1 and Comparative Examples 1 and 2, and the length L38 of the additional wiring 38 was as follows.
Example 2: L38 = 70 μm
Comparative Example 3: L38 = 30 μm
Comparative Example 4: L38 = 30 μm
Each L38 was optimized so that the input impedance seen from the transmission line 43 approached 50Ω.

  FIG. 12A is a Smith chart showing S11 in Example 2 and Comparative Examples 3 and 4, and FIG. 12B is a diagram showing S21 with respect to frequency. As shown in FIG. 12A, in both Example 2 and Comparative Examples 3 and 4, S11 can be set near the center of the Smith chart by adjusting the length of the additional wiring 38. That is, the input impedance can be around 50Ω. This is because the additional wiring 38 functions as an inductance component, and compensates for the capacitance component on the opposite side of the transmission line 33 in the mounting region 37a.

  As shown in FIG. 12B, in Example 2, S21 is larger than that in Comparative Example 3, and is about the same as that in Comparative Example 4. That is, Example 2 has the same loss as Comparative Example 4. Thus, in the second embodiment, the input impedance can be made closer to 50Ω than in the first embodiment. Further, even if the test region 37 b is provided in the pad 36, the loss can be made comparable to that in the comparative example 4.

  According to the second embodiment, one end of the additional wiring 38 (additional line) is electrically connected to the mounting region 37 a and the other end is electrically connected to the reference layer 32. The additional wiring 38 has a length less than λ / 4, where λ is the wavelength of the signal transmitted through the transmission line 33. As a result, the additional wiring 38 compensates for the capacitance component on the opposite side of the transmission line 33 in the mounting region 37a, matches the impedance between the transmission line 33 and the pad 36, and allows the input impedance to approach 50Ω. The length of the additional wiring 38 is preferably λ / 12 or more and 3λ / 12 or less. For example, the length of the additional wiring 38 is preferably λ / 6.

  The additional wiring 38 is preferably connected to the side opposite to the transmission line 33 in the mounting region 37a. Thereby, the capacitance component of the area | region on the opposite side to the transmission line 33 of the mounting area | region 37a can be compensated more. For example, the angle between the direction in which the signal wiring 34 extends from the mounting region 37a and the direction in which the additional wiring 38 extends from the mounting region 37a is preferably 90 ° or more.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

10 Semiconductor chip 11 FET
12 Semiconductor substrate 14 Insulating layer 15a-15c Through electrode 16, 16a-16c Wiring layer 17a-17c Wiring 18 Metal layer 20 Mounting substrate 22 Substrate 24 Resist 25 Via hole 26 Reference layer 28 Metal layer 30 Bump 32 Reference layer 33 Transmission line 34, 34a, 34b Signal wiring 34c Wide wiring 35, 35a, 35b Opening 36 Pad 37a Mounting area 37b Test wiring 38 Additional wiring 42 Reference layer 43 Transmission line 44 Signal wiring 45 Cut 46 Pad 50 Probe head 52a, 52b Needle Semiconductor element 54

Claims (5)

A semiconductor substrate on which a semiconductor element is formed;
A reference layer provided on an insulating layer provided on the semiconductor substrate and supplied with a reference potential;
A signal wiring provided in the insulating layer opposite to the reference layer, electrically connected to the semiconductor element, and constituting a transmission line together with the reference layer;
A first region provided on the insulating layer and spaced from the reference layer and used for mounting; a second region used for testing and provided between the first region and the signal wiring; A pad electrically connected to the signal wiring;
A high frequency device comprising:   The high frequency device according to claim 1, wherein a width of the second region is larger than a width of the signal wiring.   The high frequency device according to claim 1, wherein the pad is provided in an opening formed in the reference layer.   4. The high-frequency device according to claim 1, wherein the reference layer is provided on both sides of the second region. 5. Provided in the insulating layer facing the reference layer, one end electrically connected to the first region, the other end electrically connected to the reference layer, and a signal transmitted through the transmission line 5. The high-frequency device according to claim 1, further comprising an additional line having a length of less than λ / 4 when the wavelength is λ.

Images