JPH11186458A - Connecting structure for transmission path for high frequency and wiring board - Google Patents

Connecting structure for transmission path for high frequency and wiring board

Info

Publication number
JPH11186458A
JPH11186458A JP9352947A JP35294797A JPH11186458A JP H11186458 A JPH11186458 A JP H11186458A JP 9352947 A JP9352947 A JP 9352947A JP 35294797 A JP35294797 A JP 35294797A JP H11186458 A JPH11186458 A JP H11186458A
Authority
JP
Japan
Prior art keywords
coplanar line
line
dielectric substrate
center conductor
coplanar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9352947A
Other languages
Japanese (ja)
Other versions
JP3462062B2 (en
Inventor
Kenji Kitazawa
謙治 北澤
Shinichi Koriyama
慎一 郡山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP35294797A priority Critical patent/JP3462062B2/en
Publication of JPH11186458A publication Critical patent/JPH11186458A/en
Application granted granted Critical
Publication of JP3462062B2 publication Critical patent/JP3462062B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/1423Monolithic Microwave Integrated Circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations

Abstract

PROBLEM TO BE SOLVED: To provide a connecting structure for transmission paths for high frequencies with high reliability, in which transmission paths for high frequencies formed on the both faces of a dielectric substrate are formed in a simple structure with a small transmission loss. SOLUTION: A connection structure of a co-planar line A and a co-planar line B is composed of central conductors 2 and 4 having terminal parts 2a and 4a, and ground layers 3 and 5 formed at the both sides and surrounding of the terminal parts which are formed on the both sides of a dielectric substrate 1. A discrete distance (y) between the ground layers 3 and 5 in the periphery of the terminal parts 2a and 4a of the co-planar line A and the co-planar line B is formed so as to be larger than a discrete distance (x) at the line parts, and the terminal parts 2a and 4a are arranged so as to be made in parallel like a plane, and so as to be overlapped on each other. Thus, the first co-planar line A and the second co-planar line B are electromagnetically connected.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子、受動
部品、接続用端子間を相互に接続することが可能であっ
て、高周波信号の特性劣化を低減して特定周波数のみを
透過させることができる高周波用伝送線路の接続構造、
およびかかる接続構造を具備した配線基板に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is capable of interconnecting a semiconductor element, a passive component, and a connection terminal, and is capable of reducing deterioration of characteristics of a high-frequency signal and transmitting only a specific frequency. Connection structure for high-frequency transmission lines,
And a wiring board having such a connection structure.

【0002】[0002]

【従来技術】従来より、半導体素子を気密に封止するた
めの半導体素子用パッケージにおいては、誘電体材料か
らなる誘電体基板と蓋により形成かれたキャビティ内に
半導体素子を搭載して気密に封止した構造が知られてい
る。また、このようなパッケージにおいて周波数が1G
Hz以上のマイクロ波の信号を取り扱う場合、半導体素
子への高周波信号の入出力は、図5(a)に示されるよ
うに、誘電体基板31の半導体素子32搭載面にマイク
ロストリップ線路等の高周波用伝送線路33を形成し、
その一端がワイヤボンディングリボン等で半導体素子3
2と接続し、その伝送線路33を壁体34を通過してキ
ャビティ35外に引き出したフィードスルー型の半導体
用パッケージが考案されている。
2. Description of the Related Art Conventionally, in a semiconductor element package for hermetically sealing a semiconductor element, a semiconductor element is mounted in a cavity formed by a dielectric substrate and a lid made of a dielectric material and hermetically sealed. Stopped structures are known. In such a package, the frequency is 1G.
When a microwave signal of not less than Hz is handled, the input and output of a high-frequency signal to and from the semiconductor element are performed on the surface of the dielectric substrate 31 on which the semiconductor element 32 is mounted, as shown in FIG. Forming the transmission line 33 for
One end of the semiconductor element 3 is a wire bonding ribbon or the like.
2, a feed-through type semiconductor package in which the transmission line 33 is passed through the wall 34 and drawn out of the cavity 35 has been devised.

【0003】また、高周波信号を垂直方向に伝送する手
法としては、図5(b)に示すように、誘電体基板31
の底面に同様に高周波用伝送線路36を形成し、キャビ
ティ35内の高周波用伝送線路33と、スルーホール導
体37を介して接続した半導体素子用パッケージが多く
用いられている。
As a technique for transmitting a high-frequency signal in the vertical direction, as shown in FIG.
Similarly, a semiconductor device package in which a high-frequency transmission line 36 is similarly formed on the bottom surface of the semiconductor device and is connected to the high-frequency transmission line 33 in the cavity 35 via a through-hole conductor 37 is often used.

【0004】さらに、誘電体基板31としては、その配
線の形成の信頼性、価格などの点からアルミナセラミッ
クスが最も多く用いられている。
Further, as the dielectric substrate 31, alumina ceramics are most often used in terms of reliability of wiring formation, cost, and the like.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、図5
(a)のように、伝送線路33が壁体34を通過する場
合、壁体通過部がマイクロストリップ線路からストリッ
プ線路への変換されるために、信号線路幅を狭くする必
要がある。その結果、この通過部で反射損、放射損が発
生しやすいため高周波信号の特性劣化が起こりやすくな
るという問題がある。
However, FIG.
As shown in (a), when the transmission line 33 passes through the wall 34, since the wall passing portion is converted from the microstrip line to the strip line, it is necessary to narrow the signal line width. As a result, there is a problem that reflection loss and radiation loss are apt to occur in the passing portion, so that the characteristics of the high-frequency signal are likely to deteriorate.

【0006】これに対して、図5(b)のパッケージで
は、伝送線路が壁体34を通過しないために、信号特性
劣化が小さいが、誘電体基板31として、従来から用い
られるアルミナセラミックスを用いる場合等において、
伝送する信号の使用周波数が10GHz以上になるとス
ルーホール導体での透過損失が急激に大きくなるため
に、高周波領域の信号を特性劣化なく伝送することが困
難であった。
On the other hand, in the package of FIG. 5 (b), although the transmission line does not pass through the wall 34, the signal characteristic deterioration is small, but conventionally used alumina ceramic is used as the dielectric substrate 31. In some cases,
When the operating frequency of the signal to be transmitted is 10 GHz or higher, the transmission loss in the through-hole conductor increases rapidly, and it has been difficult to transmit the signal in the high-frequency region without characteristic deterioration.

【0007】従って、本発明は、誘電体基板の両面に形
成された高周波用伝送線路を伝送損失が小さく、且つ簡
略した構造からなり小型化が可能な高信頼性の高周波用
伝送線路の接続構造と、かかる高周波用伝送線路の接続
構造を利用した配線基板を提供することを目的とするも
のである。
Accordingly, the present invention provides a high-reliability high-frequency transmission line connection structure in which a high-frequency transmission line formed on both surfaces of a dielectric substrate has a small transmission loss and a simplified structure and can be miniaturized. It is another object of the present invention to provide a wiring board using the connection structure of the high-frequency transmission line.

【0008】[0008]

【課題を解決するための手段】本発明者らは、上記の目
的に対して検討を行った結果、誘電体基板の両面に、中
心導体と、グランド層からなるコプレーナ線路をそれぞ
れ形成するとともに、それらを特定位置に配置すること
により、両線路を電磁的に結合せしめることにより、伝
送損失の小さい接続構造となることを見いだし、本発明
に至った。
Means for Solving the Problems As a result of the study on the above object, the present inventors have formed a central conductor and a coplanar line composed of a ground layer on both surfaces of a dielectric substrate, respectively. By arranging them at a specific position and electromagnetically coupling both lines, it has been found that a connection structure with a small transmission loss is obtained, and the present invention has been accomplished.

【0009】即ち、本発明の高周波用伝送線路の接続構
造は、誘電体基板の一方の表面に形成され、終端部を有
する第1の中心導体と、その両側に形成された第1のグ
ランド層とからなる第1のコプレーナ線路と、前記誘電
体基板の他方の表面に形成され、終端部を有する第2の
中心導体と、その両側に形成された第2のグランド層と
からなる第2のコプレーナ線路とを具備し、前記第1の
コプレーナ線路および前記第2のコプレーナ線路におけ
る各中心導体の終端部付近両側の前記グランド層との離
間距離を他の線路部分よりも大きくなるように形成する
とするとともに、前記第1の中心導体と前記第2の中心
導体とを平面的にみて互いの終端部が平行且つ一部が重
なるように配置して、前記第1のコプレーナ線路と1 前
記第2のコプレーナ線路とを電磁結合せしめたことを特
徴とするものである。
That is, a connection structure of a high-frequency transmission line according to the present invention comprises a first center conductor formed on one surface of a dielectric substrate and having a termination, and first ground layers formed on both sides thereof. A second coaxial conductor formed on the other surface of the dielectric substrate and having a termination, and a second ground layer formed on both sides of the second coaxial conductor. And a coplanar line, wherein the first coplanar line and the second coplanar line are formed so that the separation distance from the ground layer on both sides near the end portion of each central conductor is larger than other line portions. In addition, the first central conductor and the second central conductor are arranged so that their end portions are parallel and partially overlap with each other when viewed in a plan view, so that the first coplanar line and the second Coplay A line is characterized in that the allowed electromagnetic coupling.

【0010】また、本発明の配線基板は、誘電体基板
と、該誘電体基板の一方の表面に設けられた電気素子
と、前記誘電体基板の一方の表面に形成され一端が前記
電気素子と電気的に接続された、終端部を有する第1の
中心導体と、その両側に形成された第1のグランド層と
からなる第1のコプレーナ線路と、前記誘電体基板の他
方の表面に形成され、終端部を有する第2の中心導体
と、その両側に形成された第2のグランド層とからなる
第2のコプレーナ線路とを具備してなり、前記第1のコ
プレーナ線路および前記第2のコプレーナ線路における
各中心導体の終端部付近両側の前記グランド層との離間
距離を他の線路部分よりも大きくなるように形成すると
するとともに、前記第1の中心導体と前記第2の中心導
体とを平面的にみて互いの終端部が平行且つ一部が重な
るように配置して、前記第1のコプレーナ線路と前記第
2のコプレーナ線路とを電磁結合せしめたことを特徴と
するものである。
Further, the wiring board of the present invention comprises a dielectric substrate, an electric element provided on one surface of the dielectric substrate, and one end formed on one surface of the dielectric substrate and having one end connected to the electric element. A first coplanar line that is electrically connected and includes a first central conductor having a terminal portion and first ground layers formed on both sides thereof; and a first coplanar line formed on the other surface of the dielectric substrate. And a second coplanar line composed of a second center conductor having a termination portion and second ground layers formed on both sides of the second center conductor, and wherein the first coplanar line and the second coplanar line are provided. The distance between the center layer and the ground layer on both sides near the end of each center conductor in the line is formed so as to be larger than the other line portions, and the first center conductor and the second center conductor are formed in a plane. In terms of each other It arranged such termination overlap parallel and partially and said first coplanar line and the second coplanar line is characterized in that the allowed electromagnetic coupling.

【0011】なお、上記においてコプレーナ線路に対し
ては、周波数が1GHz以上の信号が伝送されるもので
あることが望ましい。
In the above, it is desirable that a signal having a frequency of 1 GHz or more is transmitted to the coplanar line.

【0012】[0012]

【作用】本発明によれば、誘電体基板の一方の表面に第
1のコプレーナ線路と、他方の表面に第2のコプレーナ
線路を形成し、両者を特定条件にて誘電体基板を介して
対峙させて電磁結合することにより、スルーホール導体
やビアホール導体等による透過損失の影響を受けること
なく、良好な伝送特性で信号の伝達を行うことができ
る。
According to the present invention, a first coplanar line is formed on one surface of a dielectric substrate and a second coplanar line is formed on the other surface, and both are opposed to each other via a dielectric substrate under specific conditions. By performing electromagnetic coupling, signals can be transmitted with good transmission characteristics without being affected by transmission loss due to through-hole conductors, via-hole conductors, and the like.

【0013】従って、例えば、半導体素子用パッケージ
等の配線基板において、半導体素子搭載面に第1のコプ
レーナ線路を形成し、底面に第2のコプレーナ線路を形
成し、両者を電磁結合することにより、高周波信号の伝
送損失の発生を抑制し、高信頼性の配線基板を提供でき
る。
Accordingly, for example, in a wiring board such as a package for a semiconductor element, a first coplanar line is formed on a semiconductor element mounting surface, a second coplanar line is formed on a bottom surface, and both are electromagnetically coupled. It is possible to suppress the occurrence of transmission loss of a high-frequency signal and provide a highly reliable wiring board.

【0014】[0014]

【発明の実施の形態】本発明の高周波用伝送線路の接続
構造を図1をもとに説明する。図1において、(a)は
誘電体基板の表面の導体パターンを示す図、(b)は、
(a)におけるA−A断面図、(c)は誘電体基板の裏
面の導体パターンを示す図である。図1によれば、誘電
体基板1の一方の表面には、終端部2aを有する第1の
中心導体2と、その両側および終端部2aの周囲に形成
された第1のグランド層3とからなる第1のコプレーナ
線路Aが形成される。一方、誘電体基板1の他方の表面
にも、同様に終端部4aを有する第2の中心導体4と、
その両側およびその周囲に形成された第2のグランド層
5とからなる第2のコプレーナ線路Bが被着形成されて
いる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A connection structure of a high-frequency transmission line according to the present invention will be described with reference to FIG. 1A is a diagram showing a conductor pattern on the surface of a dielectric substrate, and FIG.
FIG. 3A is a cross-sectional view taken along line AA, and FIG. 3C is a diagram illustrating a conductor pattern on the back surface of the dielectric substrate. According to FIG. 1, on one surface of a dielectric substrate 1, a first central conductor 2 having a termination 2a and a first ground layer 3 formed on both sides thereof and around the termination 2a. A first coplanar line A is formed. On the other hand, on the other surface of the dielectric substrate 1, a second center conductor 4 also having a termination portion 4a is provided.
A second coplanar line B composed of a second ground layer 5 formed on both sides and the periphery thereof is formed.

【0015】コプレーナ線路Aにおいては、中心導体2
の両側には、線路部分においては離間間隔xをもって、
また中心導体2の終端部2a付近の両側においては離間
距離yをもって、且つ離間距離yが、前記線路部分の間
隔xよりも大きくなるようにグランド層3が形成されて
いる。この中心導体2のグランド層3との離間距離は、
特性インピーダンスの整合を図る上で必要であり、例え
ば、誘電率5.5からなる誘電体基板を用いた場合、x
は0.05mm、yは0.15mmに設計される。この
時のx、yの関係が、x=y、あるいはx>yの関係で
は、終端部における急激な特性インピーダンス不整合が
生じるため反射が生じ、伝送特性が劣化する原因となっ
てしまう。
In the coplanar line A, the center conductor 2
On both sides of the line, with a spacing x in the line section,
The ground layer 3 is formed on both sides near the terminal end 2a of the center conductor 2 so that the separation distance y is greater than the distance x between the line portions. The distance between the center conductor 2 and the ground layer 3 is
Necessary for matching characteristic impedance. For example, when a dielectric substrate having a dielectric constant of 5.5 is used, x
Is designed to be 0.05 mm and y is designed to be 0.15 mm. If the relationship between x and y at this time is x = y or x> y, abrupt characteristic impedance mismatching occurs at the terminating end, causing reflection and causing deterioration of transmission characteristics.

【0016】一方、コプレーナ線路Bにおいても、中心
導体4、終端部4aおよびグランド層5もコプレーナ線
路Aと全く同様な終端構造からなる。
On the other hand, also in the coplanar line B, the center conductor 4, the terminal 4a, and the ground layer 5 have the same terminal structure as the coplanar line A.

【0017】そして、コプレーナ線路A,Bとは、誘電
体基板1を介して、図1(a)(b)(c)に示される
通り、前記第1の中心導体2の終端部2aと、第2の中
心導体4の終端部4aとを平面的にみて互いに平行に,
且つ互いの終端部が重なるように配置されている。この
時の重なり部分の長さzは、伝送信号波長λの1/4波
長相当長さとなるように設計することにより、コプレー
ナ線路Aと、コプレーナ線路Bとを透過周波数領域で電
磁的に結合することができる。
As shown in FIGS. 1A, 1B and 1C, the coplanar lines A and B are connected to the terminal 2a of the first central conductor 2 via the dielectric substrate 1. The end portion 4a of the second center conductor 4 is parallel to each other when viewed in plan,
In addition, they are arranged so that their end portions overlap each other. At this time, the length z of the overlapping portion is designed to be a length corresponding to 1 / wavelength of the transmission signal wavelength λ, so that the coplanar line A and the coplanar line B are electromagnetically coupled in the transmission frequency region. be able to.

【0018】なお、本発明の接続構造においては、第1
のコプレーナ線路Aおよび第2のコプレーナ線路Bは、
誘電体基板1が介在した構造からなる結果、第1のコプ
レーナ線路Aおよび第2のコプレーナ線路Bは、いずれ
もグランド付きコプレーナ線路となる。また、第1のコ
プレーナ線路Aにおけるグランド層3と、第2のコプレ
ーナ線路Bにおけるグランド層5とは、例えば、スルー
ホール導体6によって電気的に接続して等電位とするこ
とが望ましい。また、終端部の周囲のグランド層には、
伝送信号の波長λの1/4波長未満の間隔で複数のスル
ーホール導体7を形成して、電磁結合部を電磁的に囲む
ことが望ましい。
In the connection structure of the present invention, the first
The coplanar line A and the second coplanar line B of
As a result of the structure in which the dielectric substrate 1 is interposed, each of the first coplanar line A and the second coplanar line B is a coplanar line with ground. Further, it is desirable that the ground layer 3 in the first coplanar line A and the ground layer 5 in the second coplanar line B are electrically connected to each other by, for example, a through-hole conductor 6 so as to have the same potential. In the ground layer around the termination,
It is desirable to form a plurality of through-hole conductors 7 at intervals less than 1 / wavelength of the wavelength λ of the transmission signal to electromagnetically surround the electromagnetic coupling portion.

【0019】また、本発明における接続構造において、
誘電体基板を構成する誘電体材料としては誘電率が15
以下のセラミックス、ガラスセラミックス、セラミック
金属複合材料、ガラス有機樹脂系複合材料等などが望ま
しく、このうち誘電率が10以下のセラミックス、ガラ
スセラミックス、セラミック金属複合材料、ガラス有機
樹脂系複合材料等が特に望ましい。
In the connection structure according to the present invention,
The dielectric material constituting the dielectric substrate has a dielectric constant of 15
The following ceramics, glass ceramics, ceramic metal composite materials, glass organic resin composite materials, and the like are desirable. Among them, ceramics, glass ceramics, ceramic metal composite materials, and glass organic resin composite materials having a dielectric constant of 10 or less are particularly preferable. desirable.

【0020】さらに、コプレーナ線路A,Bを形成する
導体としては、W、Mo等の高融点金属、金、銀、銅、
アルミニウム等の従来から用いられている種々の導体材
料によって形成することができるが、これらの中でも低
抵抗の導体である、金、銀、銅、アルミニウム等が好適
に用いられる。
Further, conductors forming the coplanar lines A and B include high melting point metals such as W and Mo, gold, silver, copper, and the like.
It can be formed of various conductor materials which have been conventionally used such as aluminum, and among them, low-resistance conductors such as gold, silver, copper, and aluminum are preferably used.

【0021】次に、上記の高周波用伝送線路の接続構造
を適用した配線基板に係る例として、半導体素子用パッ
ケージを例として説明する。図2(a)に、その構造を
説明するための断面図を、(b)に半導体素子搭載面の
導体パターン、(c)に底面の導体パターンを示した。
図2によれば、半導体素子用パッケージ10は、誘電体
基板11と蓋体12によりキャビティ13が形成されて
おり、そのキャビティ13内には、MMIC、MIC等
の半導体素子14が搭載されている。
Next, a semiconductor device package will be described as an example of a wiring board to which the above-described connection structure for high-frequency transmission lines is applied. 2A is a cross-sectional view for explaining the structure, FIG. 2B is a conductor pattern on a semiconductor element mounting surface, and FIG. 2C is a bottom conductor pattern.
According to FIG. 2, the semiconductor element package 10 has a cavity 13 formed by a dielectric substrate 11 and a lid 12, and a semiconductor element 14 such as an MMIC or MIC is mounted in the cavity 13. .

【0022】本発明によれば、上記の半導体素子用パッ
ケージのキャビティ13内の誘電体基板11の表面に
は、半導体素子に信号を伝送するための線路として、中
心導体15とグランド層16からなる第1のコプレーナ
線路Aが形成されている。そして、この第1のコプレー
ナ線路Aの一端は、半導体素子14とリボン、ワイヤ、
TAB(Tape Automated Bonding)等によって電気的に
接続されている。また、第1のコプレーナ線路Aの他端
は、キャビティ13内の誘電体基板11の表面にて終端
部15aを形成している。
According to the present invention, the center conductor 15 and the ground layer 16 are formed on the surface of the dielectric substrate 11 in the cavity 13 of the semiconductor element package as a line for transmitting a signal to the semiconductor element. A first coplanar line A is formed. One end of the first coplanar line A is connected to the semiconductor element 14 with a ribbon, a wire,
They are electrically connected by TAB (Tape Automated Bonding) or the like. The other end of the first coplanar line A forms a terminating portion 15 a on the surface of the dielectric substrate 11 in the cavity 13.

【0023】また、誘電体基板のキャビティ13外の誘
電体基板11の底面にも同様に、中心導体17とグラン
ド層18からなる第2のコプレーナ線路Bが形成されて
いる。第2のコプレーナ線路Bの一端は、パッケージの
外部電気回路基板への接続部を形成しており、他端は終
端部17aを形成し、第1のコプレーナ線路Aにおける
中心導体15の終端部15aと図1に示したような構造
にて配設することにより、第1のコプレーナ線路Aと第
2のコプレーナ線路Bとを電磁結合されている。
Similarly, a second coplanar line B including a center conductor 17 and a ground layer 18 is formed on the bottom surface of the dielectric substrate 11 outside the cavity 13 of the dielectric substrate. One end of the second coplanar line B forms a connection portion to the external electric circuit board of the package, the other end forms a terminal portion 17a, and the terminal portion 15a of the center conductor 15 in the first coplanar line A. 1 and the structure shown in FIG. 1, the first coplanar line A and the second coplanar line B are electromagnetically coupled.

【0024】その結果、半導体素子14から第1のコプ
レーナ線路Aを経由して第2のコプレーナ線路Bまでの
一連を接続できるとともに、この接続間において従来の
ようなスルーホール導体や壁体を通過することがないた
めに、伝送信号の伝送損失を低減することができる。
As a result, it is possible to connect a series from the semiconductor element 14 to the second coplanar line B via the first coplanar line A, and to pass through a conventional through-hole conductor or wall between these connections. As a result, the transmission loss of the transmission signal can be reduced.

【0025】なお、蓋体12は、キャビティからの電磁
波が外部に漏洩するのを防止できる材料から構成され、
セラミックス、セラミック金属複合材料、ガラスセラミ
ックス等が使用できる。
The lid 12 is made of a material that can prevent the electromagnetic waves from the cavity from leaking outside.
Ceramics, ceramic metal composite materials, glass ceramics and the like can be used.

【0026】また、図2の半導体素子用パッケージにお
いては、キャビティ13内には、半第1のコプレーナ線
路Aの他に、半導体素子14に電力を供給するための電
源用信号線路(図示せず)が形成され、その電源用信号
線路の他端は、スルーホール導体を通じて誘電体基板1
1の下面まで導出される。
In the semiconductor device package shown in FIG. 2, the power supply signal line (not shown) for supplying power to the semiconductor device 14 is provided in the cavity 13 in addition to the semi-first coplanar line A. ) Is formed, and the other end of the power supply signal line is connected to the dielectric substrate 1 through a through-hole conductor.
1 to the lower surface.

【0027】なお、図2において半導体素子用パッケー
ジによれば、誘電体基板11と蓋体12によるキャビテ
ィ13の形成に代えて、誘電体基板11の表面に実装さ
れた半導体素子14を封止用樹脂によって封止すること
も可能である。
In FIG. 2, according to the semiconductor device package, instead of forming the cavity 13 by the dielectric substrate 11 and the lid 12, the semiconductor device 14 mounted on the surface of the dielectric substrate 11 is sealed. It is also possible to seal with resin.

【0028】また、配線基板の一例として、第1のコプ
レーナ線路に対して半導体素子が接続された半導体素子
用パッケージを例示したが、その他、誘電体基板の表面
および裏面に半導体素子を実装し、それらを第1のコプ
レーナ線路および第2のコプレーナ線路の電磁結合によ
って接続して、モジュール化を図ることもできる。
Also, as an example of the wiring board, a semiconductor element package in which the semiconductor element is connected to the first coplanar line is illustrated. In addition, the semiconductor element is mounted on the front and back surfaces of the dielectric substrate. They can also be connected by electromagnetic coupling of the first coplanar line and the second coplanar line to achieve modularization.

【0029】また、コプレーナ線路に接続される素子と
しては半導体素子に限られることなく、光導波路、超伝
導素子、アンテナ素子などと接続することができる。
The element connected to the coplanar line is not limited to a semiconductor element, but can be connected to an optical waveguide, a superconducting element, an antenna element, or the like.

【0030】図3は、図1の高周波用伝送線路の接続構
造の特性を評価するための1手段として、半導体素子用
パッケージとしての伝送特性を評価するためのものであ
って、(a)は誘電体基板表面(半導体素子搭載面)の
パターン図、(b)は裏面のパターン図である。このパ
ターン図から示すように、表面側に2つの終端部19
a、19bを有する中心導体19と、グランド層20か
らなる第1のコプレーナ線路Aを形成し、裏面側に第1
のコプレーナ線路Aにおける中心導体19の終端部19
a、19bとそれぞれ電磁結合された中心導体21、2
1’、グランド層22を具備する2つの第2のコプレー
ナ線路B、B’を形成し、裏面側の2つの第2コプレー
ナ線路B、B’の伝送特性を評価した。
FIG. 3 shows one means for evaluating the characteristics of the connection structure of the high-frequency transmission line of FIG. 1 for evaluating the transmission characteristics of a semiconductor device package. FIG. 3B is a pattern diagram of the surface of the dielectric substrate (the surface on which the semiconductor element is mounted), and FIG. As shown in this pattern diagram, two end portions 19 are provided on the front side.
a first coplanar line A composed of a center conductor 19 having a, a and 19b and a ground layer 20;
End portion 19 of center conductor 19 in coplanar line A of FIG.
a, 19b, and the center conductors 21, 2 electromagnetically coupled to
1 ′, two second coplanar lines B and B ′ including the ground layer 22 were formed, and the transmission characteristics of the two second coplanar lines B and B ′ on the back side were evaluated.

【0031】この評価にあたっては、誘電体基板を誘電
率5.6、誘電損失30.0×10-4(測定周波数60
GHz)の誘電体材料によって形成し、中心導体および
グランド層を銅メタライズによって形成し、さらにその
表面に金メッキを施した。
In this evaluation, the dielectric substrate was made to have a dielectric constant of 5.6 and a dielectric loss of 30.0 × 10 −4 (measurement frequency 60
GHz), a center conductor and a ground layer were formed by copper metallization, and the surface thereof was plated with gold.

【0032】なお、図3における各コプレーナ線路の各
寸法は、信号線路幅aが110μm、終端部長さbが
1.0mm、線路部分の中心導体とグランド層との離間
距離xが90μm、中心導体の終端部付近のグランド層
との離間距離yが400μm、重なり部長さzが0.8
mmとした。
The dimensions of each coplanar line in FIG. 3 are as follows: the signal line width a is 110 μm, the terminal length b is 1.0 mm, the distance x between the center conductor of the line portion and the ground layer is 90 μm, The distance y from the ground layer near the terminal end is 400 μm, and the overlap length z is 0.8
mm.

【0033】また、電磁結合部周辺及び信号線路の両脇
のグランド層20、22に0.5mm間隔でスルーホー
ル導体(図示せず)を形成して、第1および第2のグラ
ンド層間を電気的に接続した。この測定用配線基板に対
して、ネットワークアナライザーによって伝送特性を測
定した。このときの結果を図4に示す。
Further, through-hole conductors (not shown) are formed at intervals of 0.5 mm in the ground layers 20 and 22 around the electromagnetic coupling portion and on both sides of the signal line, so that the first and second ground layers are electrically connected. Connected. The transmission characteristics of the wiring board for measurement were measured by a network analyzer. FIG. 4 shows the result at this time.

【0034】このとき40GHzで伝送特性はS11が
−19.5dB、S21が−0.9dBと優れた伝送特
性を示し優れたものであった。
At this time, the transmission characteristics at 40 GHz were excellent, showing excellent transmission characteristics of S1 at -19.5 dB and S21 at -0.9 dB.

【0035】次に、図5に示した従来の半導体素子用パ
ッケージに対して同様に評価を行った。この評価では、
誘電体基板として、誘電率9.8、誘電損失18.0×
10-4(測定周波数60GHz)の誘電体材料を用い、
表面および底面に形成された伝送線路間を径200μm
のタングステン導体からなるスルーホール導体で接続し
た半導体装置をネットワークアナライザーで同様に測定
し、その結果を図6に示した。図6の結果から、スルー
ホール導体にて伝送線路を接続した場合、周波数が20
GHz以上でS11:−10dB以上、S21:−30
dB以下となることから、高周波信号を半導体素子に伝
送することは不可能であることがわかった。
Next, the conventional semiconductor device package shown in FIG. 5 was similarly evaluated. In this assessment,
As a dielectric substrate, a dielectric constant of 9.8 and a dielectric loss of 18.0 ×
Using a dielectric material of 10 -4 (measuring frequency 60 GHz),
200μm diameter between transmission lines formed on the top and bottom
The semiconductor devices connected by through-hole conductors made of tungsten conductors were similarly measured by a network analyzer, and the results are shown in FIG. According to the results of FIG. 6, when the transmission line is connected by the through-hole conductor, the frequency is 20
S11: -10 dB or more, S21: -30 at GHz or more
Since it is less than dB, it was found that it was impossible to transmit a high-frequency signal to the semiconductor element.

【0036】[0036]

【発明の効果】以上詳述した通り、本発明の高周波用伝
送線路の接続構造によれば、誘電体基板の表裏に設けら
れた高周波用伝送線路を特性劣化の小さくして接続する
ことが可能となり、半導体素子用パッケージやモジュー
ル基板などの配線基板において、1GHz以上の高周波
信号を扱う配線基板における信号伝達の信頼性を高める
ことができる。
As described above in detail, according to the connection structure of a high-frequency transmission line of the present invention, it is possible to connect the high-frequency transmission lines provided on the front and back of the dielectric substrate with less characteristic deterioration. Thus, in a wiring substrate such as a semiconductor element package or a module substrate, the reliability of signal transmission in a wiring substrate that handles high-frequency signals of 1 GHz or more can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の高周波用伝送線路の接続構造を説明す
るための図であり、(a)は、その表面の導体パターン
を示す図、(b)は(a)におけるA−A断面図、
(c)は底面の導体パターンを示す図である。
1A and 1B are diagrams for explaining a connection structure of a high-frequency transmission line according to the present invention, wherein FIG. 1A is a diagram illustrating a conductor pattern on a surface thereof, and FIG. 1B is a cross-sectional view taken along line AA in FIG. ,
(C) is a diagram showing a conductor pattern on the bottom surface.

【図2】本発明の高周波用伝送線路の接続構造を用いた
配線基板の一例として半導体素子用パッケージの構造を
説明するためのもので、(a)は断面図、(b)は半導
体素子搭載面の導体パターン図、(c)は底面の導体パ
ターン図である。
FIGS. 2A and 2B are diagrams for explaining a structure of a semiconductor element package as an example of a wiring board using the connection structure of a high-frequency transmission line of the present invention, wherein FIG. 2A is a cross-sectional view, and FIG. (C) is a conductor pattern diagram on the bottom surface.

【図3】図1の高周波用伝送線路の接続構造の特性を評
価するための配線基板を説明するためのものであり、
(a)は誘電体基板表面(半導体素子搭載面)のパター
ン図、(b)は裏面のパターン図である。
3 is a diagram for explaining a wiring board for evaluating characteristics of a connection structure of the high-frequency transmission line of FIG. 1,
(A) is a pattern diagram of a dielectric substrate surface (semiconductor element mounting surface), and (b) is a pattern diagram of a back surface.

【図4】図3に基づく本発明における配線基板の伝送特
性を示す図である。
FIG. 4 is a diagram showing transmission characteristics of the wiring board according to the present invention based on FIG. 3;

【図5】(a)および(b)はいずれも従来の半導体素
子用パッケージの構造を説明するための断面図である。
5 (a) and 5 (b) are cross-sectional views for explaining the structure of a conventional semiconductor device package.

【図6】図5(b)のパッケージにおける伝送特性を示
す図である。
FIG. 6 is a diagram illustrating transmission characteristics in the package of FIG.

【符号の説明】[Explanation of symbols]

1・・・誘電体基板 2・・・第1の中心導体 2a,4a・・終端部 3・・・第1のグランド層 4・・・第2の中心導体 5・・・第2のグランド層 A・・・第1のコプレーナ線路 B・・・第2のコプレーナ線路 DESCRIPTION OF SYMBOLS 1 ... Dielectric board 2 ... 1st center conductor 2a, 4a ... Termination part 3 ... 1st ground layer 4 ... 2nd center conductor 5 ... 2nd ground layer A: first coplanar line B: second coplanar line

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】誘電体基板の一方の表面に形成され、終端
部を有する第1の中心導体と、その両側に形成された第
1のグランド層とからなる第1のコプレーナ線路と、前
記誘電体基板の他方の表面に形成され、終端部を有する
第2の中心導体と、その両側に形成された第2のグラン
ド層とからなる第2のコプレーナ線路との接続構造であ
って、前記第1のコプレーナ線路および前記第2のコプ
レーナ線路における各中心導体の終端部付近両側の前記
グランド層との離間距離を他の線路部分よりも大きくな
るように形成するとするとともに、前記第1の中心導体
と前記第2の中心導体とを平面的にみて互いの終端部が
平行且つ一部が重なるように配置して、前記第1のコプ
レーナ線路と前記第2のコプレーナ線路とを電磁結合せ
しめたことを特徴とする高周波用伝送線路の接続構造。
1. A first coplanar line formed on one surface of a dielectric substrate and having a first central conductor having a terminal portion, and first ground layers formed on both sides of the first central conductor. A connection structure for connecting a second center conductor formed on the other surface of the body substrate and having a termination portion, and a second coplanar line including second ground layers formed on both sides of the second center conductor, In the first coplanar line and the second coplanar line, the distance from the ground layer on both sides near the end of each central conductor is formed to be larger than the other line portions, and the first central conductor is formed. And the second center conductor are arranged so that their end portions are parallel and partly overlapped with each other when viewed in a plane, and the first coplanar line and the second coplanar line are electromagnetically coupled. Features Connection structure of the high frequency transmission line.
【請求項2】前記コプレーナ線路に、周波数が1GHz
以上の信号が伝送される請求項1記載の高周波用伝送線
路の接続構造。
2. The coplanar line has a frequency of 1 GHz.
The connection structure for a high-frequency transmission line according to claim 1, wherein the signal is transmitted.
【請求項3】誘電体基板と、該誘電体基板の一方の表面
に設けられた電気素子と、前記誘電体基板の一方の表面
に形成され一端が前記電気素子と電気的に接続された、
終端部を有する第1の中心導体と、その両側に形成され
た第1のグランド層とからなる第1のコプレーナ線路
と、前記誘電体基板の他方の表面に形成され、終端部を
有する第2の中心導体と、その両側に形成された第2の
グランド層とからなる第2のコプレーナ線路とを具備し
てなり、前記第1のコプレーナ線路および前記第2のコ
プレーナ線路における各中心導体の終端部付近両側の前
記グランド層との離間距離を他の線路部分よりも大きく
なるように形成するとするとともに、前記第1の中心導
体と前記第2の中心導体とを平面的にみて互いの終端部
が平行且つ一部が重なるように配置して、前記第1のコ
プレーナ線路と前記第2のコプレーナ線路とを電磁結合
せしめたことを特徴とする配線基板。
3. A dielectric substrate, an electric element provided on one surface of the dielectric substrate, and one end formed on one surface of the dielectric substrate and electrically connected to the electric element at one end.
A first coplanar line including a first center conductor having a terminal portion and first ground layers formed on both sides thereof; and a second coplanar line formed on the other surface of the dielectric substrate and having a terminal portion. , And a second coplanar line including a second ground layer formed on both sides of the center conductor, and a termination of each center conductor in the first coplanar line and the second coplanar line. The distance between the ground layer and the ground layer on both sides in the vicinity of the portion is formed so as to be larger than the other line portions, and the first center conductor and the second center conductor are mutually terminated at a planar view. Wherein the first coplanar line and the second coplanar line are electromagnetically coupled to each other so as to be parallel and partially overlapped with each other.
【請求項4】前記コプレーナ線路に、周波数が1GHz
以上の信号が伝送される請求項3記載の配線基板。
4. The coplanar line has a frequency of 1 GHz.
The wiring board according to claim 3, wherein the signal is transmitted.
JP35294797A 1997-12-22 1997-12-22 Connection structure of high-frequency transmission line and wiring board Expired - Fee Related JP3462062B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289736A (en) * 2001-03-27 2002-10-04 Kyocera Corp Package for storing high-frequency semiconductor element and its mounting structure
WO2004075336A1 (en) * 2003-02-21 2004-09-02 Matsushita Electric Industrial Co., Ltd. High frequency circuit
JP2010068405A (en) * 2008-09-12 2010-03-25 New Japan Radio Co Ltd High-frequency transmission device
US8089107B2 (en) 2006-03-14 2012-01-03 Sony Corporation Three-dimensional integrated device
JP2013165273A (en) * 2008-09-05 2013-08-22 Mitsubishi Electric Corp High frequency circuit package and sensor module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293826A (en) * 1996-04-26 1997-11-11 Kyocera Corp High frequency semiconductor device
JPH09326631A (en) * 1996-01-03 1997-12-16 Agence Spatiale Europ Microwave planar array antenna

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09326631A (en) * 1996-01-03 1997-12-16 Agence Spatiale Europ Microwave planar array antenna
JPH09293826A (en) * 1996-04-26 1997-11-11 Kyocera Corp High frequency semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289736A (en) * 2001-03-27 2002-10-04 Kyocera Corp Package for storing high-frequency semiconductor element and its mounting structure
JP4623850B2 (en) * 2001-03-27 2011-02-02 京セラ株式会社 High frequency semiconductor element storage package and its mounting structure
WO2004075336A1 (en) * 2003-02-21 2004-09-02 Matsushita Electric Industrial Co., Ltd. High frequency circuit
US8089107B2 (en) 2006-03-14 2012-01-03 Sony Corporation Three-dimensional integrated device
JP2013165273A (en) * 2008-09-05 2013-08-22 Mitsubishi Electric Corp High frequency circuit package and sensor module
JP2010068405A (en) * 2008-09-12 2010-03-25 New Japan Radio Co Ltd High-frequency transmission device

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