JP7151456B2 - Impedance compensation circuit - Google Patents

Description

The present invention relates to impedance compensation circuits.

A semiconductor integrated circuit (MMIC) used in high frequency bands such as a microwave band and a millimeter wave band is mounted on a printed circuit board (PCB) using face-down mounting and flip-chip mounting techniques.

Face-down mounting technology is used when structurally connecting a high-frequency integrated circuit and a conductor pattern provided on a printed circuit board, for example, gold (Au), copper (Cu), tin (Sn)-silver ( Ag) or the like is used for connection using metal balls of solder, thereby electrically connecting between the high frequency integrated circuit and the conductor pattern on the printed circuit board. At this connection point, discontinuity occurs in impedance, and the characteristics tend to deteriorate.

For example, the solder bumps formed on the WLCSP need to be large enough to maintain mechanical strength with the printed circuit board. ) and the pads of the integrated circuit. Since the size of the solder bumps cannot be ignored with respect to the length of the wavelength, the inductance component of the solder bumps cannot be ignored either. As a result, the signal transmission characteristics are degraded. This phenomenon appears more conspicuously as the frequency becomes higher. Therefore, it is necessary to design the circuit so as to offset the generated capacitance and inductance.

JP 2017-121032 A JP-A-7-147352 JP-A-7-74285

When a compensating circuit is provided inside the integrated circuit to compensate for the effects of parasitic elements, the compensating circuit inside the integrated circuit must be reconfigured every time the specifications of the size of the solder bumps and the shape of the electrode pads in the integrated circuit are changed. , and the integrated circuit must be revised.

It takes a lot of time and money to revise an integrated circuit. Therefore, it is necessary to avoid characteristic deterioration without revising the integrated circuit. In addition, it is also necessary to match, for example, electrode pad size, solder bump size, and underfill physical properties in the integrated circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an impedance compensation circuit capable of preventing characteristic deterioration without revising an integrated circuit and eliminating impedance mismatch without affecting physical properties in the integrated circuit.

According to the first aspect of the invention, the via is configured to open or short-circuit the tip of the interlayer connection to the inner layer of the substrate to the ground. The substrate is a structure with multiple layers including a top surface and a ground plane on an inner layer of the multiple layers.

According to the first aspect of the invention, the via is constructed using a three-dimensional structure in which a plurality of layers are connected from the surface layer surface of the substrate to the inner layer. The wiring length can be freely changed by adjusting the number of inner layers forming vias. Impedance matching can be achieved by opening or shorting the tip of the via that faces the ground plane of the inner layer of the substrate to the ground plane, and by using the via as a compensating circuit with a total line length of less than λ/4 .

As a result, a matching element that can be freely adjusted outside the integrated circuit can be realized, and characteristic deterioration can be prevented without revising the integrated circuit. By providing a compensation circuit, the impedance mismatch can be resolved without affecting other physical properties within the integrated circuit. Since the inner layer of the substrate is used for three-dimensional connection, the size of the circuit configuration on the substrate can be reduced.

Sectional drawing which shows the mounting structure which concerns on 1st Embodiment A perspective view showing the structure of an impedance compensation circuit Compensation circuit schematic Block diagram schematically representing FIG. A perspective view showing the structure of an impedance compensation circuit Compensation circuit schematic Block diagram schematically representing FIG. A plan view showing a mounting structure according to the second embodiment. A perspective view showing the structure of an impedance compensation circuit A plan view showing another mounting structure

Several embodiments of the impedance compensation circuit will be described below with reference to the drawings. In each of the embodiments described below, the same or similar reference numerals are given to components that perform the same or similar operations, and description thereof will be omitted as necessary.

(First embodiment)
As shown in FIG. 1, a high frequency integrated circuit 2 is mounted on a substrate 1 by MMIC (Monolithic Microwave Integrated Circuit). The high-frequency integrated circuit 2 is packaged by a WLCSP (Wafer level Chip Size Package) and used for automotive radar applications, for example. The high-frequency integrated circuit 2 includes a transmitter for generating a millimeter-wave band signal modulated by a system such as FMCW (Frequency Modulated Continuous Wave) and outputting it to a transmission line 3 formed on the substrate 1 .

The substrate 1 is made of, for example, a resin substrate. The substrate 1 is a multi-layer build-up substrate configured by repeating lamination, drilling, wiring formation, and the like for each layer. The substrate 1 comprises a plurality of layers L1-L6 of conductive plates, with dielectric layers sandwiched between these layers L1-L6. Layer L1 corresponds to the surface layer.

The middle layer L4 inside the substrate 1 is configured as a large area, low impedance ground. The substrate 1 is configured by laminating a laminated structure of upper layers L1 to L4 and a laminated structure of lower layers L5 to L6 with a layer L4 as a boundary. A pattern is formed on each layer L1 to L6, and the pattern is electrically connected by vias V1, V2, etc. to form a circuit. In FIG. 1, only pattern 4 of layer L1 is labeled. Since the substrate 1 is constructed using a build-up substrate, the hole diameters of the vias V1 and V2 and the wiring length of the inner layer pattern can be freely changed.

A pattern 4 on layer L1 is electrically connected to an antenna load 5 . The pattern 4 constitutes a transmission line 3 for mainly transmitting high frequency signals.

A terminal 6 of a bare chip is exposed on the upper surface of the high frequency integrated circuit 2 (corresponding to the negative direction of the Z direction in FIG. 1). When the high-frequency integrated circuit 2 is mounted on the layer L1 on the surface of the substrate 1, the upper surface of the bare chip is reversed and mounted face down on the surface of the layer L1 of the substrate 1. FIG. In face-down mounting, gold (Au), copper (Cu), solder (tin (Sn)-silver ( Ag)) or the like is used for bonding.

As shown in FIG. 2, inside the high-frequency integrated circuit 2, signal wiring 8 made of aluminum wiring is extended in the X direction. The ground wirings 9 are spaced apart on both sides of the signal wirings 8 in the Y direction. The ground wiring 9 is wider than the signal wiring 8 . The ground wiring 9 is also made of aluminum wiring. The signal wiring 8 and the ground wiring 9 are connected to the terminals 6 respectively. Terminal 6 is joined to layer L1 of substrate 1 by metal ball 7 .

When the terminal 6 is joined to the layer L1 of the substrate 1 by the metal ball 7, an impedance mismatch occurs due to the influence of the parasitic capacitance C (see FIG. 1) inside the high frequency integrated circuit 2 and the inductance of the metal ball 7. FIG. Compensation circuit 10 is provided to compensate for the effects of this impedance mismatch.

As shown in FIGS. 1 and 2, the compensating circuit 10 has a three-dimensional structure with vias V1 and V2 from the pattern 4 of the transmission line 3 between the layers L1 to L3 of the substrate 1. FIG. The compensating circuit 10 is configured to extend directly below the electrode pads formed on the layer L<b>1 of the substrate 1 to achieve impedance matching.

As shown in FIG. 2, patterns 4, 4a, and 4b are formed on the layer L1. The pattern 4 is a pattern for mainly transmitting a signal output to the outside through the signal wiring 8 inside the high frequency integrated circuit 2, and extends in the X direction. The patterns 4a and 4b are patterns arranged to be spaced apart on both sides of the pattern 4 in the Y direction and extending in the X direction.

The patterns 4a and 4b are connected to the ground terminals 6a and 6b of the high frequency integrated circuit 2 by metal balls 7. As shown in FIG. Vias Va and Vb are arranged on the substrate 1 at certain intervals in the X direction.

The via Va is configured to provide a through connection between the pattern 4a of the layer L1 and the ground plane of the layer L4. The via Vb is configured to provide a through connection between the pattern 4b of layer L1 and the ground plane of layer L4.

On the other hand, the vias V1 and V2 are arranged at a location G2 in the pattern 4 separated from the joint G1 between the pattern 4 and the metal ball 7 by a predetermined distance La in the X direction. As shown in FIG. 1, via V1 connects between layers L1 and L2, and via V2 connects between layers L2 and L3.

One of the many vias Va is arranged on the positive side in the Y direction away from the arrangement location G2 of the vias V1 and V2. One of the large number of vias Vb is arranged away from the location G2 of the vias V1 and V2 on the negative side in the Y direction. In FIG. 2, these target vias Va and Vb are indicated as vias Vaa and Vbb, respectively. A bridging wiring 12 is formed between the via Vaa and the via Vbb in the layer L3. The bridging wiring 12 is a high-impedance wiring that is narrow in the X direction in the drawing.

The pattern 4a is connected to the vias V1 to V2 via a point G2 separated from the junction G1 by a predetermined distance La in the X direction, and is further connected to the vias Vaa and Vbb through the bridging wiring 12. FIG. Also, vias Vaa and Vbb are shorted to the ground plane of layer L4. This constitutes a short stub Ss.

As shown in FIG. 3, the high frequency integrated circuit 2 has a power amplifier 2a at the end of its transmitter. The output of the power amplifier 2a is applied to the feeding point 5a of the antenna load 5 through the transmission line 3. FIG.

When the component of the parasitic capacitance C parasitic inside the high-frequency integrated circuit 2 of FIG. is preferably configured to be shorted to the ground plane of layer L4. At this time, the total line length L of via V1 and via V2 is set to less than λ/4.
This corresponds to short-circuiting the inductive reactance element 20 to the ground in the middle of the transmission line 3, as shown in FIG. By arranging the compensating circuit 10 as close to the joint G1 of the metal ball 7 as possible, the impedance can be compensated in a wide frequency band.

According to the present embodiment, by configuring the compensation circuit 10 with a three-dimensional structure between the power amplifier 2a and the feeding point 5a of the antenna load 5, it is possible to suppress the feeding loss and utilize the antenna gain without waste. can.

On the other hand, if the inductance caused by the metal balls 7 of the high-frequency integrated circuit 2 becomes dominant, the vias V1 to V2 connected to the inner layers L1 to L3 of the substrate 1, as shown in the compensating circuit 110 of FIG. It is preferable to configure the open stub So with the tip in an open state. At this time, the total line length L of via V1 and via V2 is set to less than λ/4. This corresponds to connecting a capacitive reactance element 21 in the middle of the transmission line 3 as shown in FIG. 6, and to constructing an open stub So as shown in FIG.

The structure of the open stub So shown in FIG. 5 is the structure of the short stub Ss shown in FIG. 2 with the bridging wiring 12 removed. Therefore, the lower end of the via V2 is not connected to the bridging wiring 12 and is in an open state on the layer L3. By configuring the compensation circuit 110 in this manner, the influence of parasitic elements that cause characteristic deterioration can be canceled out.

The inventor measured return loss characteristics and insertion loss characteristics from the joint G1 of the high frequency integrated circuit 2 to the antenna load 5 in order to confirm the effect of the compensation circuit 10 with the short stub Ss. The inventors have confirmed by computer simulation that the return loss can be reduced to about -30 dBm and the insertion loss characteristic can be improved by about 1.8 dB in the 80 GHz transmission/reception frequency band of the millimeter wave band radar.

According to this embodiment, impedance matching is achieved by constructing the compensation circuits 10 and 110 in the inner layer of the substrate 1, so that the shape of the terminal 6 and the size of the metal ball 7 of the high frequency integrated circuit 2 are not affected. A high frequency integrated circuit 2 can be designed.

In addition, since the impedance around the terminal 6 is determined by the chip size of the high frequency integrated circuit 2, the size of the metal balls 7, the pitch between the terminals of the high frequency integrated circuit 2, the material of the underfill, etc., the compensating circuits 10 and 110 It does not change even if the internal circuit of the integrated circuit 2 is changed. Furthermore, even if the shape and material of the high-frequency integrated circuit 2 are changed, there is no need to change the design, and development costs can be reduced.

In general, compensation circuits are often constructed on layer L1 of substrate 1 . As a result, a large circuit layout space is occupied on the substrate 1, which is not preferable.
In this embodiment, the vias V1 and V2 are formed inside the substrate 1, and the compensating circuits 10 and 110 are formed using the three-dimensional structure of the vias V1 and V2 and the pattern 4, so that miniaturization can be achieved. can be planned. As a result, the compensating circuits 10 and 110 that are compact and have good performance can be realized while effectively using the circuit layout space on the layer L1 for other purposes.
In addition, since the wiring length can be freely changed by adjusting the number of inner layers forming the vias V1 and V2, an adjustable matching element can be realized. Therefore, characteristic deterioration can be suppressed without revising the high-frequency integrated circuit 2 . It can be adapted to the pad size, bump size, and underfill physical properties of the high frequency integrated circuit 2 .

(Second embodiment)
Many radio frequency integrated circuits 2 tend to include multi-channel transmitters and receivers. The high-frequency integrated circuit 2 shown in FIG. 8 incorporates transmitters for a plurality of channels CH1 to CH5, and is capable of transmitting and outputting only for the plurality of channels CH1 to CH5. Transmission output terminals of channels CH1 to CH5 are connected to transmission lines 3 through metal balls 7, respectively. When configuring the compensation circuit 110 by the open stub So for each of the channels CH1 to CH5, as shown in FIG. good to do

As shown in the perspective view of FIG. 9, the compensating circuits 110 have the same structure among the channels CH1 to CH3. Thereby, impedance matching can be performed in the same state among the plurality of channels CH1 to CH3.

As shown in FIG. 10, when combining and outputting signals of a plurality of channels CH1 to CH3, it is desirable to configure a compensation circuit 110 in each transmission path of the transmission line 3 of each channel CH1 to CH3. As shown in FIG. 10, a compensation circuit 110 may be provided in the transmission line 3 of each of the channels CH1 to CH3 on the high frequency integrated circuit 2 side of the synthesis point P1. Also, the compensating circuit 110 may be provided on the antenna load 5 side of the combining point P1.

Further, when distributing the signal power from the terminal 6 of each channel CH4 to CH5 to a plurality of transmission lines 3, it is desirable to provide a compensating circuit 110 in the middle of the signal transmission line 3. FIG. At this time, as shown in FIG. 10, it is preferable to provide a compensation circuit 110 on the high frequency integrated circuit 2 side of the signal distribution branch point P2. Compensation circuits 110 may be provided on the antenna load 5 side from the signal distribution branch point P2. You may provide in these both. The compensating circuit 110 can evenly distribute the signal power from the transmission line 3 of each channel CH4 to CH5.

In general, the compensation circuit is often constructed on the layer L1 of the substrate 1. FIG. In particular, when a high-frequency integrated circuit 2 corresponding to multiple channels is provided on the substrate 1 and a large number of compensation circuits are configured for each channel, it is necessary to physically separate the adjacent terminals of the channels of the high-frequency integrated circuit 2. tends to grow. This is critical for the multi-channel high-frequency integrated circuit 2 and often lacks realization.

In this embodiment, compensation circuits 110 are provided for all channels CH1 to CH5. Since the compensating circuits 110 for all of these channels CH1 to CH3 and CH4 to CH5 are configured with the same structure, miniaturization can be achieved.
Although the form using the compensation circuit 110 with the open stub So is shown in this embodiment, the compensation circuit 10 with the short stub Ss may be used.

(Other embodiments)
The present disclosure is not limited to the embodiments described above, and can be implemented in various modifications, and can be applied to various embodiments without departing from the scope of the present disclosure. For example, the following modifications or extensions are possible.

Although the board|substrate 1 demonstrated the form using the resin board, it is not restricted to this and a ceramic board may be used. The transmission line 3 may be applied to the transmission output or reception input of a high frequency signal, and the antenna load 5 is not limited to a transmission antenna and may be a reception antenna.

Although the high-frequency integrated circuit 2 is applied to a semiconductor integrated circuit (MMIC) of a millimeter-wave radar system for vehicles, it is not limited to this. Not only a monolithic IC but also an HIC (Hybrid Integrated Circuit) may be used. Any integrated circuit used in the radio frequency band can be applied.

The configurations and functions of the multiple embodiments described above may be combined. A mode in which part of the above embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, all conceivable aspects can be regarded as embodiments as long as they do not deviate from the essence of the invention specified by the language in the claims.

Although the present disclosure has been described in accordance with the embodiments described above, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of this disclosure.

In the drawings, 1 is a substrate, 2 is a high frequency integrated circuit (integrated circuit), 3 is a transmission line, 5 is an antenna load, 7 is a metal ball, 10 and 110 are compensation circuits, 20 is an inductive reactance element, and 21 is a capacitive. Reactance elements, L1 to L6 denote layers, and V1 and V2 denote vias.

Claims (3)

Compensation circuit (10, 110),
The substrate has a structure with a plurality of layers including a surface layer surface, and a ground plane is provided in an inner layer (L4) of the plurality of layers,
The compensation circuit is
Constructed using a three-dimensional structure having vias (V1, V2) for interlayer connection from the surface layer of the substrate that mainly transmits the high frequency signal to the inner layer of the substrate,
The via is configured to open or short-circuit a tip toward the ground plane of the inner layer of the substrate to the ground plane ,
An impedance compensation circuit in which the total line length of the vias is less than λ/4 . The transmission line (3) is configured with only a plurality of channels (CH1 to CH5) for transmission output or reception input of the high frequency signal,
2. The impedance compensating circuit according to claim 1, wherein said compensating circuit comprises said vias having the same structure among a plurality of channels. The substrate is constructed by repeating lamination, drilling, wiring formation, etc. for each layer, and the plurality of layers are electrically connected by vias (V1, V2, Va, Vb, Vaa, Vbb). It is composed of a build-up board that is composed of a circuit by
3. The impedance compensation circuit according to claim 1, wherein said build-up board is formed by pasting together a laminate structure of upper layers and a laminate structure of lower layers with the middle layer (L4) as a boundary.

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