WO2010130293A1 - A transition from a chip to a waveguide - Google Patents

A transition from a chip to a waveguide Download PDF

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Publication number
WO2010130293A1
WO2010130293A1 PCT/EP2009/055911 EP2009055911W WO2010130293A1 WO 2010130293 A1 WO2010130293 A1 WO 2010130293A1 EP 2009055911 W EP2009055911 W EP 2009055911W WO 2010130293 A1 WO2010130293 A1 WO 2010130293A1
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WO
WIPO (PCT)
Prior art keywords
main side
chip
planar structure
top layer
bottom layer
Prior art date
Application number
PCT/EP2009/055911
Other languages
French (fr)
Inventor
Per Ligander
Original Assignee
Telefonaktiebolaget L M Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget L M Ericsson (Publ) filed Critical Telefonaktiebolaget L M Ericsson (Publ)
Priority to PCT/EP2009/055911 priority Critical patent/WO2010130293A1/en
Publication of WO2010130293A1 publication Critical patent/WO2010130293A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/08—Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H01P5/10—Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
    • H01P5/107—Hollow-waveguide/strip-line transitions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Definitions

  • the present invention relates to a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality.
  • the planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side.
  • the present invention also relates to a transition comprising a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality.
  • the planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side.
  • a microstrip transmission line comprises a metal ground plane and a conductor, where a dielectric carrier material is positioned between the metal ground plane and the conductor. This configuration is economical and relatively easy to design.
  • the filter may have to be realized in waveguide technology. Waveguides are normally filled with air or other low-loss materials. When there is a filter in a microwave circuit microstrip layout, the filter may thus be realized by means of a waveguide filter in order to lower the losses.
  • a signal that is carried by a microstrip transmission line is intended to be radiated by a radiating element, such as for example an antenna.
  • microstrip transmission line is transformed to a waveguide interface, for example when a diplexer or a triplexer is used.
  • the microstrip signal is often first fed through an integrated circuit, normally comprising a so-called chip, before being fed to a waveguide.
  • the chip is based on GaAs and comprises an LNA (Low Noise Amplifier), or some other circuitry having a desired electrical functionality.
  • LNA Low Noise Amplifier
  • a typical such chip comprises a number of input leads, output leads, ground leads, control leads and bias leads.
  • the most common way is to connect the chip's pads to a conductor dielectric carrier material, for example in the form of a PCB (Printed Circuit Board) made from any suitable kind of laminate material, where the PCB conductor is connected to a probe.
  • the probe is arranged in such a way that it feeds a waveguide and/or an antenna, where the waveguide may be in the form of a surface-mounted waveguide.
  • Such a surface-mounted waveguide is normally made having three walls and one open side. Metal ization is then provided on the side of the dielectric carrier material facing the waveguide, where the metalization serves as the remaining wall of the waveguide, thus closing the waveguide structure when the waveguide is fitted to the dielectric carrier material.
  • planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality.
  • the planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side.
  • One port of said ports is electrically connected to a radiating element positioned on the first chip main side.
  • the radiating element is arranged for transferring a signal between a surface-mountable waveguide part and said one port when the surface-mountable waveguide part is mounted on the dielectric carrier material such that it covers the radiating element.
  • a transition arrangement comprising a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality.
  • the planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side. One port of said ports is electrically connected to a radiating element positioned on the first chip main side.
  • the radiating element is arranged for transferring a signal between a surface-mountable waveguide part and said one port when the surface-mountable waveguide part is mounted on the dielectric carrier material such that it covers the radiating element.
  • the planar structure is mounted in a cavity in the dielectric carrier material such that the first chip main side and the first main side of the dielectric carrier material essentially lie in the same plane.
  • those ports of said ports that are separate from said one port are arranged to be connected to corresponding connection pads by means of bond wires.
  • the dielectric carrier material is in the form of a multilayer structure, comprising a top layer and a bottom layer, where the top layer comprises a first top layer side and a second top layer side, where the first top layer side is constituted by the first main side, and where the bottom layer comprises a first bottom layer side and a second bottom layer side, where the second bottom layer side is constituted by the second main side.
  • the second top layer side comprises a first metalization
  • that the first bottom layer side comprises a second metalization
  • the top layer is made in a first material
  • the bottom layer is made in a second material
  • the top layer and the bottom layer are mounted to each other by means of an adhesive compound, positioned between the first metalization and the second metalization. Then, the cavity is formed in the top layer such that the planar structure is mounted to the first metalization.
  • Figure 1 shows a top view of a chip mounted to a dielectric carrier material, the chip being partly covered by a waveguide part;
  • Figure 2 shows a sectional view of a chip mounted to a dielectric carrier material, the chip being partly covered by a waveguide part.
  • Figure 1 and Figure 2 show a top view a sectional view of a chip 1 which has a first chip main side 2 and a second chip main side 3, where the first chip main side 2 comprises a first input port 4, a second input port 5 and a third input port 6, the input ports 4, 5, 6 being arranged to receive input signals and bias voltage.
  • the first chip main side 2 also comprises a ground port 7, a first control signal port 8 and second control signal port 9, and a first output port 10 and a second output port 11 , the output ports being arranged to deliver output signals.
  • the first chip main side 2 also comprises at least one electrical functionality F which in this example is a low noise amplifier (LNA).
  • the ports are formed as metal pads.
  • LNA low noise amplifier
  • the chip is mounted on a dielectric carrier material 12 having a first main side 13 and a second main side 14.
  • the first main side 13 comprises a first input connection pad 15, a second input connection pad 16 and a third input connection pad 17, the input connection pads 15, 16, 17 being connected to corresponding input ports 4, 5, 6.
  • the first main side 13 also comprises a ground pad 18, a first control signal pad 19 and a second control signal pad 20, which are connected to corresponding ground port 7 and control signal ports 8, 9, respectively.
  • the first main side 13 comprises an output pad 21 which is connected to the corresponding second output port 11.
  • the pads mentioned are connected to the corresponding ports by means of bond wires 23. For the sake of clarity of the figure, only one bond wire has been designated with a reference number.
  • One of the output ports is intended to be connected to a waveguide.
  • the first output port 10 is electrically connected to a radiating element 22 positioned on the first chip main side 2.
  • the radiating element 22 is arranged for radiating an output signal into a surface-mountable waveguide 24, when the surface-mountable waveguide 24 is mounted on the dielectric carrier material 12 such that it covers the radiating element 22.
  • the surface-mountable waveguide 24 is a part that is in the form of a lid, covering the radiating element 22 in such a way that there is a matched transition from the radiating element 22 to the surface-mountable waveguide 24.
  • the surface-mountable waveguide 24 is of a previously known type, being attached in a known way; for example by means of soldering flanges 24a, 24b.
  • the surface-mountable waveguide 24, in the following referred to as "waveguide”, comprises a first wall 25, a second wall 26, a third wall 27, a
  • the 90° bend part 28 is arranged to direct a microwave signal from the radiating element 22, having an electromagnetic field vector E that is essentially parallel to the first main side
  • a waveguide metalization 30 is provided on the first main side 13 which is arranged to be facing the waveguide 24 and at least correspond to the open side 29 such that the waveguide metalization 30 serves as the remaining wall of the waveguide, thus closing the waveguide structure, when the waveguide is fitted to the dielectric carrier material 12.
  • the output signal that is intended to be fed into the waveguide 24 is thus fed from the first output port 10 which in turn is electrically connected to the radiating element 22. In this way, an output signal may be transferred from the first output port 10 to the waveguide 24.
  • the first output port 10 does not have to be a pad to which a radiating element 22 is fastened, instead the radiating element 22 and the first output port 10 may be formed from the same part, where the first output port 10 extends in such a way that it transits into a radiating element. In this way, no separate radiating element part will have to be manufactured and attached to the chip 1. Irrespective of if the first output port 10 and the radiating element 22 are different parts or are formed from the same part, they are electrically connected to each other.
  • the dielectric carrier material may be formed in a number of different ways.
  • the dielectric carrier material 12 is in the form of a multilayer structure, comprising a top layer 31 and a bottom layer 32.
  • the top layer 31 comprises a first top layer side and a second top layer side 33, where the first top layer side is constituted by the first main side 13.
  • the bottom layer 32 comprises a first bottom layer side 34 and a second bottom layer side, where the second bottom layer side is constituted by the second main side 14.
  • the second top layer side 33 comprises a first metalization 35
  • the first bottom layer side 34 comprises a second metalization 36.
  • the top layer 31 is made in a first material
  • the bottom layer 32 is made in a second material, the top layer 31 and the bottom layer 32 being mounted to each other by means of an adhesive compound 37, positioned between the first metalization 35 and the second metalization 36.
  • the adhesive compound 37 is for example in the form of a special epoxy film, known as prepreg.
  • the bottom layer 32 is comprised by re-inforced glass fibre, known as FR4, and the top layer 31 is comprised by a PTFE (polytetrafluoroethylene) laminate.
  • the second chip main side 3 comprises a chip metalization 39, where the chip metalization 39 is fastened to the first metalization 35 by means of soldering or similar.
  • the metalizations 30, 35, 36 described are made by relatively thin metal films, having a thickness of for example 17 ⁇ m or 35 ⁇ m, and being made in for example copper or gold, where the copper may be plated by a desired metal.
  • the chip metallization may be of the magnitude 3 ⁇ m.
  • the first chip main side 2 there is a metalization forming a frame 40 around the radiating element 22 when it enters the waveguide 24, except for a probe transition 41.
  • the frame 40 comprises a number of via holes, for reasons of clarity only one is shown with a reference number 42, but of course all the vias shown are of the same kind.
  • the vias 42 are electrically connecting the frame 40 to the chip metalization 39 such that a virtual electrically conducting wall is obtained along the height of the chip 1.
  • the dielectric carrier material 12 may be made having one dielectric material layer only, where the side of the dielectric material layer that faces away from the waveguide 24 is attached to a rigid metal layer, known as hardback (not shown). In this case, a cavity is formed in the dielectric material layer such that the chip 1 is mounted to the rigid metal layer.
  • the rigid metal layer may for example be made in copper or brass, and may be gold-plated.
  • the use of a bond wire for an output signal at relatively high frequencies, such as 60-90 GHz, may be avoided.
  • a direct connection from an output port on the chip to a radiating element is used, the radiating element being used for signal transfer to a waveguide.
  • the first output port 10 which in this example has been arranged for outputting a signal, instead could be an input port arranged for receiving an input signal that is fed from the waveguide 24.
  • the radiating element 22 is connected to an input port instead, and transfers an input signal from the waveguide to the input port.
  • the present invention is not limited to the examples described above, but may vary freely within the scope of the appended claims.
  • the present invention may be used with any suitable planar structure that forms a chip, having at least one electrical function.
  • the radiating element 22 is fastened to the first output port 10
  • this may be done in many ways, for example by means of soldering or thermal compression.
  • the chip may be made in many suitable materials such as GaAs (Gallium- Arsenide), SiGe (Silicon-Germanium) and CMOS (Complementary metal- oxide-semiconductor).
  • the chip may be in the form of an MMIC (Monolithic Microwave Integrated Circuit).
  • MMIC Monitoring Microwave Integrated Circuit
  • the chip does not have to be mounted in a cavity, but may for example be mounted on the first top layer side/first main side 13 of the dielectric carrier material 12.
  • the dielectric materials may comprise several layers if necessary, the layers comprising different types of circuitry and/or metalizations. Such a layered structure may also be necessary for mechanical reasons.
  • the dielectric carrier material 12 and its layer or layers may be made in one or several materials including re-inforced glass fibre, known as FR4, re-inforced PTFE (polytetrafluoroethylene) and ceramic compounds.
  • the number of ports on the chip and corresponding connection pads on the dielectric carrier material 12 may of course vary depending on the types used; also the number of used ports and pads and which ports and pads that are used varies in the same way.
  • the metal material may be any suitable conductor such as copper or gold.
  • the radiating element has been shown to have a T-shape, this is only an example of a shape.
  • a radiating element used in the present invention may have any suitable shape as for example straight, chamfered, tapered and with varying widths continuously and/or is steps.
  • the frame 40 is shown comprising a single row of via holes 42. In order to further increase leakage suppression, more than one row of via holes may be used, the frame 40 then comprising at least two adjacent rows of via holes around its circumference.
  • the waveguide part 24 may be made in a non-conducting material, such as plastic, which is covered by a thin layer of metalization.
  • the 90° bend part 28 is showed comprising an inclined, continuous wall part 43, presenting an angle.
  • An example of another shape of the 90° bend part 28 is a stepped structure, having a plurality of steps.
  • the shapes described are commonly known for waveguide bends in general, and are designed to provide a matched transition from a microsthp element, such as the radiating element, to a waveguide.
  • the prepreg used may be any sort of suitable adhesive compound.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Waveguides (AREA)

Abstract

The present invention relates to a planar structure in the form of chip (1), the planar structure (1) having a first chip main side (2) and a second chip main side (3), where the first chip main side (2) comprises at least one input port (4, 5, 6), arranged to receive an input signal, at least one output port (10, 11), arranged to output an output signal, and at least one electrical functionality (F). The planar structure (1) is arranged for mounting on a dielectric carrier material (12) having a first main side (13) and a second main side (14). One port (10) of said ports (4, 5, 6, 10, 11) is electrically connected to a radiating element (22) positioned on the first chip main side (2), the radiating element (22) being arranged for transferring a signal between a surface-mountable waveguide part (24) and said one port (10) when the surface-mountable waveguide part (24) is mounted on the dielectric carrier material (12) such that it covers the radiating element (22).

Description

TITLE
A transition from a chip to a waveguide
TECHNICAL FIELD The present invention relates to a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality. The planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side.
The present invention also relates to a transition comprising a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality. The planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side.
BACKGROUND
When designing microwave circuits, microsthp transmission lines are commonly used. A microstrip transmission line comprises a metal ground plane and a conductor, where a dielectric carrier material is positioned between the metal ground plane and the conductor. This configuration is economical and relatively easy to design.
However, due to losses in the dielectric carrier material, it is sometimes not possible to use microstrip transmission lines. When there for example is a filter in the layout, the filter may have to be realized in waveguide technology. Waveguides are normally filled with air or other low-loss materials. When there is a filter in a microwave circuit microstrip layout, the filter may thus be realized by means of a waveguide filter in order to lower the losses.
There is also a possibility that a signal that is carried by a microstrip transmission line is intended to be radiated by a radiating element, such as for example an antenna.
There are also a number of other circumstances where a microstrip transmission line is transformed to a waveguide interface, for example when a diplexer or a triplexer is used.
In these cases, the microstrip signal is often first fed through an integrated circuit, normally comprising a so-called chip, before being fed to a waveguide. For example, the chip is based on GaAs and comprises an LNA (Low Noise Amplifier), or some other circuitry having a desired electrical functionality. A typical such chip comprises a number of input leads, output leads, ground leads, control leads and bias leads.
There is thus a desire to obtain a transition from such a chip to a waveguide. The most common way is to connect the chip's pads to a conductor dielectric carrier material, for example in the form of a PCB (Printed Circuit Board) made from any suitable kind of laminate material, where the PCB conductor is connected to a probe. The probe is arranged in such a way that it feeds a waveguide and/or an antenna, where the waveguide may be in the form of a surface-mounted waveguide.
Such a surface-mounted waveguide is normally made having three walls and one open side. Metal ization is then provided on the side of the dielectric carrier material facing the waveguide, where the metalization serves as the remaining wall of the waveguide, thus closing the waveguide structure when the waveguide is fitted to the dielectric carrier material.
However, when the frequencies used lie around 60-90 GHz, the losses will be too high, resulting in that a satisfactory result is not possible to achieve. This is due to the fact that the connections from the chip itself to the PCB conductors normally are wire-bonded with a bond wire. Such a wire-bonding constitutes a large inductance, and induces heavy losses at 60-90 GHz.
There is thus a desire for a transition from a microwave chip to a waveguide, where the losses are minimized.
SUMMARY
It is an object of the present invention to provide a transition from a microwave chip to a waveguide interface, where the losses are minimized.
This object is achieved by means of a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality. The planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side.
One port of said ports is electrically connected to a radiating element positioned on the first chip main side. The radiating element is arranged for transferring a signal between a surface-mountable waveguide part and said one port when the surface-mountable waveguide part is mounted on the dielectric carrier material such that it covers the radiating element.
This object is also achieved by means of a transition arrangement comprising a planar structure in the form of chip, the planar structure having a first chip main side and a second chip main side, where the first chip main side comprises at least one input port, arranged to receive an input signal, at least one output port, arranged to output an output signal, and at least one electrical functionality. The planar structure is arranged for mounting on a dielectric carrier material having a first main side and a second main side. One port of said ports is electrically connected to a radiating element positioned on the first chip main side. The radiating element is arranged for transferring a signal between a surface-mountable waveguide part and said one port when the surface-mountable waveguide part is mounted on the dielectric carrier material such that it covers the radiating element.
According to an embodiment example, the planar structure is mounted in a cavity in the dielectric carrier material such that the first chip main side and the first main side of the dielectric carrier material essentially lie in the same plane.
According to another embodiment example, those ports of said ports that are separate from said one port are arranged to be connected to corresponding connection pads by means of bond wires.
According to another embodiment example, the dielectric carrier material is in the form of a multilayer structure, comprising a top layer and a bottom layer, where the top layer comprises a first top layer side and a second top layer side, where the first top layer side is constituted by the first main side, and where the bottom layer comprises a first bottom layer side and a second bottom layer side, where the second bottom layer side is constituted by the second main side.
Preferably, the second top layer side comprises a first metalization, and that the first bottom layer side comprises a second metalization. For example, the top layer is made in a first material, and the bottom layer is made in a second material, the top layer and the bottom layer are mounted to each other by means of an adhesive compound, positioned between the first metalization and the second metalization. Then, the cavity is formed in the top layer such that the planar structure is mounted to the first metalization.
Other embodiment examples are evident from the dependent claims. A number of advantages is provided by means of the present invention, for example the following is achieved:
- a robust low loss transition from a microwave chip to a waveguide interface; and - possible assembly in a pick&place process.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be described more in detail with reference to the appended drawings, where:
Figure 1 shows a top view of a chip mounted to a dielectric carrier material, the chip being partly covered by a waveguide part; and
Figure 2 shows a sectional view of a chip mounted to a dielectric carrier material, the chip being partly covered by a waveguide part.
DETAILED DESCRIPTION
Figure 1 and Figure 2 show a top view a sectional view of a chip 1 which has a first chip main side 2 and a second chip main side 3, where the first chip main side 2 comprises a first input port 4, a second input port 5 and a third input port 6, the input ports 4, 5, 6 being arranged to receive input signals and bias voltage. The first chip main side 2 also comprises a ground port 7, a first control signal port 8 and second control signal port 9, and a first output port 10 and a second output port 11 , the output ports being arranged to deliver output signals. The first chip main side 2 also comprises at least one electrical functionality F which in this example is a low noise amplifier (LNA). The ports are formed as metal pads.
The chip is mounted on a dielectric carrier material 12 having a first main side 13 and a second main side 14. The first main side 13 comprises a first input connection pad 15, a second input connection pad 16 and a third input connection pad 17, the input connection pads 15, 16, 17 being connected to corresponding input ports 4, 5, 6. The first main side 13 also comprises a ground pad 18, a first control signal pad 19 and a second control signal pad 20, which are connected to corresponding ground port 7 and control signal ports 8, 9, respectively. Furthermore, the first main side 13 comprises an output pad 21 which is connected to the corresponding second output port 11. The pads mentioned are connected to the corresponding ports by means of bond wires 23. For the sake of clarity of the figure, only one bond wire has been designated with a reference number.
One of the output ports is intended to be connected to a waveguide.
According to the present invention, the first output port 10 is electrically connected to a radiating element 22 positioned on the first chip main side 2. The radiating element 22 is arranged for radiating an output signal into a surface-mountable waveguide 24, when the surface-mountable waveguide 24 is mounted on the dielectric carrier material 12 such that it covers the radiating element 22.
The surface-mountable waveguide 24 is a part that is in the form of a lid, covering the radiating element 22 in such a way that there is a matched transition from the radiating element 22 to the surface-mountable waveguide 24. The surface-mountable waveguide 24 is of a previously known type, being attached in a known way; for example by means of soldering flanges 24a, 24b.
The surface-mountable waveguide 24, in the following referred to as "waveguide", comprises a first wall 25, a second wall 26, a third wall 27, a
90° bend part 28 and one open side 29. The 90° bend part 28 is arranged to direct a microwave signal from the radiating element 22, having an electromagnetic field vector E that is essentially parallel to the first main side
13, into the waveguide such that the electromagnetic field vector E gradually becomes essentially perpendicular to the first main side 13. A waveguide metalization 30 is provided on the first main side 13 which is arranged to be facing the waveguide 24 and at least correspond to the open side 29 such that the waveguide metalization 30 serves as the remaining wall of the waveguide, thus closing the waveguide structure, when the waveguide is fitted to the dielectric carrier material 12.
The output signal that is intended to be fed into the waveguide 24 is thus fed from the first output port 10 which in turn is electrically connected to the radiating element 22. In this way, an output signal may be transferred from the first output port 10 to the waveguide 24.
The first output port 10 does not have to be a pad to which a radiating element 22 is fastened, instead the radiating element 22 and the first output port 10 may be formed from the same part, where the first output port 10 extends in such a way that it transits into a radiating element. In this way, no separate radiating element part will have to be manufactured and attached to the chip 1. Irrespective of if the first output port 10 and the radiating element 22 are different parts or are formed from the same part, they are electrically connected to each other.
The dielectric carrier material may be formed in a number of different ways. In this example, the dielectric carrier material 12 is in the form of a multilayer structure, comprising a top layer 31 and a bottom layer 32. The top layer 31 comprises a first top layer side and a second top layer side 33, where the first top layer side is constituted by the first main side 13. The bottom layer 32 comprises a first bottom layer side 34 and a second bottom layer side, where the second bottom layer side is constituted by the second main side 14.
The second top layer side 33 comprises a first metalization 35, and the first bottom layer side 34 comprises a second metalization 36.
The top layer 31 is made in a first material, and the bottom layer 32 is made in a second material, the top layer 31 and the bottom layer 32 being mounted to each other by means of an adhesive compound 37, positioned between the first metalization 35 and the second metalization 36. The adhesive compound 37 is for example in the form of a special epoxy film, known as prepreg. For example, the bottom layer 32 is comprised by re-inforced glass fibre, known as FR4, and the top layer 31 is comprised by a PTFE (polytetrafluoroethylene) laminate.
There is a cavity 38 formed in the top layer 31 , such that the chip 1 is mounted to the first metalization 35. In this example, the second chip main side 3 comprises a chip metalization 39, where the chip metalization 39 is fastened to the first metalization 35 by means of soldering or similar.
The metalizations 30, 35, 36 described are made by relatively thin metal films, having a thickness of for example 17μm or 35μm, and being made in for example copper or gold, where the copper may be plated by a desired metal. The chip metallization, however, may be of the magnitude 3 μm.
As shown in Figure 1 and Figure 2, on the first chip main side 2 there is a metalization forming a frame 40 around the radiating element 22 when it enters the waveguide 24, except for a probe transition 41. The frame 40 comprises a number of via holes, for reasons of clarity only one is shown with a reference number 42, but of course all the vias shown are of the same kind. The vias 42 are electrically connecting the frame 40 to the chip metalization 39 such that a virtual electrically conducting wall is obtained along the height of the chip 1.
As an alternative for the dielectric carrier material 12, it may be made having one dielectric material layer only, where the side of the dielectric material layer that faces away from the waveguide 24 is attached to a rigid metal layer, known as hardback (not shown). In this case, a cavity is formed in the dielectric material layer such that the chip 1 is mounted to the rigid metal layer. The rigid metal layer may for example be made in copper or brass, and may be gold-plated.
By means of the present invention, the use of a bond wire for an output signal at relatively high frequencies, such as 60-90 GHz, may be avoided. Instead a direct connection from an output port on the chip to a radiating element is used, the radiating element being used for signal transfer to a waveguide. Of course this works reciprocally, such that the first output port 10 which in this example has been arranged for outputting a signal, instead could be an input port arranged for receiving an input signal that is fed from the waveguide 24. Then the radiating element 22 is connected to an input port instead, and transfers an input signal from the waveguide to the input port.
The present invention is not limited to the examples described above, but may vary freely within the scope of the appended claims. For example, the present invention may be used with any suitable planar structure that forms a chip, having at least one electrical function.
In the examples discussed above where the radiating element 22 is fastened to the first output port 10, this may be done in many ways, for example by means of soldering or thermal compression.
The chip may be made in many suitable materials such as GaAs (Gallium- Arsenide), SiGe (Silicon-Germanium) and CMOS (Complementary metal- oxide-semiconductor). The chip may be in the form of an MMIC (Monolithic Microwave Integrated Circuit). The chip does not have to be mounted in a cavity, but may for example be mounted on the first top layer side/first main side 13 of the dielectric carrier material 12.
The dielectric materials may comprise several layers if necessary, the layers comprising different types of circuitry and/or metalizations. Such a layered structure may also be necessary for mechanical reasons. The dielectric carrier material 12 and its layer or layers may be made in one or several materials including re-inforced glass fibre, known as FR4, re-inforced PTFE (polytetrafluoroethylene) and ceramic compounds.
The number of ports on the chip and corresponding connection pads on the dielectric carrier material 12 may of course vary depending on the types used; also the number of used ports and pads and which ports and pads that are used varies in the same way.
Where there is a metalization, the metal material may be any suitable conductor such as copper or gold.
The radiating element has been shown to have a T-shape, this is only an example of a shape. A radiating element used in the present invention may have any suitable shape as for example straight, chamfered, tapered and with varying widths continuously and/or is steps.
The frame 40 is shown comprising a single row of via holes 42. In order to further increase leakage suppression, more than one row of via holes may be used, the frame 40 then comprising at least two adjacent rows of via holes around its circumference.
The waveguide part 24 may be made in a non-conducting material, such as plastic, which is covered by a thin layer of metalization.
The 90° bend part 28 is showed comprising an inclined, continuous wall part 43, presenting an angle. An example of another shape of the 90° bend part 28 is a stepped structure, having a plurality of steps. The shapes described are commonly known for waveguide bends in general, and are designed to provide a matched transition from a microsthp element, such as the radiating element, to a waveguide. The prepreg used may be any sort of suitable adhesive compound.

Claims

1. A planar structure in the form of chip (1 ), the planar structure (1 ) having a first chip main side (2) and a second chip main side (3), where the first chip main side (2) comprises at least one input port (4, 5, 6), arranged to receive an input signal, at least one output port (10, 11 ), arranged to output an output signal, and at least one electrical functionality (F), the planar structure (1 ) being arranged for mounting on a dielectric carrier material (12) having a first main side (13) and a second main side (14), characterized in that one port (10) of said ports (4, 5, 6, 10, 11 ) is electrically connected to a radiating element (22) positioned on the first chip main side (2), the radiating element (22) being arranged for transferring a signal between a surface- mountable waveguide part (24) and said one port (10) when the surface- mountable waveguide part (24) is mounted on the dielectric carrier material (12) such that it covers the radiating element (22).
2. The planar structure according to claim 1 , characterized in that the planar structure (1 ) is mounted in a cavity (38) in the dielectric carrier material (12) such that the first chip main side (2) and the first main side (13) of the dielectric carrier material essentially lie in the same plane.
3. The planar structure according to any one of the claims 1 or 2, characterized in that those ports (4, 5, 6, 11 ) of said ports (4, 5, 6, 10, 11 ) that are separate from said one port (10) are arranged to be connected to corresponding connection pads (15, 16, 17, 21 ) by means of bond wires (23).
4. The planar structure according to any one of the preceding claims, characterized in that it is in the form of a chip (1 ) constituted by any one of CMOS, Complementary metal-oxide-semiconductor, SiGe, Silicon- Germanium, and GaAs, Gallium-Arsenide.
5. The planar structure according to claim 4, characterized in that the chip (1 ) comprises an LNA, Low Noise Amplifier.
6. The planar structure according to any one of the preceding claims, characterized in that the radiating element (22) is in the form of a microstrip patch element.
7. The planar structure according to any one of the claims 1 -5, characterized in that the radiating element (22) is in the form of a co-planar waveguide, CPW, patch element.
8. The planar structure according to any one of the preceding claims, characterized in that the dielectric carrier material (12) is in the form of a multilayer structure, comprising a top layer (31 ) and a bottom layer (32), where the top layer (31 ) comprises a first top layer side and a second top layer side (33), where the first top layer side is constituted by the first main side (13), and where the bottom layer (32) comprises a first bottom layer side (34) and a second bottom layer side, where the second bottom layer side is constituted by the second main side (14).
9. The planar structure according to claim 8, characterized in that the second top layer side (33) comprises a first metalization (35), and that the first bottom layer side (34) comprises a second metalization (36).
10. The planar structure according to claim 9, characterized in that the top layer (31 ) is made in a first material, and that the bottom layer (32) is made in a second material, the top layer (31 ) and the bottom layer (32) being mounted to each other by means of an adhesive compound (37), positioned between the first metalization (35), and the second metalization (36), and where the cavity (38) is formed in the top layer (31 ) such that the planar structure (1 ) is mounted to the first metalization (35).
11. A transition arrangement comprising a planar structure in the form of chip (1 ), the planar structure (1 ) having a first chip main side (2) and a second chip main side (3), where the first chip main side (2) comprises at least one input port (4, 5, 6), arranged to receive an input signal, at least one output port (10, 11 ), arranged to output an output signal, and at least one electrical functionality (F), the planar structure (1 ) being arranged for mounting on a dielectric carrier material (12) having a first main side (13) and a second main side (14), characterized in that one port (10) of said ports (4, 5, 6, 10, 11 ) is electrically connected to a radiating element (22) positioned on the first chip main side (2), the radiating element (22) being arranged for transferring a signal between a surface-mountable waveguide part (24) and said one port (10) when the surface-mountable waveguide part (24) is mounted on the dielectric carrier material (12) such that it covers the radiating element (22).
12. The transition according to claim 11 , characterized in that the planar structure (1 ) is mounted in a cavity (38) in the dielectric carrier material (12) such that the first chip main side (2) and the first main side (13) of the dielectric carrier material essentially lie in the same plane.
13. The transition according to any one of the claims 11 or 12, characterized in that those ports (4, 5, 6, 11 ) of said ports (4, 5, 6, 10, 11 ) that are separate from said one port (10) are arranged to be connected to corresponding connection pads (15, 16, 17, 21 ) by means of bond wires (23).
14. The transition according to any one of the claims 11 -13, characterized in that it is in the form of a chip (1 ) constituted by any one of CMOS, Complementary metal-oxide-semiconductor, SiGe, Silicon- Germanium, and GaAs, Gallium-Arsenide.
15. The transition according to claim 14, characterized in that the chip (1 ) comprises an LNA, Low Noise Amplifier.
16. The transition according to any one of the claims 11 -15, characterized in that the radiating element (22) is in the form of a microsthp patch element.
17. The transition according to any one of the claims 11 -15, characterized in that the radiating element (22) is in the form of a co-planar waveguide, CPW, patch element.
18. The transition according to any one of the claims 11 -17, characterized in that the dielectric carrier material (12) is in the form of a multilayer structure, comprising a top layer (31 ) and a bottom layer (32), where the top layer (31 ) comprises a first top layer side and a second top layer side (33), where the first top layer side is constituted by the first main side (13), and where the bottom layer (32) comprises a first bottom layer side (34) and a second bottom layer side, where the second bottom layer side is constituted by the second main side (14).
19. The transition according to claim 18, characterized in that the second top layer side (33) comprises a first metalization (35), and that the first bottom layer side (34) comprises a second metalization (36).
20. The transition according to claim 19, characterized in that the top layer (31 ) is made in a first material, and that the bottom layer (32) is made in a second material, the top layer (31 ) and the bottom layer (32) being mounted to each other by means of an adhesive compound (37), positioned between the first metalization (35), and the second metalization (36), and where the cavity (38) is formed in the top layer (31 ) such that the planar structure (1 ) is mounted to the first metalization (35).
PCT/EP2009/055911 2009-05-15 2009-05-15 A transition from a chip to a waveguide WO2010130293A1 (en)

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