JP2020080405A5 - - Google Patents

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Publication number
JP2020080405A5
JP2020080405A5 JP2019194604A JP2019194604A JP2020080405A5 JP 2020080405 A5 JP2020080405 A5 JP 2020080405A5 JP 2019194604 A JP2019194604 A JP 2019194604A JP 2019194604 A JP2019194604 A JP 2019194604A JP 2020080405 A5 JP2020080405 A5 JP 2020080405A5
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JP
Japan
Prior art keywords
etch
etching
excess metal
layer
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019194604A
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English (en)
Japanese (ja)
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JP2020080405A (ja
JP7278194B2 (ja
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Priority claimed from GBGB1817370.8A external-priority patent/GB201817370D0/en
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Publication of JP2020080405A publication Critical patent/JP2020080405A/ja
Publication of JP2020080405A5 publication Critical patent/JP2020080405A5/ja
Application granted granted Critical
Publication of JP7278194B2 publication Critical patent/JP7278194B2/ja
Active legal-status Critical Current
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JP2019194604A 2018-10-25 2019-10-25 集積回路を製造する方法 Active JP7278194B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1817370.8 2018-10-25
GBGB1817370.8A GB201817370D0 (en) 2018-10-25 2018-10-25 A method of fabricating integrated circuits

Publications (3)

Publication Number Publication Date
JP2020080405A JP2020080405A (ja) 2020-05-28
JP2020080405A5 true JP2020080405A5 (enExample) 2022-10-21
JP7278194B2 JP7278194B2 (ja) 2023-05-19

Family

ID=64560369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019194604A Active JP7278194B2 (ja) 2018-10-25 2019-10-25 集積回路を製造する方法

Country Status (7)

Country Link
US (1) US11361975B2 (enExample)
EP (1) EP3644352A1 (enExample)
JP (1) JP7278194B2 (enExample)
KR (1) KR102542747B1 (enExample)
CN (1) CN111106006B (enExample)
GB (1) GB201817370D0 (enExample)
TW (1) TWI801672B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114361057B (zh) * 2021-12-27 2025-07-22 粤芯半导体技术股份有限公司 半导体器件的缺陷检测方法及电子设备

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242536A (en) * 1990-12-20 1993-09-07 Lsi Logic Corporation Anisotropic polysilicon etching process
US5362356A (en) * 1990-12-20 1994-11-08 Lsi Logic Corporation Plasma etching process control
JPH05259127A (ja) * 1992-01-14 1993-10-08 Lsi Logic Corp プラズマエッチングにおけるエッチング監視方法
KR100293830B1 (ko) * 1992-06-22 2001-09-17 리차드 에이치. 로브그렌 플라즈마 처리 쳄버내의 잔류물 제거를 위한 플라즈마 정결방법
US6759263B2 (en) * 2002-08-29 2004-07-06 Chentsau Ying Method of patterning a layer of magnetic material
DE102005004360A1 (de) * 2005-01-31 2006-08-17 Advanced Micro Devices, Inc., Sunnyvale Effizientes Verfahren zum Herstellen und Zusammenfügen eines mikroelektronischen Chips mit Lothöckern
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US8659165B2 (en) * 2008-08-12 2014-02-25 Texas Instruments Incorporated Contact and VIA interconnects using metal around dielectric pillars
US7687311B1 (en) 2008-11-13 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing stackable dies
US20110155692A1 (en) * 2009-12-30 2011-06-30 Tzong-Liang Yau Method of forming patterns
US20120009777A1 (en) * 2010-07-07 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. UBM Etching Methods
CN103107085B (zh) 2013-01-31 2016-02-10 电子科技大学 一种NiCr薄膜的干法刻蚀工艺
US20140252571A1 (en) * 2013-03-06 2014-09-11 Maxim Integrated Products, Inc. Wafer-level package mitigated undercut
US20150048496A1 (en) 2013-08-13 2015-02-19 Macrotech Technology Inc. Fabrication process and structure to form bumps aligned on tsv on chip backside
US20160099173A1 (en) * 2014-10-03 2016-04-07 Applied Materials, Inc. Methods for etching a barrier layer for an interconnection structure for semiconductor applications
CN105355574B (zh) * 2015-11-13 2018-12-11 颀中科技(苏州)有限公司 镍金凸块的制作方法及镍金凸块组件
US10297551B2 (en) * 2016-08-12 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package
JP6702108B2 (ja) 2016-09-14 2020-05-27 富士通株式会社 端子構造、半導体装置、電子装置及び端子の形成方法

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