JP2020047917A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2020047917A JP2020047917A JP2019160462A JP2019160462A JP2020047917A JP 2020047917 A JP2020047917 A JP 2020047917A JP 2019160462 A JP2019160462 A JP 2019160462A JP 2019160462 A JP2019160462 A JP 2019160462A JP 2020047917 A JP2020047917 A JP 2020047917A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- chip
- semiconductor device
- upper insulating
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 225
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000011810 insulating material Substances 0.000 claims abstract description 11
- 230000003247 decreasing effect Effects 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 69
- 238000012360 testing method Methods 0.000 claims description 58
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 239000002184 metal Substances 0.000 claims description 52
- 238000012544 monitoring process Methods 0.000 claims description 39
- 238000002161 passivation Methods 0.000 claims description 18
- 230000007423 decrease Effects 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 description 137
- 239000010410 layer Substances 0.000 description 105
- 238000005520 cutting process Methods 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 23
- 238000005530 etching Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 5
- 230000001678 irradiating effect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical compound C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- -1 TiN Chemical class 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000417 polynaphthalene Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
Abstract
Description
20 スクライブライン領域
21 カッティング領域
23 エッジ領域
40 工程モニターリング構造体
100 半導体基板
101 半導体集積回路
103 層間絶縁膜
105a 下部配線
105b ダミー下部配線
110 下部絶縁膜
120 ダム構造体
121a 金属配線
122a 金属ビア
123a チップパッド
130 上部絶縁膜
140 再配線層
141a 再配線チップパッド
151 保護膜
153 パッシベーション層
Claims (25)
- チップ領域及び前記チップ領域周辺のエッジ領域を含む半導体基板と、
前記半導体基板上に配置された下部絶縁膜と、
前記チップ領域の前記下部絶縁膜上に配置されたチップパッドと、
前記下部絶縁膜と異なる絶縁物質を含み、前記下部絶縁膜上で前記チップパッドを覆う上部絶縁膜と、
前記チップ領域で前記上部絶縁膜を貫通してチップパッドと連結される再配線チップパッドと、を含み、
前記上部絶縁膜は、
前記チップ領域で第1厚さを有する第1部分と、
前記第1部分から延長されて前記エッジ領域に配置され、前記第1厚さより小さい第2厚さを有する第2部分と、
前記第1部分と離隔され、前記第2部分から延長された第3部分と、を含み、前記第3部分の厚さは、前記第2部分から遠くなるほど、減少する半導体装置。 - 前記上部絶縁膜は、前記第1部分と前記第2部分との間に第1傾斜面を有し、前記第2部分と前記第3部分との間に第2傾斜面を有し、
前記第1傾斜面の傾斜度は、前記第2傾斜面の傾斜度と異なる請求項1に記載の半導体装置。 - 前記下部絶縁膜は、前記上部絶縁膜より低い誘電常数を有する誘電物質を含む請求項1又は2に記載の半導体装置。
- 前記エッジ領域で、前記下部絶縁膜は、第1下部厚さを有する第1部分及び前記第1下部厚さより小さい第2下部厚さを有する第2部分を含む請求項1又は2に記載の半導体装置。
- 前記エッジ領域の前記下部絶縁膜内に提供されたダム構造体をさらに含み、
前記ダム構造体は、前記上部絶縁膜の前記第2部分の下に配置される請求項1−4のうち何れか1項に記載の半導体装置。 - 前記エッジ領域の前記半導体基板上に配置されたテスト構造体をさらに含み、
前記テスト構造体は、前記上部絶縁膜の前記第3部分と重畳される請求項1−4のうち何れか1項に記載の半導体装置。 - 前記エッジ領域で前記下部絶縁膜上に配置されたダミー金属パターンをさらに含み、
前記上部絶縁膜は、前記エッジ領域で前記ダミー金属パターンの一部を露出させる請求項1−4のうち何れか1項に記載の半導体装置。 - 前記ダミー金属パターンと重畳されるように前記下部絶縁膜内に提供されたダミー金属構造体をさらに含み、
前記ダミー金属構造体は、前記ダミー金属パターンと異なる金属物質を含む請求項7に記載の半導体装置。 - 前記エッジ領域の前記下部絶縁膜上に配置された工程モニターリングパターンをさらに含み、
前記上部絶縁膜は、前記エッジ領域で前記第1厚さと実質的に同一な第4厚さを有し、前記工程モニターリングパターンを覆う第4部分をさらに含む請求項1−4のうち何れか1項に記載の半導体装置。 - 前記上部絶縁膜の前記第1部分を覆い、前記第2及び第3部分を露出させるパッシベーション層さらに含む請求項1−9のうち何れか1項に記載の半導体装置。
- チップ領域及び前記チップ領域周辺のエッジ領域を含む半導体基板と、
前記半導体基板上に配置された下部絶縁膜と、
前記チップ領域の前記下部絶縁膜上に配置されたチップパッドと、
前記下部絶縁膜上に配置され、前記チップ領域で前記チップパッドを露出させる第1オープニング及び前記エッジ領域で前記下部絶縁膜の一部を露出させる第2オープニングを有する上部絶縁膜と、
前記第1オープニング内で前記チップパッドと連結される再配線チップパッドと、を含み、
前記第2オープニングの少なくとも一部は、丸味を帯びた側壁を有する半導体装置。 - 前記エッジ領域で、前記上部絶縁膜は、第1厚さを有する第1部分、前記チップ領域から遠くなるほど、減少する厚さを有する第2部分を含み、
前記チップ領域で前記上部絶縁膜は、前記第1厚さより大きい第2厚さを有する請求項11に記載の半導体装置。 - 前記エッジ領域で、前記下部絶縁膜は、第1厚さを有する第1部分及び前記第1厚さより小さい第2厚さを有する第2部分を含む請求項11又は12に記載の半導体装置。
- 前記上部絶縁膜の前記第2オープニングは、前記下部絶縁膜の前記第2部分を露出させる請求項13に記載の半導体装置。
- 前記上部絶縁膜は、順に積層された第1、第2、及び第3絶縁膜を含み、前記第2絶縁膜は、前記第1及び第3絶縁膜と異なる絶縁物質を含み、
前記エッジ領域で前記第3絶縁膜は、段差を有する請求項11−14のうち何れか1項に記載の半導体装置。 - 前記下部絶縁膜は、前記上部絶縁膜より低い誘電常数を有する誘電物質を含む請求項11−14のうち何れか1項に記載の半導体装置。
- 前記エッジ領域の前記半導体基板上に提供されたテスト構造体をさらに含み、
前記上部絶縁膜の前記第2オープニングは、前記テスト構造体とオーバーラップされる請求項11−14のうち何れか1項に記載の半導体装置。 - 前記エッジ領域で前記下部絶縁膜上に配置されるダミー金属パターンをさらに含み、
前記上部絶縁膜の前記第2オープニングは、前記ダミー金属パターンを露出させる請求項11−14のうち何れか1項に記載の半導体装置。 - 前記ダミー金属パターンは、前記チップパッドと同一なレベルに位置する請求項18に記載の半導体装置。
- 前記エッジ領域の前記半導体基板上に配置されたテスト構造体と、
前記エッジ領域の前記下部絶縁膜上に配置され、前記テスト構造体と連結される再配線テストパッドと、をさらに含み、
前記第2オープニングは、前記再配線テストパッドの一部を露出させる請求項11−14のうち何れか1項に記載の半導体装置。 - 前記チップ領域の前記上部絶縁膜上に配置されて、前記再配線チップパッドの一部及び前記上部絶縁膜の前記丸味を帯びた側壁を露出させるパッシベーション層をさらに含む請求項11−14のうち何れか1項に記載の半導体装置。
- 前記エッジ領域の一部に提供される工程モニターリング構造体をさらに含み、
前記上部絶縁膜は、前記エッジ領域に延長されて前記工程モニターリング構造体を覆う請求項11−14のうち何れか1項に記載の半導体装置。 - チップ領域及び前記チップ領域周辺のエッジ領域を含む半導体基板と、
前記半導体基板上に配置された下部絶縁膜と、
前記チップ領域の前記下部絶縁膜上に配置されたチップパッドと、
前記下部絶縁膜と異なる絶縁物質を含み、前記下部絶縁膜上で前記チップパッドを覆う上部絶縁膜と、
前記チップ領域で前記上部絶縁膜を貫通してチップパッドと連結される再配線チップパッドと、を含み、
前記上部絶縁膜は、
前記エッジ領域の一部で第1厚さを有する第1部分と、
前記エッジ領域の他の一部で前記第1厚さより小さい第2厚さを有する第2部分と、を含む半導体装置。 - 前記エッジ領域の半導体基板上に配置された工程モニターリング構造体をさらに含み、
前記上部絶縁膜の第1部分は、前記工程モニターリング構造体を覆う請求項23に記載の半導体装置。 - 前記上部絶縁膜は、前記エッジ領域で丸味を帯びた側壁を有する請求項23に記載の半導体装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020180111016A KR102571558B1 (ko) | 2018-09-17 | 2018-09-17 | 반도체 장치 |
KR10-2018-0111016 | 2018-09-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020047917A true JP2020047917A (ja) | 2020-03-26 |
JP7300939B2 JP7300939B2 (ja) | 2023-06-30 |
Family
ID=69772279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019160462A Active JP7300939B2 (ja) | 2018-09-17 | 2019-09-03 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US11075181B2 (ja) |
JP (1) | JP7300939B2 (ja) |
KR (1) | KR102571558B1 (ja) |
CN (1) | CN110911372A (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102557402B1 (ko) * | 2018-10-19 | 2023-07-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR102518803B1 (ko) | 2018-10-24 | 2023-04-07 | 삼성전자주식회사 | 반도체 패키지 |
US11088094B2 (en) * | 2019-05-31 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air channel formation in packaging process |
US11735487B2 (en) * | 2019-10-30 | 2023-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method of fabricating the same |
KR20220033655A (ko) * | 2020-09-09 | 2022-03-17 | 삼성전자주식회사 | 반도체 패키지 |
CN113270393B (zh) * | 2021-05-12 | 2024-03-15 | 武汉新芯集成电路制造有限公司 | 测试键结构及晶圆堆叠结构 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001071805A1 (en) * | 2000-03-23 | 2001-09-27 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
JP2006228865A (ja) * | 2005-02-16 | 2006-08-31 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2008047652A (ja) * | 2006-08-11 | 2008-02-28 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
JP2009239149A (ja) * | 2008-03-28 | 2009-10-15 | Nec Electronics Corp | 半導体ウエハ、半導体チップ、半導体装置、及び半導体装置の製造方法 |
JP2013077800A (ja) * | 2011-09-15 | 2013-04-25 | Fujitsu Semiconductor Ltd | 半導体装置、半導体ウェハ及び半導体装置の製造方法 |
JP2017034185A (ja) * | 2015-08-05 | 2017-02-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
WO2017056297A1 (ja) * | 2015-10-01 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3953027B2 (ja) | 2003-12-12 | 2007-08-01 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP4654598B2 (ja) | 2004-04-30 | 2011-03-23 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP2007027600A (ja) | 2005-07-21 | 2007-02-01 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2007103717A (ja) | 2005-10-05 | 2007-04-19 | Sony Corp | 半導体装置及びその製造方法 |
KR100881109B1 (ko) | 2005-11-24 | 2009-02-02 | 가부시키가이샤 리코 | 스크라이브 라인에 의해 분할된 반도체 칩 및 스크라이브 라인 상에 형성된 공정-모니터 전극 패드를 포함하는 반도체 웨이퍼 |
JP5055895B2 (ja) | 2006-08-25 | 2012-10-24 | ソニー株式会社 | 印刷用マスク、印刷用マスクの使用方法及び半導体装置の製造方法 |
JP5622433B2 (ja) | 2010-04-28 | 2014-11-12 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5244898B2 (ja) | 2010-12-14 | 2013-07-24 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
US8994148B2 (en) * | 2013-02-19 | 2015-03-31 | Infineon Technologies Ag | Device bond pads over process control monitor structures in a semiconductor die |
US9917011B2 (en) | 2014-05-19 | 2018-03-13 | Sharp Kabushiki Kaisha | Semiconductor wafer, semiconductor device diced from semiconductor wafer, and method for manufacturing semiconductor device |
US9496189B2 (en) * | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
KR102428328B1 (ko) | 2017-07-26 | 2022-08-03 | 삼성전자주식회사 | 반도체 장치 |
-
2018
- 2018-09-17 KR KR1020180111016A patent/KR102571558B1/ko active IP Right Grant
-
2019
- 2019-05-21 US US16/418,036 patent/US11075181B2/en active Active
- 2019-09-03 JP JP2019160462A patent/JP7300939B2/ja active Active
- 2019-09-17 CN CN201910874908.8A patent/CN110911372A/zh active Pending
-
2021
- 2021-06-29 US US17/361,588 patent/US11626377B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001071805A1 (en) * | 2000-03-23 | 2001-09-27 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
JP2006228865A (ja) * | 2005-02-16 | 2006-08-31 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2008047652A (ja) * | 2006-08-11 | 2008-02-28 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
JP2009239149A (ja) * | 2008-03-28 | 2009-10-15 | Nec Electronics Corp | 半導体ウエハ、半導体チップ、半導体装置、及び半導体装置の製造方法 |
JP2013077800A (ja) * | 2011-09-15 | 2013-04-25 | Fujitsu Semiconductor Ltd | 半導体装置、半導体ウェハ及び半導体装置の製造方法 |
JP2017034185A (ja) * | 2015-08-05 | 2017-02-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
WO2017056297A1 (ja) * | 2015-10-01 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US11626377B2 (en) | 2023-04-11 |
KR20200032299A (ko) | 2020-03-26 |
JP7300939B2 (ja) | 2023-06-30 |
US11075181B2 (en) | 2021-07-27 |
KR102571558B1 (ko) | 2023-08-29 |
US20200091100A1 (en) | 2020-03-19 |
US20210327839A1 (en) | 2021-10-21 |
CN110911372A (zh) | 2020-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102428328B1 (ko) | 반도체 장치 | |
JP7300939B2 (ja) | 半導体装置 | |
JP7225056B2 (ja) | 半導体装置 | |
US10854562B2 (en) | Semiconductor device | |
US8871627B2 (en) | Semiconductor device having low dielectric insulating film and manufacturing method of the same | |
KR20200050349A (ko) | 금속 범프 측벽 보호 | |
US11721577B2 (en) | Semiconductor package and method of manufacturing the same | |
KR20230000798A (ko) | 반도체 패키지 및 그 제조 방법 | |
KR20200069710A (ko) | 전도성 필라를 갖는 반도체 패키지 및 그 제조 방법 | |
US11158589B2 (en) | Semiconductor device and semiconductor package comprising the same | |
US20230096434A1 (en) | Semiconductor chips having recessed regions | |
KR20230103160A (ko) | 리세스 영역을 갖는 반도체 칩 및 이를 포함하는 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210331 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220426 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220607 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220907 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20230110 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20230410 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20230613 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20230620 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7300939 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |