JP2020013988A - 改善された歩留まりを示す被覆された印刷された電子デバイス - Google Patents
改善された歩留まりを示す被覆された印刷された電子デバイス Download PDFInfo
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Abstract
Description
Claims (20)
- あるパターンで配置された複数のコンタクトパッドと、
別のパターンで配置された複数の電極トレースであって、一組の下部電極トレースおよび一組の上部電極トレースを含み、各電極トレースが、前記複数のコンタクトパッドのうちの関連付けられたコンタクトパッドと電気的に連絡する、複数の電極トレースと、
複数のメモリセルであって、各メモリセルが、前記複数の電極トレースのうちの一対の電極トレースの交差部に位置し、前記下部電極トレースのうちの1つの領域から形成される下部電極層、上部電極トレースのうちの1つの領域から形成される上部電極層、および前記下部電極層と前記上部電極層との間の強誘電体層、を含む、複数のメモリセルと、
前記複数の電極トレースを覆い、かつ各電極トレースの各縁部を越えて横方向に延在して各電極トレースを囲む緩衝帯を提供する保護層であって、前記緩衝帯が、各電極トレースの端部から延在して各関連付けられたコンタクトパッドの一部を重なり領域で覆い、各コンタクトパッドがまた、少なくとも1つの覆われていない縁部を有する、保護層と、を備える被覆された印刷された電子デバイス。 - 前記緩衝帯は、前記重なり領域において2*√2*(線位置合わせ能力)以下である緩衝帯幅を特徴とする、請求項1に記載のデバイス。
- 前記緩衝帯幅は、前記重なり領域において200μmより大きく、2*√2*(線位置合わせ能力)以下である、請求項2に記載のデバイス。
- 前記緩衝帯幅は、0より大きく500μm以下である、請求項1に記載のデバイス。
- 前記緩衝帯幅は、200μmより大きく500μm以下である、請求項1に記載のデバイス。
- 前記重なり領域以外の領域において、前記緩衝帯幅は、少なくとも2*√2*(線位置合わせ能力)である、請求項2に記載のデバイス。
- 前記重なり領域内の縁部の部分を除いて、各コンタクトパッドのすべての縁部は覆われていない、請求項1に記載のデバイス。
- 前記保護層は、前記保護層の縁部と各コンタクトパッドの隣接する対向縁部との間に間隙を画定するように構成されている、請求項1に記載のデバイス。
- 前記間隙は、少なくとも2*(線位置合わせ能力)である間隙幅を特徴とする、請求項8に記載のデバイス。
- 前記間隙は、少なくとも80μmである間隙幅を特徴とする、請求項8に記載のデバイス。
- 前記保護層は、前記複数のコンタクトパッド上に付けられた開口を画定するように構成されている、請求項1に記載のデバイス。
- 前記複数のコンタクトパッドは、互いに平行に延在する2つのアレイに配置され、それらの間に空間を画定すること、さらに前記保護層は、2つの開口を画定するように構成され、各開口が、前記2つのアレイのそれぞれの一方の上に位置付けられ、さらに前記複数の電極トレースが、前記空間内に位置付けられた格子パターンで配置されている、請求項1に記載のデバイス。
- 前記緩衝帯幅は、0より大きく500μm以下であり、さらに前記保護層は、前記保護層の縁部と各コンタクトパッドの隣接する対向縁部との間に間隙を画定するように構成され、前記間隙が、少なくとも80μmの間隙幅を特徴とする、請求項11に記載のデバイス。
- 前記緩衝帯幅は、0より大きく500μm以下であり、さらに前記保護層は、前記保護層の縁部と各コンタクトパッドの隣接する対向縁部との間に間隙を画定するように構成され、前記間隙は、少なくとも80μmの間隙幅を特徴とする、請求項12に記載のデバイス。
- 前記保護層は、前記複数の電極トレース上に位置付けられた連続的なほぼ矩形の形状の領域として構成されている、請求項1に記載のデバイス。
- 前記緩衝帯幅は、0より大きく500μm以下である、請求項15に記載のデバイス。
- 前記複数のコンタクトパッドは、互いに平行に延在し、それらの間に空間を画定する2つのアレイに配置され、さらに前記複数の電極トレースは、前記空間内に位置付けられた格子パターンで配置されている、請求項16に記載のデバイス。
- 基板と、前記基板上の複数の被覆された印刷された電子デバイスとを含む複数の被覆された印刷された電子デバイスであって、各デバイスが、請求項1に記載のデバイスに従って構成されている、複数の被覆された印刷された電子デバイス。
- 被覆された印刷された電子デバイスの製造方法であって、
基板上に複数の下部電極トレースを印刷することと、
前記複数の下部電極トレース上に強誘電体材料の層を印刷することと、
前記強誘電体材料の前記層上に複数の上部電極トレースを印刷することであって、前記複数の下部電極トレースおよび前記複数の上部電極トレースが、あるパターンで配置された複数の電極トレースを形成し、かつ複数のメモリセルを画定し、各メモリセルが、前記複数の電極トレースのうちの一対の電極トレースの交差部に位置する、印刷することと、
前記複数の電極トレース上に複数のコンタクトパッドを印刷することであって、前記複数のコンタクトパッドが、別のパターンで配置され、前記複数の電極トレースの各電極トレースが、前記複数のコンタクトパッドのうちの関連付けられたコンタクトパッドと電気的に連絡している、印刷することと、
前記複数の電極トレースおよび前記複数のコンタクトパッド上に硬化性組成物を印刷することと、
前記硬化性組成物を硬化させて保護層を形成することと、を含み、
前記保護層は、前記複数の電極トレースを覆い、かつ各電極トレースの各縁部を越えて横方向に延在して各電極トレースを囲む緩衝帯を提供し、前記緩衝帯が、各電極トレースの端部から延在して各関連付けられたコンタクトパッドの一部を重なり領域で覆い、各コンタクトパッドがまた、少なくとも1つの覆われていない縁部を有する、方法。 - 被覆された印刷された電子デバイスを使用する方法であって、被覆された印刷された電子デバイスの複数のコンタクトパッドを読み取り/書き込みユニットの複数のピンと接触させることを含み、前記デバイスは、
あるパターンで配置された前記複数のコンタクトパッドと、
別のパターンで配置された複数の電極トレースであって、一組の下部電極トレースおよび一組の上部電極トレースを含み、各電極トレースが、前記複数のコンタクトパッドのうちの関連付けられたコンタクトパッドと電気的に連絡する、複数の電極トレースと、
複数のメモリセルであって、各メモリセルが、前記複数の電極トレースのうちの一対の電極トレースの交差部に位置し、前記下部電極トレースのうちの1つの領域から形成される下部電極層、上部電極トレースのうちの1つの領域から形成される上部電極層、および前記下部電極層と前記上部電極層との間の強誘電体層を含む、複数のメモリセルと、
前記複数の電極トレースを覆い、かつ各電極トレースの各縁部を越えて横方向に延在して各電極トレースを囲む緩衝帯を提供する保護層であって、前記緩衝帯が、各電極トレースの端部から延在して各関連付けられたコンタクトパッドの一部を重なり領域で覆い、各コンタクトパッドがまた、少なくとも1つの覆われていない縁部を有する、保護層と、を備える、方法。
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US7374954B2 (en) * | 2003-05-30 | 2008-05-20 | Hynix Semiconductor Inc. | Ferroelectric register, and method for manufacturing capacitor of the same |
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US7767498B2 (en) | 2005-08-25 | 2010-08-03 | Vitex Systems, Inc. | Encapsulated devices and method of making |
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US5214300A (en) * | 1970-09-28 | 1993-05-25 | Ramtron Corporation | Monolithic semiconductor integrated circuit ferroelectric memory device |
US3720862A (en) * | 1971-01-18 | 1973-03-13 | Owens Illinois Inc | Capacitor with high k dielectric materials |
US4713157A (en) * | 1976-02-17 | 1987-12-15 | Ramtron Corporation | Combined integrated circuit/ferroelectric memory device, and ion beam methods of constructing same |
US7374954B2 (en) * | 2003-05-30 | 2008-05-20 | Hynix Semiconductor Inc. | Ferroelectric register, and method for manufacturing capacitor of the same |
US20070138520A1 (en) * | 2005-12-20 | 2007-06-21 | Agfa-Gevaert | Ferroelectric passive memory cell, device and method of manufacture thereof |
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