JP2020009441A5 - - Google Patents

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Publication number
JP2020009441A5
JP2020009441A5 JP2019123601A JP2019123601A JP2020009441A5 JP 2020009441 A5 JP2020009441 A5 JP 2020009441A5 JP 2019123601 A JP2019123601 A JP 2019123601A JP 2019123601 A JP2019123601 A JP 2019123601A JP 2020009441 A5 JP2020009441 A5 JP 2020009441A5
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Japan
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memory
address
error
memory address
data
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JP2019123601A
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Japanese (ja)
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JP2020009441A (ja
JP7252845B2 (ja
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Priority claimed from US16/150,239 external-priority patent/US11151006B2/en
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JP2019123601A 2018-07-02 2019-07-02 高帯域幅メモリのras(信頼性、アクセシビリティ、及びサービサビリティ)キャッシュ構造 Active JP7252845B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862692960P 2018-07-02 2018-07-02
US62/692,960 2018-07-02
US16/150,239 2018-10-02
US16/150,239 US11151006B2 (en) 2018-07-02 2018-10-02 HBM RAS cache architecture

Publications (3)

Publication Number Publication Date
JP2020009441A JP2020009441A (ja) 2020-01-16
JP2020009441A5 true JP2020009441A5 (enExample) 2022-07-08
JP7252845B2 JP7252845B2 (ja) 2023-04-05

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JP2019123601A Active JP7252845B2 (ja) 2018-07-02 2019-07-02 高帯域幅メモリのras(信頼性、アクセシビリティ、及びサービサビリティ)キャッシュ構造

Country Status (5)

Country Link
US (3) US11151006B2 (enExample)
JP (1) JP7252845B2 (enExample)
KR (1) KR102420098B1 (enExample)
CN (2) CN110673980B (enExample)
TW (1) TWI768200B (enExample)

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