KR102420098B1 - 고-대역폭 메모리 신뢰성, 접근성 및 유용성(ras) 캐시 구조 - Google Patents

고-대역폭 메모리 신뢰성, 접근성 및 유용성(ras) 캐시 구조 Download PDF

Info

Publication number
KR102420098B1
KR102420098B1 KR1020190039290A KR20190039290A KR102420098B1 KR 102420098 B1 KR102420098 B1 KR 102420098B1 KR 1020190039290 A KR1020190039290 A KR 1020190039290A KR 20190039290 A KR20190039290 A KR 20190039290A KR 102420098 B1 KR102420098 B1 KR 102420098B1
Authority
KR
South Korea
Prior art keywords
memory
address
error
data
memory address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020190039290A
Other languages
English (en)
Korean (ko)
Other versions
KR20200003709A (ko
Inventor
디민 니우
크리슈나 말라디
홍종 정
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Publication of KR20200003709A publication Critical patent/KR20200003709A/ko
Application granted granted Critical
Publication of KR102420098B1 publication Critical patent/KR102420098B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2094—Redundant storage or storage space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/82—Solving problems relating to consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
KR1020190039290A 2018-07-02 2019-04-03 고-대역폭 메모리 신뢰성, 접근성 및 유용성(ras) 캐시 구조 Active KR102420098B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862692960P 2018-07-02 2018-07-02
US62/692,960 2018-07-02
US16/150,239 2018-10-02
US16/150,239 US11151006B2 (en) 2018-07-02 2018-10-02 HBM RAS cache architecture

Publications (2)

Publication Number Publication Date
KR20200003709A KR20200003709A (ko) 2020-01-10
KR102420098B1 true KR102420098B1 (ko) 2022-07-12

Family

ID=69055272

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020190039290A Active KR102420098B1 (ko) 2018-07-02 2019-04-03 고-대역폭 메모리 신뢰성, 접근성 및 유용성(ras) 캐시 구조

Country Status (5)

Country Link
US (3) US11151006B2 (enExample)
JP (1) JP7252845B2 (enExample)
KR (1) KR102420098B1 (enExample)
CN (2) CN110673980B (enExample)
TW (1) TWI768200B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511017B (zh) * 2018-04-02 2021-08-20 郑州云海信息技术有限公司 一种光媒介存储光媒介机构及系统
US11151006B2 (en) * 2018-07-02 2021-10-19 Samsung Electronics Co., Ltd. HBM RAS cache architecture
US10802967B1 (en) * 2019-06-28 2020-10-13 Intel Corporation Partial write management in a multi-tiled compute engine
CN113495671B (zh) 2020-04-01 2023-10-17 长鑫存储技术有限公司 读写方法及存储器装置
EP3936996A4 (en) 2020-04-01 2022-07-06 Changxin Memory Technologies, Inc. READ-WRITE METHOD AND STORAGE DEVICE
EP3964940A4 (en) 2020-04-01 2022-08-17 Changxin Memory Technologies, Inc. READ/WRITE METHOD AND STORAGE DEVICE
EP3985494B1 (en) 2020-04-01 2024-01-17 Changxin Memory Technologies, Inc. Read-write method and memory device
CN113495672B (zh) 2020-04-01 2023-08-11 长鑫存储技术有限公司 读写方法及存储器装置
EP3964941B1 (en) 2020-04-01 2024-02-28 Changxin Memory Technologies, Inc. Read-write method and memory device
CN113495674B (zh) 2020-04-01 2023-10-10 长鑫存储技术有限公司 读写方法及存储器装置
CN113495675B (zh) 2020-04-01 2023-08-11 长鑫存储技术有限公司 读写方法及存储器装置
US12393344B2 (en) * 2020-04-07 2025-08-19 Micron Technology, Inc. Apparatuses and methods for die replacement in stacked memory
KR102893029B1 (ko) 2020-09-11 2025-11-27 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
WO2022056757A1 (en) * 2020-09-17 2022-03-24 Alibaba Group Holding Limited Three-dimensional stacked processing systems
US11573905B2 (en) * 2021-01-21 2023-02-07 Vmware, Inc. Saving page retire information persistently across operating system reboots
KR20230166563A (ko) * 2022-05-31 2023-12-07 삼성전자주식회사 작동 도중에 발생하는 메모리 고장을 실시간으로 리페어링하는 방법과 메모리 시스템, 및 메모리 시스템을 포함하는 데이터 처리 장치
US12373361B2 (en) * 2022-09-01 2025-07-29 Advanced Micro Devices, Inc. Systems, methods, and devices for advanced memory technology
US12019870B2 (en) 2022-11-07 2024-06-25 International Business Machines Corporation System wide memory technology over-provisioning
CN119336694A (zh) * 2023-07-21 2025-01-21 华为技术有限公司 一种芯片系统及通信设备
US20250279153A2 (en) * 2023-11-02 2025-09-04 Micron Technology, Inc. Sparing techniques in stacked memory architectures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140376320A1 (en) 2013-06-25 2014-12-25 Advanced Micro Devices, Inc. Spare memory external to protected memory
US20150199246A1 (en) 2014-01-16 2015-07-16 Fujitsu Limited Memory device, storage method and control device
US20150199126A1 (en) 2014-01-10 2015-07-16 Advanced Micro Devices, Inc. Page migration in a 3d stacked hybrid memory

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06139152A (ja) * 1992-10-27 1994-05-20 Kawasaki Steel Corp 記憶装置用入出力回路
JP3242890B2 (ja) * 1998-12-16 2001-12-25 株式会社ハギワラシスコム 記憶装置
DE102004047813A1 (de) * 2004-09-29 2006-03-30 Infineon Technologies Ag Halbleiterbaustein mit einer Umlenkschaltung
US20060080572A1 (en) 2004-09-30 2006-04-13 Fong John Y Set associative repair cache systems and methods
JP2006323739A (ja) * 2005-05-20 2006-11-30 Renesas Technology Corp メモリモジュール、メモリシステム、及び情報機器
US20070147115A1 (en) 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7647536B2 (en) 2005-12-30 2010-01-12 Intel Corporation Repair bits for a low voltage cache
US8898437B2 (en) 2007-11-02 2014-11-25 Qualcomm Incorporated Predecode repair cache for instructions that cross an instruction cache line
US8756486B2 (en) 2008-07-02 2014-06-17 Micron Technology, Inc. Method and apparatus for repairing high capacity/high bandwidth memory devices
US9042191B2 (en) 2009-08-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Self-repairing memory
CN103620562A (zh) * 2011-06-30 2014-03-05 惠普发展公司，有限责任合伙企业 包括用于将数据从活动存储器管芯拷贝至空闲存储器管芯的存储器模块拷贝引擎的存储器模块
US8867286B2 (en) 2011-12-20 2014-10-21 Industrial Technology Research Institute Repairable multi-layer memory chip stack and method thereof
CN103377143B (zh) * 2012-04-27 2016-12-21 群联电子股份有限公司 存储器管理方法、存储器控制器与存储器存储装置
US9230609B2 (en) * 2012-06-05 2016-01-05 Rambus Inc. Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
KR102025080B1 (ko) * 2013-01-02 2019-09-25 삼성전자 주식회사 스토리지 시스템 및 스토리지 시스템의 여분 공간 조절 방법
US9372750B2 (en) * 2013-11-01 2016-06-21 Qualcomm Incorporated Method and apparatus for non-volatile RAM error re-mapping
US20160147667A1 (en) 2014-11-24 2016-05-26 Samsung Electronics Co., Ltd. Address translation in memory
KR102190125B1 (ko) 2014-12-05 2020-12-11 삼성전자주식회사 어드레스 리매핑을 위한 적층형 메모리 장치, 이를 포함하는 메모리 시스템 및 어드레스 리매핑 방법
US9632867B2 (en) * 2014-12-08 2017-04-25 Cypress Semiconductor Corporation Methods, circuits, devices, systems and machine executable code for reading from a non-volatile memory array
KR102538246B1 (ko) * 2015-12-01 2023-06-01 삼성전자주식회사 불휘발성 메모리 모듈
CN106055420B (zh) * 2016-05-18 2019-07-16 东软医疗系统股份有限公司 一种数据校验方法、装置及设备
US10395748B2 (en) * 2016-06-15 2019-08-27 Micron Technology, Inc. Shared error detection and correction memory
KR102793137B1 (ko) 2016-11-07 2025-04-10 삼성전자주식회사 어드레스 맵핑 테이블의 에러 정정을 수행하는 메모리 시스템
US20180137005A1 (en) * 2016-11-15 2018-05-17 Intel Corporation Increased redundancy in multi-device memory package to improve reliability
US11151006B2 (en) * 2018-07-02 2021-10-19 Samsung Electronics Co., Ltd. HBM RAS cache architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140376320A1 (en) 2013-06-25 2014-12-25 Advanced Micro Devices, Inc. Spare memory external to protected memory
US20150199126A1 (en) 2014-01-10 2015-07-16 Advanced Micro Devices, Inc. Page migration in a 3d stacked hybrid memory
US20150199246A1 (en) 2014-01-16 2015-07-16 Fujitsu Limited Memory device, storage method and control device

Also Published As

Publication number Publication date
CN110673980A (zh) 2020-01-10
CN119356934A (zh) 2025-01-24
US11151006B2 (en) 2021-10-19
KR20200003709A (ko) 2020-01-10
JP2020009441A (ja) 2020-01-16
US20220035719A1 (en) 2022-02-03
US20250077370A1 (en) 2025-03-06
TWI768200B (zh) 2022-06-21
CN110673980B (zh) 2024-09-20
JP7252845B2 (ja) 2023-04-05
TW202006548A (zh) 2020-02-01
US12181987B2 (en) 2024-12-31
US20200004652A1 (en) 2020-01-02

Similar Documents

Publication Publication Date Title
KR102420098B1 (ko) 고-대역폭 메모리 신뢰성, 접근성 및 유용성(ras) 캐시 구조
US20240176546A1 (en) Quasi-volatile memory device with a back-channel usage
CN111279322B (zh) 一种处理系统和在3d堆栈存储器中混写的方法
US11726876B2 (en) FPGA acceleration system for MSR codes
US12189468B2 (en) Cloud scale server reliability management
US20180276161A1 (en) PCIe VIRTUAL SWITCHES AND AN OPERATING METHOD THEREOF
US11467902B2 (en) Apparatus to insert error-correcting coding (ECC) information as data within dynamic random access memory (DRAM)
CN113778328B (zh) 在半导体封装之间引导控制数据
US20210110043A1 (en) Platform firmware boot mechanism
US20220350500A1 (en) Embedded controller and memory to store memory error information
US20230318825A1 (en) Separately storing encryption keys and encrypted data in a hybrid memory
JP7402798B2 (ja) データセンタにおけるプログラマブルデバイス向けのセキュリティ
US12436711B2 (en) Providing fine grain access to package memory
USRE50078E1 (en) Device and system including adaptive repair circuit
CN116490925A (zh) 存储器电路架构
US11429496B2 (en) Platform data resiliency mechanism
US11960770B2 (en) Access request management using sub-commands
WO2022133873A1 (en) Configurable fault tolerant mechanism

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20190403

PG1501 Laying open of application
A201 Request for examination
A302 Request for accelerated examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20220323

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20190403

Comment text: Patent Application

PA0302 Request for accelerated examination

Patent event date: 20220323

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

Patent event date: 20190403

Patent event code: PA03021R01I

Comment text: Patent Application

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20220422

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20220707

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20220708

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20250625

Start annual number: 4

End annual number: 4