JP7252845B2 - 高帯域幅メモリのｒａｓ（信頼性、アクセシビリティ、及びサービサビリティ）キャッシュ構造 - Google Patents

高帯域幅メモリのｒａｓ（信頼性、アクセシビリティ、及びサービサビリティ）キャッシュ構造 Download PDF

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JP7252845B2
JP7252845B2 JP2019123601A JP2019123601A JP7252845B2 JP 7252845 B2 JP7252845 B2 JP 7252845B2 JP 2019123601 A JP2019123601 A JP 2019123601A JP 2019123601 A JP2019123601 A JP 2019123601A JP 7252845 B2 JP7252845 B2 JP 7252845B2
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memory
address
data
error
processor
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JP2020009441A (ja
JP2020009441A5 (enExample
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迪 民 牛
マラディ，クリシュナ
宏 忠 チョン
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Samsung Electronics Co Ltd
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    • G06F11/00—Error detection; Error correction; Monitoring
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    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
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    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
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    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches
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    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
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    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
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    • G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
    • G—PHYSICS
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    • G11C—STATIC STORES
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    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
JP2019123601A 2018-07-02 2019-07-02 高帯域幅メモリのｒａｓ（信頼性、アクセシビリティ、及びサービサビリティ）キャッシュ構造 Active JP7252845B2 (ja)

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US201862692960P 2018-07-02 2018-07-02
US62/692,960 2018-07-02
US16/150,239 2018-10-02
US16/150,239 US11151006B2 (en) 2018-07-02 2018-10-02 HBM RAS cache architecture

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JP2020009441A JP2020009441A (ja) 2020-01-16
JP2020009441A5 JP2020009441A5 (enExample) 2022-07-08
JP7252845B2 true JP7252845B2 (ja) 2023-04-05

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US (3) US11151006B2 (enExample)
JP (1) JP7252845B2 (enExample)
KR (1) KR102420098B1 (enExample)
CN (2) CN110673980B (enExample)
TW (1) TWI768200B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511017B (zh) * 2018-04-02 2021-08-20 郑州云海信息技术有限公司 一种光媒介存储光媒介机构及系统
US11151006B2 (en) * 2018-07-02 2021-10-19 Samsung Electronics Co., Ltd. HBM RAS cache architecture
US10802967B1 (en) * 2019-06-28 2020-10-13 Intel Corporation Partial write management in a multi-tiled compute engine
CN113495671B (zh) 2020-04-01 2023-10-17 长鑫存储技术有限公司 读写方法及存储器装置
EP3936996A4 (en) 2020-04-01 2022-07-06 Changxin Memory Technologies, Inc. READ-WRITE METHOD AND STORAGE DEVICE
EP3964940A4 (en) 2020-04-01 2022-08-17 Changxin Memory Technologies, Inc. READ/WRITE METHOD AND STORAGE DEVICE
EP3985494B1 (en) 2020-04-01 2024-01-17 Changxin Memory Technologies, Inc. Read-write method and memory device
CN113495672B (zh) 2020-04-01 2023-08-11 长鑫存储技术有限公司 读写方法及存储器装置
EP3964941B1 (en) 2020-04-01 2024-02-28 Changxin Memory Technologies, Inc. Read-write method and memory device
CN113495674B (zh) 2020-04-01 2023-10-10 长鑫存储技术有限公司 读写方法及存储器装置
CN113495675B (zh) 2020-04-01 2023-08-11 长鑫存储技术有限公司 读写方法及存储器装置
US12393344B2 (en) * 2020-04-07 2025-08-19 Micron Technology, Inc. Apparatuses and methods for die replacement in stacked memory
KR102893029B1 (ko) 2020-09-11 2025-11-27 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
WO2022056757A1 (en) * 2020-09-17 2022-03-24 Alibaba Group Holding Limited Three-dimensional stacked processing systems
US11573905B2 (en) * 2021-01-21 2023-02-07 Vmware, Inc. Saving page retire information persistently across operating system reboots
KR20230166563A (ko) * 2022-05-31 2023-12-07 삼성전자주식회사 작동 도중에 발생하는 메모리 고장을 실시간으로 리페어링하는 방법과 메모리 시스템, 및 메모리 시스템을 포함하는 데이터 처리 장치
US12373361B2 (en) * 2022-09-01 2025-07-29 Advanced Micro Devices, Inc. Systems, methods, and devices for advanced memory technology
US12019870B2 (en) 2022-11-07 2024-06-25 International Business Machines Corporation System wide memory technology over-provisioning
CN119336694A (zh) * 2023-07-21 2025-01-21 华为技术有限公司 一种芯片系统及通信设备
US20250279153A2 (en) * 2023-11-02 2025-09-04 Micron Technology, Inc. Sparing techniques in stacked memory architectures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140082411A1 (en) 2011-06-30 2014-03-20 Hewlett-Packard Development Company, L.P. Memory module that includes a memory module copy engine for copying data from an active memory die to a spare memory die
US20150199246A1 (en) 2014-01-16 2015-07-16 Fujitsu Limited Memory device, storage method and control device

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06139152A (ja) * 1992-10-27 1994-05-20 Kawasaki Steel Corp 記憶装置用入出力回路
JP3242890B2 (ja) * 1998-12-16 2001-12-25 株式会社ハギワラシスコム 記憶装置
DE102004047813A1 (de) * 2004-09-29 2006-03-30 Infineon Technologies Ag Halbleiterbaustein mit einer Umlenkschaltung
US20060080572A1 (en) 2004-09-30 2006-04-13 Fong John Y Set associative repair cache systems and methods
JP2006323739A (ja) * 2005-05-20 2006-11-30 Renesas Technology Corp メモリモジュール、メモリシステム、及び情報機器
US20070147115A1 (en) 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7647536B2 (en) 2005-12-30 2010-01-12 Intel Corporation Repair bits for a low voltage cache
US8898437B2 (en) 2007-11-02 2014-11-25 Qualcomm Incorporated Predecode repair cache for instructions that cross an instruction cache line
US8756486B2 (en) 2008-07-02 2014-06-17 Micron Technology, Inc. Method and apparatus for repairing high capacity/high bandwidth memory devices
US9042191B2 (en) 2009-08-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Self-repairing memory
US8867286B2 (en) 2011-12-20 2014-10-21 Industrial Technology Research Institute Repairable multi-layer memory chip stack and method thereof
CN103377143B (zh) * 2012-04-27 2016-12-21 群联电子股份有限公司 存储器管理方法、存储器控制器与存储器存储装置
US9230609B2 (en) * 2012-06-05 2016-01-05 Rambus Inc. Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
KR102025080B1 (ko) * 2013-01-02 2019-09-25 삼성전자 주식회사 스토리지 시스템 및 스토리지 시스템의 여분 공간 조절 방법
US9406403B2 (en) * 2013-06-25 2016-08-02 Advanced Micro Devices, Inc. Spare memory external to protected memory
US9372750B2 (en) * 2013-11-01 2016-06-21 Qualcomm Incorporated Method and apparatus for non-volatile RAM error re-mapping
US9535831B2 (en) 2014-01-10 2017-01-03 Advanced Micro Devices, Inc. Page migration in a 3D stacked hybrid memory
US20160147667A1 (en) 2014-11-24 2016-05-26 Samsung Electronics Co., Ltd. Address translation in memory
KR102190125B1 (ko) 2014-12-05 2020-12-11 삼성전자주식회사 어드레스 리매핑을 위한 적층형 메모리 장치, 이를 포함하는 메모리 시스템 및 어드레스 리매핑 방법
US9632867B2 (en) * 2014-12-08 2017-04-25 Cypress Semiconductor Corporation Methods, circuits, devices, systems and machine executable code for reading from a non-volatile memory array
KR102538246B1 (ko) * 2015-12-01 2023-06-01 삼성전자주식회사 불휘발성 메모리 모듈
CN106055420B (zh) * 2016-05-18 2019-07-16 东软医疗系统股份有限公司 一种数据校验方法、装置及设备
US10395748B2 (en) * 2016-06-15 2019-08-27 Micron Technology, Inc. Shared error detection and correction memory
KR102793137B1 (ko) 2016-11-07 2025-04-10 삼성전자주식회사 어드레스 맵핑 테이블의 에러 정정을 수행하는 메모리 시스템
US20180137005A1 (en) * 2016-11-15 2018-05-17 Intel Corporation Increased redundancy in multi-device memory package to improve reliability
US11151006B2 (en) * 2018-07-02 2021-10-19 Samsung Electronics Co., Ltd. HBM RAS cache architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140082411A1 (en) 2011-06-30 2014-03-20 Hewlett-Packard Development Company, L.P. Memory module that includes a memory module copy engine for copying data from an active memory die to a spare memory die
US20150199246A1 (en) 2014-01-16 2015-07-16 Fujitsu Limited Memory device, storage method and control device
JP2015135577A (ja) 2014-01-16 2015-07-27 富士通株式会社 記憶装置、記憶方法及び制御装置

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CN110673980A (zh) 2020-01-10
CN119356934A (zh) 2025-01-24
US11151006B2 (en) 2021-10-19
KR20200003709A (ko) 2020-01-10
JP2020009441A (ja) 2020-01-16
US20220035719A1 (en) 2022-02-03
US20250077370A1 (en) 2025-03-06
TWI768200B (zh) 2022-06-21
CN110673980B (zh) 2024-09-20
TW202006548A (zh) 2020-02-01
US12181987B2 (en) 2024-12-31
US20200004652A1 (en) 2020-01-02
KR102420098B1 (ko) 2022-07-12

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