JP2019534566A - 高圧アニーリング及び湿式エッチング速度の低下 - Google Patents
高圧アニーリング及び湿式エッチング速度の低下 Download PDFInfo
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract
Description
本出願は、「高圧アニーリング及び湿式エッチング速度の低下」と題する2016年11月1日出願の米国仮特許出願第62/415,757号、及び「高圧アニーリング及び湿式エッチング速度の低減」と題する2016年11月23日出願の米国非仮出願第15/360,016号の利益を主張する。第62/415,757及び第15/360,016の開示は、あらゆる目的のためにその全体を参照することによって本明細書に組み込まれる。
Claims (15)
- パターン形成された基板の上で間隙充填誘電体を処理する方法であって、
前記パターン形成された基板の上の間隙に、ポアを含むがそれ以外は前記パターン形成された基板の上の前記間隙を充填する間隙充填誘電体を形成することと、
前記パターン形成された基板を基板処理チャンバの基板処理領域内に配置することと、
高密度化された間隙充填誘電体を形成するために、前記間隙充填誘電体を14.7psiを上回る分圧で気相H2Oに曝露することによって、前記間隙充填誘電体を高密度化することと
を含む方法。 - 前記間隙充填誘電体が、ケイ素及び水素を含む、請求項1に記載の方法。
- 前記間隙充填誘電体を高密度化する前に、前記間隙充填誘電体をUV光に曝露することを更に含む、請求項1に記載の方法。
- 前記間隙充填誘電体をHF又は緩衝酸化物エッチング溶液でエッチングすることを更に含む、請求項1に記載の方法。
- 前記パターン形成された基板の温度が、前記間隙充填誘電体を高密度化する間、300°Cから700°Cの間である、請求項1に記載の方法。
- 前記基板処理領域内の露出面の最低温度が180°Cを上回る、請求項1に記載の方法。
- 前記間隙充填誘電体を高密度化した後に、前記パターン形成された基板を前記基板処理領域から取り外すことを更に含む、請求項1に記載の方法。
- 前記間隙充填誘電体を形成することが、前記間隙充填誘電体が前記パターン形成された基板の上の他の場所に最初に堆積された後に、前記間隙に材料を流入させることを含む、請求項1に記載の方法。
- 前記間隙充填誘電体を形成することが、液相前駆体から前記パターン形成された基板の上に材料を流動させることを含む、請求項1に記載の方法。
- 前記間隙充填誘電体が、前記間隙充填誘電体を形成した後に、ケイ素、炭素、窒素、水素及び酸素以外の元素を包含しない、請求項1に記載の方法。
- パターン形成された基板のトレンチを充填する方法であって、
前記パターン形成された基板の上に誘電体膜を形成することであって、誘電体材料を、前記パターン形成された基板の上の他の場所に最初に堆積した後に、前記トレンチに流入させることを含む、誘電体膜を形成することと、
前記パターン形成された基板を基板処理チャンバの基板処理領域内に配置することと、
高密度化された間隙充填誘電体を形成するために、前記基板処理領域内のH2Oの分圧で前記誘電体材料を気相H2Oに曝露することによって、前記トレンチの中の前記誘電体材料を高密度化することと
を含む方法。 - 前記基板処理領域内で露出される最も冷たい表面の温度が180°Cから275°Cの間である、請求項11に記載の方法。
- 前記基板処理領域内のH2Oの前記分圧が、145psiから864psiの間である、請求項11に記載の方法。
- プロセス圧力(psiでの)が(14.7/760)*10(a−b/(T+c))未満であり、ここでa=7.96681、b=1668.21、c=228であり、かつTは前記基板処理領域内の任意の露出面の最低温度であり、Tが100°Cから374°Cの間である、請求項11に記載の方法。
- 前記誘電体材料を高密度化している間、前記基板処理領域内に結露が形成されない、請求項11に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662415757P | 2016-11-01 | 2016-11-01 | |
US62/415,757 | 2016-11-01 | ||
US15/360,016 US10062561B2 (en) | 2016-11-01 | 2016-11-23 | High-pressure annealing and reducing wet etch rates |
US15/360,016 | 2016-11-23 | ||
PCT/US2017/057911 WO2018085072A1 (en) | 2016-11-01 | 2017-10-23 | High-pressure annealing and reducing wet etch rates |
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JP2019534566A true JP2019534566A (ja) | 2019-11-28 |
JP7048596B2 JP7048596B2 (ja) | 2022-04-05 |
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US (1) | US10062561B2 (ja) |
JP (1) | JP7048596B2 (ja) |
CN (1) | CN109923660B (ja) |
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WO (1) | WO2018085072A1 (ja) |
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US11037781B2 (en) | 2018-06-29 | 2021-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device and method for high pressure anneal |
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US20180122630A1 (en) | 2018-05-03 |
WO2018085072A1 (en) | 2018-05-11 |
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