JP2019534550A5 - - Google Patents

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Publication number
JP2019534550A5
JP2019534550A5 JP2019513837A JP2019513837A JP2019534550A5 JP 2019534550 A5 JP2019534550 A5 JP 2019534550A5 JP 2019513837 A JP2019513837 A JP 2019513837A JP 2019513837 A JP2019513837 A JP 2019513837A JP 2019534550 A5 JP2019534550 A5 JP 2019534550A5
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JP
Japan
Prior art keywords
mask
cut region
dummy gates
gate cut
region
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Ceased
Application number
JP2019513837A
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English (en)
Japanese (ja)
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JP2019534550A (ja
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Publication date
Priority claimed from US15/271,867 external-priority patent/US9997360B2/en
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Publication of JP2019534550A publication Critical patent/JP2019534550A/ja
Publication of JP2019534550A5 publication Critical patent/JP2019534550A5/ja
Ceased legal-status Critical Current

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JP2019513837A 2016-09-21 2017-08-28 FinFETにおけるレイアウトの影響の緩和 Ceased JP2019534550A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/271,867 US9997360B2 (en) 2016-09-21 2016-09-21 Method for mitigating layout effect in FINFET
US15/271,867 2016-09-21
PCT/US2017/048841 WO2018057243A1 (en) 2016-09-21 2017-08-28 Layout effect mitigation in finfet

Publications (2)

Publication Number Publication Date
JP2019534550A JP2019534550A (ja) 2019-11-28
JP2019534550A5 true JP2019534550A5 (https=) 2020-09-24

Family

ID=59791201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019513837A Ceased JP2019534550A (ja) 2016-09-21 2017-08-28 FinFETにおけるレイアウトの影響の緩和

Country Status (7)

Country Link
US (2) US9997360B2 (https=)
EP (1) EP3516696B1 (https=)
JP (1) JP2019534550A (https=)
KR (1) KR20190046884A (https=)
CN (1) CN109716529A (https=)
BR (1) BR112019004961A2 (https=)
WO (1) WO2018057243A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997360B2 (en) 2016-09-21 2018-06-12 Qualcomm Incorporated Method for mitigating layout effect in FINFET
CN111508897A (zh) * 2019-01-31 2020-08-07 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
JP7370730B2 (ja) * 2019-05-14 2023-10-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN110752152B (zh) * 2019-10-17 2021-10-15 上海华力集成电路制造有限公司 鳍式晶体管的多晶硅栅截断的工艺方法
US11842994B2 (en) 2020-04-30 2023-12-12 Taiwan Semiconductor Manufacturing Company, Ltd Semiconductor device having staggered gate-stub-size profile and method of manufacturing same
DE102020132921A1 (de) * 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. HALBLEITERVORRICHTUNG MIT GESTUFTEM GATESTUMPFGRÖßENPROFIL UND VERFAHREN ZUR HERSTELLUNG DAVON

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JPH09246406A (ja) * 1996-03-12 1997-09-19 Toshiba Corp 半導体装置とその製造方法
US6677645B2 (en) * 2002-01-31 2004-01-13 International Business Machines Corporation Body contact MOSFET
US20130309856A1 (en) 2012-05-15 2013-11-21 International Business Machines Corporation Etch resistant barrier for replacement gate integration
KR101937851B1 (ko) * 2012-06-27 2019-04-10 삼성전자 주식회사 반도체 집적 회로, 그 설계 방법 및 제조방법
US8835237B2 (en) 2012-11-07 2014-09-16 International Business Machines Corporation Robust replacement gate integration
CN103855021B (zh) * 2012-12-04 2017-04-05 中芯国际集成电路制造(上海)有限公司 一种FinFET器件的制造方法
US9263252B2 (en) 2013-01-07 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of protecting an interlayer dielectric layer and structure formed thereby
US9997617B2 (en) * 2013-03-13 2018-06-12 Qualcomm Incorporated Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods
US9153478B2 (en) * 2013-03-15 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer etching process for integrated circuit design
KR102025309B1 (ko) * 2013-08-22 2019-09-25 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9117886B2 (en) 2013-11-27 2015-08-25 United Microelectronics Corp. Method for fabricating a semiconductor device by forming and removing a dummy gate structure
US9214557B2 (en) * 2014-02-06 2015-12-15 Globalfoundries Singapore Pte. Ltd. Device with isolation buffer
US9373641B2 (en) 2014-08-19 2016-06-21 International Business Machines Corporation Methods of forming field effect transistors using a gate cut process following final gate formation
KR102197402B1 (ko) 2014-10-14 2020-12-31 삼성전자주식회사 반도체 장치 제조 방법
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US9653281B2 (en) * 2015-06-22 2017-05-16 Qualcomm Incorporated Structure and method for tunable memory cells including fin field effect transistors
US9853112B2 (en) * 2015-07-17 2017-12-26 Qualcomm Incorporated Device and method to connect gate regions separated using a gate cut
US9627474B2 (en) * 2015-09-18 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of fabricating the same
US9634138B1 (en) * 2016-08-24 2017-04-25 Qualcomm Incorporated Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
US9997360B2 (en) 2016-09-21 2018-06-12 Qualcomm Incorporated Method for mitigating layout effect in FINFET

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