JP2019534550A - ＦｉｎＦＥＴにおけるレイアウトの影響の緩和 - Google Patents

ＦｉｎＦＥＴにおけるレイアウトの影響の緩和 Download PDF

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Publication number
JP2019534550A
JP2019534550A JP2019513837A JP2019513837A JP2019534550A JP 2019534550 A JP2019534550 A JP 2019534550A JP 2019513837 A JP2019513837 A JP 2019513837A JP 2019513837 A JP2019513837 A JP 2019513837A JP 2019534550 A JP2019534550 A JP 2019534550A
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Japan
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mask
cut region
layer
gate cut
gate
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Japanese (ja)
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JP2019534550A5 (https=
Inventor
ダ・ヤン
ヤンシャン・リュウ
ジュン・ユアン
カーン・リム
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クアルコム，インコーポレイテッド
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Publication of JP2019534550A publication Critical patent/JP2019534550A/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2019513837A 2016-09-21 2017-08-28 ＦｉｎＦＥＴにおけるレイアウトの影響の緩和 Ceased JP2019534550A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/271,867 US9997360B2 (en) 2016-09-21 2016-09-21 Method for mitigating layout effect in FINFET
US15/271,867 2016-09-21
PCT/US2017/048841 WO2018057243A1 (en) 2016-09-21 2017-08-28 Layout effect mitigation in finfet

Publications (2)

Publication Number Publication Date
JP2019534550A true JP2019534550A (ja) 2019-11-28
JP2019534550A5 JP2019534550A5 (https=) 2020-09-24

Family

ID=59791201

Family Applications (1)

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JP2019513837A Ceased JP2019534550A (ja) 2016-09-21 2017-08-28 ＦｉｎＦＥＴにおけるレイアウトの影響の緩和

Country Status (7)

Country Link
US (2) US9997360B2 (https=)
EP (1) EP3516696B1 (https=)
JP (1) JP2019534550A (https=)
KR (1) KR20190046884A (https=)
CN (1) CN109716529A (https=)
BR (1) BR112019004961A2 (https=)
WO (1) WO2018057243A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997360B2 (en) 2016-09-21 2018-06-12 Qualcomm Incorporated Method for mitigating layout effect in FINFET
CN111508897A (zh) * 2019-01-31 2020-08-07 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
JP7370730B2 (ja) * 2019-05-14 2023-10-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN110752152B (zh) * 2019-10-17 2021-10-15 上海华力集成电路制造有限公司 鳍式晶体管的多晶硅栅截断的工艺方法
US11842994B2 (en) 2020-04-30 2023-12-12 Taiwan Semiconductor Manufacturing Company, Ltd Semiconductor device having staggered gate-stub-size profile and method of manufacturing same
DE102020132921A1 (de) * 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. HALBLEITERVORRICHTUNG MIT GESTUFTEM GATESTUMPFGRÖßENPROFIL UND VERFAHREN ZUR HERSTELLUNG DAVON

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246406A (ja) * 1996-03-12 1997-09-19 Toshiba Corp 半導体装置とその製造方法
JP2014010839A (ja) * 2012-06-27 2014-01-20 Samsung Electronics Co Ltd 半導体集積回路とその設計方法及び製造方法
JP2015041771A (ja) * 2013-08-22 2015-03-02 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 半導体装置及びその製造方法
US9379104B1 (en) * 2015-03-05 2016-06-28 Globalfoundries Inc. Method to make gate-to-body contact to release plasma induced charging
JP2018523232A (ja) * 2015-07-17 2018-08-16 クアルコム，インコーポレイテッド ゲートカットを使用して分離されたゲート領域を接続するためのデバイスおよび方法
JP2019525480A (ja) * 2016-08-24 2019-09-05 クアルコム，インコーポレイテッド 隣接する非対称アクティブゲート／ダミーゲート幅レイアウトを採用する電界効果トランジスタ（ｆｅｔ）デバイス

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677645B2 (en) * 2002-01-31 2004-01-13 International Business Machines Corporation Body contact MOSFET
US20130309856A1 (en) 2012-05-15 2013-11-21 International Business Machines Corporation Etch resistant barrier for replacement gate integration
US8835237B2 (en) 2012-11-07 2014-09-16 International Business Machines Corporation Robust replacement gate integration
CN103855021B (zh) * 2012-12-04 2017-04-05 中芯国际集成电路制造(上海)有限公司 一种FinFET器件的制造方法
US9263252B2 (en) 2013-01-07 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of protecting an interlayer dielectric layer and structure formed thereby
US9997617B2 (en) * 2013-03-13 2018-06-12 Qualcomm Incorporated Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods
US9153478B2 (en) * 2013-03-15 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer etching process for integrated circuit design
US9117886B2 (en) 2013-11-27 2015-08-25 United Microelectronics Corp. Method for fabricating a semiconductor device by forming and removing a dummy gate structure
US9214557B2 (en) * 2014-02-06 2015-12-15 Globalfoundries Singapore Pte. Ltd. Device with isolation buffer
US9373641B2 (en) 2014-08-19 2016-06-21 International Business Machines Corporation Methods of forming field effect transistors using a gate cut process following final gate formation
KR102197402B1 (ko) 2014-10-14 2020-12-31 삼성전자주식회사 반도체 장치 제조 방법
US9653281B2 (en) * 2015-06-22 2017-05-16 Qualcomm Incorporated Structure and method for tunable memory cells including fin field effect transistors
US9627474B2 (en) * 2015-09-18 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of fabricating the same
US9997360B2 (en) 2016-09-21 2018-06-12 Qualcomm Incorporated Method for mitigating layout effect in FINFET

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246406A (ja) * 1996-03-12 1997-09-19 Toshiba Corp 半導体装置とその製造方法
JP2014010839A (ja) * 2012-06-27 2014-01-20 Samsung Electronics Co Ltd 半導体集積回路とその設計方法及び製造方法
JP2015041771A (ja) * 2013-08-22 2015-03-02 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 半導体装置及びその製造方法
US9379104B1 (en) * 2015-03-05 2016-06-28 Globalfoundries Inc. Method to make gate-to-body contact to release plasma induced charging
JP2018523232A (ja) * 2015-07-17 2018-08-16 クアルコム，インコーポレイテッド ゲートカットを使用して分離されたゲート領域を接続するためのデバイスおよび方法
JP2019525480A (ja) * 2016-08-24 2019-09-05 クアルコム，インコーポレイテッド 隣接する非対称アクティブゲート／ダミーゲート幅レイアウトを採用する電界効果トランジスタ（ｆｅｔ）デバイス

Also Published As

Publication number Publication date
WO2018057243A1 (en) 2018-03-29
EP3516696A1 (en) 2019-07-31
US20180082846A1 (en) 2018-03-22
US10181403B2 (en) 2019-01-15
KR20190046884A (ko) 2019-05-07
CN109716529A (zh) 2019-05-03
EP3516696B1 (en) 2020-08-05
US9997360B2 (en) 2018-06-12
BR112019004961A2 (pt) 2019-07-02
US20180197743A1 (en) 2018-07-12

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