JP2019534501A5 - - Google Patents

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Publication number
JP2019534501A5
JP2019534501A5 JP2019512811A JP2019512811A JP2019534501A5 JP 2019534501 A5 JP2019534501 A5 JP 2019534501A5 JP 2019512811 A JP2019512811 A JP 2019512811A JP 2019512811 A JP2019512811 A JP 2019512811A JP 2019534501 A5 JP2019534501 A5 JP 2019534501A5
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JP
Japan
Prior art keywords
processor
power state
low power
power
state
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JP2019512811A
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English (en)
Japanese (ja)
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JP2019534501A (ja
JP6748298B2 (ja
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Priority claimed from US15/259,697 external-priority patent/US10606339B2/en
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Publication of JP2019534501A5 publication Critical patent/JP2019534501A5/ja
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Publication of JP6748298B2 publication Critical patent/JP6748298B2/ja
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JP2019512811A 2016-09-08 2017-09-07 ハードウェア制御分割スヌープディレクトリを使用するコヒーレント相互接続電力低減 Active JP6748298B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/259,697 2016-09-08
US15/259,697 US10606339B2 (en) 2016-09-08 2016-09-08 Coherent interconnect power reduction using hardware controlled split snoop directories
PCT/US2017/050450 WO2018049010A1 (en) 2016-09-08 2017-09-07 Coherent interconnect power reduction using hardware controlled split snoop directories

Publications (3)

Publication Number Publication Date
JP2019534501A JP2019534501A (ja) 2019-11-28
JP2019534501A5 true JP2019534501A5 (enExample) 2020-05-21
JP6748298B2 JP6748298B2 (ja) 2020-08-26

Family

ID=59901602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019512811A Active JP6748298B2 (ja) 2016-09-08 2017-09-07 ハードウェア制御分割スヌープディレクトリを使用するコヒーレント相互接続電力低減

Country Status (7)

Country Link
US (1) US10606339B2 (enExample)
EP (1) EP3510487B1 (enExample)
JP (1) JP6748298B2 (enExample)
KR (1) KR102132571B1 (enExample)
CN (1) CN109690502A (enExample)
BR (1) BR112019004001A8 (enExample)
WO (1) WO2018049010A1 (enExample)

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JP6772007B2 (ja) * 2016-09-12 2020-10-21 キヤノン株式会社 情報処理装置及びその制御方法、コンピュータプログラム
KR102659679B1 (ko) 2019-04-22 2024-04-19 주식회사 엘지에너지솔루션 배터리의 미분 전압 커브를 결정하기 위한 장치 및 방법과, 상기 장치를 포함하는 배터리 팩
US11354239B2 (en) * 2020-09-18 2022-06-07 Microsoft Technology Licensing, Llc Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
US11703932B2 (en) * 2021-06-24 2023-07-18 Advanced Micro Devices, Inc. Demand based probe filter initialization after low power state
KR102864772B1 (ko) * 2022-11-21 2025-09-24 연세대학교 산학협력단 근접 데이터 처리를 이용한 이종 멀티 코어 프로세서 및 시스템
US20240219988A1 (en) * 2023-01-03 2024-07-04 Advanced Micro Devices, Inc. Chiplet interconnect power state management
US20250093937A1 (en) * 2023-09-14 2025-03-20 Apple Inc. Multi-Processor Power Management Circuit
CN117931529B (zh) * 2024-03-21 2024-08-27 上海励驰半导体有限公司 启动管理方法和设备、电子设备及存储介质
US20250307146A1 (en) * 2024-03-28 2025-10-02 Intel Corporation Coherent cache fabric with reduced power mode
US20250307153A1 (en) * 2024-03-29 2025-10-02 Intel Corporation Apparatus and Method for Performance and Energy Efficient Compute

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GB2403561A (en) * 2003-07-02 2005-01-05 Advanced Risc Mach Ltd Power control within a coherent multi-processor system
US7089361B2 (en) 2003-08-07 2006-08-08 International Business Machines Corporation Dynamic allocation of shared cache directory for optimizing performance
US7752474B2 (en) 2006-09-22 2010-07-06 Apple Inc. L1 cache flush when processor is entering low power mode
CN101689106B (zh) * 2007-06-12 2013-10-09 松下电器产业株式会社 多处理器控制装置、多处理器控制方法以及多处理器控制电路
US8527709B2 (en) * 2007-07-20 2013-09-03 Intel Corporation Technique for preserving cached information during a low power mode
US20110103391A1 (en) * 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
US8392665B2 (en) * 2010-09-25 2013-03-05 Intel Corporation Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines
US8918591B2 (en) * 2010-10-29 2014-12-23 Freescale Semiconductor, Inc. Data processing system having selective invalidation of snoop requests and method therefor
US20130318308A1 (en) 2012-05-24 2013-11-28 Sonics, Inc. Scalable cache coherence for a network on a chip
US9170955B2 (en) * 2012-11-27 2015-10-27 Intel Corporation Providing extended cache replacement state information
US9317102B2 (en) 2013-01-03 2016-04-19 Apple Inc. Power control for cache structures
US9304923B2 (en) 2013-03-12 2016-04-05 Arm Limited Data coherency management
US9213643B2 (en) 2013-03-13 2015-12-15 Applied Micro Circuits Corporation Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
US9361236B2 (en) 2013-06-18 2016-06-07 Arm Limited Handling write requests for a data array
US9342134B2 (en) * 2013-09-27 2016-05-17 Intel Corporation Power consumption reduction in a computing device
US9665153B2 (en) 2014-03-21 2017-05-30 Intel Corporation Selecting a low power state based on cache flush latency determination
EP3129886B1 (en) * 2014-12-14 2019-10-02 VIA Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits
US11237965B2 (en) 2014-12-31 2022-02-01 Arteris, Inc. Configurable snoop filters for cache coherent systems
US20160314024A1 (en) * 2015-04-24 2016-10-27 Mediatek Inc. Clearance mode in a multicore processor system

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