KR102132571B1 - 하드웨어 제어형 분할된 스누프 디렉토리들을 사용한 코히어런트 인터커넥트 전력 감소 - Google Patents

하드웨어 제어형 분할된 스누프 디렉토리들을 사용한 코히어런트 인터커넥트 전력 감소 Download PDF

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KR102132571B1
KR102132571B1 KR1020197006539A KR20197006539A KR102132571B1 KR 102132571 B1 KR102132571 B1 KR 102132571B1 KR 1020197006539 A KR1020197006539 A KR 1020197006539A KR 20197006539 A KR20197006539 A KR 20197006539A KR 102132571 B1 KR102132571 B1 KR 102132571B1
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processor
snoop
divided
power
power state
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KR20190046840A (ko
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크리스토쁘 아부안
뤽 몽페뤼
필리쁘 부까르
라케쉬 쿠마르 굽타
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)
KR1020197006539A 2016-09-08 2017-09-07 하드웨어 제어형 분할된 스누프 디렉토리들을 사용한 코히어런트 인터커넥트 전력 감소 Active KR102132571B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/259,697 US10606339B2 (en) 2016-09-08 2016-09-08 Coherent interconnect power reduction using hardware controlled split snoop directories
US15/259,697 2016-09-08
PCT/US2017/050450 WO2018049010A1 (en) 2016-09-08 2017-09-07 Coherent interconnect power reduction using hardware controlled split snoop directories

Publications (2)

Publication Number Publication Date
KR20190046840A KR20190046840A (ko) 2019-05-07
KR102132571B1 true KR102132571B1 (ko) 2020-07-09

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KR1020197006539A Active KR102132571B1 (ko) 2016-09-08 2017-09-07 하드웨어 제어형 분할된 스누프 디렉토리들을 사용한 코히어런트 인터커넥트 전력 감소

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Country Link
US (1) US10606339B2 (enExample)
EP (1) EP3510487B1 (enExample)
JP (1) JP6748298B2 (enExample)
KR (1) KR102132571B1 (enExample)
CN (1) CN109690502A (enExample)
BR (1) BR112019004001A8 (enExample)
WO (1) WO2018049010A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6772007B2 (ja) * 2016-09-12 2020-10-21 キヤノン株式会社 情報処理装置及びその制御方法、コンピュータプログラム
KR102659679B1 (ko) 2019-04-22 2024-04-19 주식회사 엘지에너지솔루션 배터리의 미분 전압 커브를 결정하기 위한 장치 및 방법과, 상기 장치를 포함하는 배터리 팩
US11354239B2 (en) * 2020-09-18 2022-06-07 Microsoft Technology Licensing, Llc Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
US11703932B2 (en) * 2021-06-24 2023-07-18 Advanced Micro Devices, Inc. Demand based probe filter initialization after low power state
KR102864772B1 (ko) * 2022-11-21 2025-09-24 연세대학교 산학협력단 근접 데이터 처리를 이용한 이종 멀티 코어 프로세서 및 시스템
US20240219988A1 (en) * 2023-01-03 2024-07-04 Advanced Micro Devices, Inc. Chiplet interconnect power state management
US20250093937A1 (en) * 2023-09-14 2025-03-20 Apple Inc. Multi-Processor Power Management Circuit
CN117931529B (zh) * 2024-03-21 2024-08-27 上海励驰半导体有限公司 启动管理方法和设备、电子设备及存储介质
US20250307146A1 (en) * 2024-03-28 2025-10-02 Intel Corporation Coherent cache fabric with reduced power mode
US20250307153A1 (en) * 2024-03-29 2025-10-02 Intel Corporation Apparatus and Method for Performance and Energy Efficient Compute

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140189411A1 (en) 2013-01-03 2014-07-03 Apple Inc. Power control for cache structures
US20140281275A1 (en) 2013-03-13 2014-09-18 Applied Micro Circuits Corporation Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
US20160188471A1 (en) 2014-12-31 2016-06-30 Arteris, Inc. Configurable snoop filters for cache coherent systems
US20160314024A1 (en) 2015-04-24 2016-10-27 Mediatek Inc. Clearance mode in a multicore processor system

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2403561A (en) * 2003-07-02 2005-01-05 Advanced Risc Mach Ltd Power control within a coherent multi-processor system
US7089361B2 (en) 2003-08-07 2006-08-08 International Business Machines Corporation Dynamic allocation of shared cache directory for optimizing performance
US7752474B2 (en) 2006-09-22 2010-07-06 Apple Inc. L1 cache flush when processor is entering low power mode
US8489862B2 (en) * 2007-06-12 2013-07-16 Panasonic Corporation Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same
US8527709B2 (en) * 2007-07-20 2013-09-03 Intel Corporation Technique for preserving cached information during a low power mode
US20110103391A1 (en) * 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
US8392665B2 (en) * 2010-09-25 2013-03-05 Intel Corporation Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines
US8918591B2 (en) * 2010-10-29 2014-12-23 Freescale Semiconductor, Inc. Data processing system having selective invalidation of snoop requests and method therefor
US20130318308A1 (en) 2012-05-24 2013-11-28 Sonics, Inc. Scalable cache coherence for a network on a chip
US9170955B2 (en) * 2012-11-27 2015-10-27 Intel Corporation Providing extended cache replacement state information
US9304923B2 (en) 2013-03-12 2016-04-05 Arm Limited Data coherency management
US9361236B2 (en) 2013-06-18 2016-06-07 Arm Limited Handling write requests for a data array
US9342134B2 (en) * 2013-09-27 2016-05-17 Intel Corporation Power consumption reduction in a computing device
US9665153B2 (en) 2014-03-21 2017-05-30 Intel Corporation Selecting a low power state based on cache flush latency determination
US10698827B2 (en) * 2014-12-14 2020-06-30 Via Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140189411A1 (en) 2013-01-03 2014-07-03 Apple Inc. Power control for cache structures
US20140281275A1 (en) 2013-03-13 2014-09-18 Applied Micro Circuits Corporation Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
US20160188471A1 (en) 2014-12-31 2016-06-30 Arteris, Inc. Configurable snoop filters for cache coherent systems
US20160314024A1 (en) 2015-04-24 2016-10-27 Mediatek Inc. Clearance mode in a multicore processor system

Also Published As

Publication number Publication date
EP3510487A1 (en) 2019-07-17
EP3510487B1 (en) 2023-02-22
BR112019004001A2 (pt) 2019-05-28
BR112019004001A8 (pt) 2023-02-14
JP2019534501A (ja) 2019-11-28
WO2018049010A1 (en) 2018-03-15
CN109690502A (zh) 2019-04-26
US10606339B2 (en) 2020-03-31
KR20190046840A (ko) 2019-05-07
JP6748298B2 (ja) 2020-08-26
US20180067542A1 (en) 2018-03-08

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