BR112019004001A8 - Redução coerente de potência de interconexão utilizando diretórios de monitoramento divididos controlados por hardware - Google Patents

Redução coerente de potência de interconexão utilizando diretórios de monitoramento divididos controlados por hardware

Info

Publication number
BR112019004001A8
BR112019004001A8 BR112019004001A BR112019004001A BR112019004001A8 BR 112019004001 A8 BR112019004001 A8 BR 112019004001A8 BR 112019004001 A BR112019004001 A BR 112019004001A BR 112019004001 A BR112019004001 A BR 112019004001A BR 112019004001 A8 BR112019004001 A8 BR 112019004001A8
Authority
BR
Brazil
Prior art keywords
power
split
processor caches
power reduction
interconnection power
Prior art date
Application number
BR112019004001A
Other languages
English (en)
Other versions
BR112019004001A2 (pt
Inventor
Avoinne Christophe
Montperrus Luc
Boucard Philippe
Kumar Gupta Rakesh
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112019004001A2 publication Critical patent/BR112019004001A2/pt
Publication of BR112019004001A8 publication Critical patent/BR112019004001A8/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)

Abstract

Os aspectos incluem dispositivo de computação, aparelhos e métodos implementados pelo aparelho para implementar múltiplos diretórios de monitoramento divididos em um dispositivo de computação incluindo qualquer quantidade de processadores, qualquer quantidade de domínios de potência, e qualquer quantidade de caches de processador. Por exemplo, vários aspectos podem incluir ativar um primeiro diretório de monitoramento dividido para um primeiro domínio de potência e um segundo diretório dividido para um segundo domínio de potência, em que o primeiro domínio de potência inclui uma primeira pluralidade de caches de processador e o segundo domínio de potência inclui pelo menos uma cache de processador, determinar se todas da primeira pluralidade de caches de processador estão em um estado de baixa potência, e desativar o primeiro diretório de monitoramento dividido em resposta à determinação de que a primeira pluralidade de caches de processador está em um estado de baixa potência. Operações similares podem ser realizadas para um número N de domínios de potência e um número M de caches de processador.
BR112019004001A 2016-09-08 2017-09-07 Redução coerente de potência de interconexão utilizando diretórios de monitoramento divididos controlados por hardware BR112019004001A8 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/259,697 US10606339B2 (en) 2016-09-08 2016-09-08 Coherent interconnect power reduction using hardware controlled split snoop directories
PCT/US2017/050450 WO2018049010A1 (en) 2016-09-08 2017-09-07 Coherent interconnect power reduction using hardware controlled split snoop directories

Publications (2)

Publication Number Publication Date
BR112019004001A2 BR112019004001A2 (pt) 2019-05-28
BR112019004001A8 true BR112019004001A8 (pt) 2023-02-14

Family

ID=59901602

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112019004001A BR112019004001A8 (pt) 2016-09-08 2017-09-07 Redução coerente de potência de interconexão utilizando diretórios de monitoramento divididos controlados por hardware

Country Status (7)

Country Link
US (1) US10606339B2 (pt)
EP (1) EP3510487B1 (pt)
JP (1) JP6748298B2 (pt)
KR (1) KR102132571B1 (pt)
CN (1) CN109690502A (pt)
BR (1) BR112019004001A8 (pt)
WO (1) WO2018049010A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6772007B2 (ja) * 2016-09-12 2020-10-21 キヤノン株式会社 情報処理装置及びその制御方法、コンピュータプログラム
KR102659679B1 (ko) 2019-04-22 2024-04-19 주식회사 엘지에너지솔루션 배터리의 미분 전압 커브를 결정하기 위한 장치 및 방법과, 상기 장치를 포함하는 배터리 팩
US11354239B2 (en) * 2020-09-18 2022-06-07 Microsoft Technology Licensing, Llc Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
CN117931529B (zh) * 2024-03-21 2024-08-27 上海励驰半导体有限公司 启动管理方法和设备、电子设备及存储介质

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US7089361B2 (en) 2003-08-07 2006-08-08 International Business Machines Corporation Dynamic allocation of shared cache directory for optimizing performance
US7752474B2 (en) 2006-09-22 2010-07-06 Apple Inc. L1 cache flush when processor is entering low power mode
US8489862B2 (en) * 2007-06-12 2013-07-16 Panasonic Corporation Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same
US8527709B2 (en) * 2007-07-20 2013-09-03 Intel Corporation Technique for preserving cached information during a low power mode
US20110103391A1 (en) * 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
US8392665B2 (en) * 2010-09-25 2013-03-05 Intel Corporation Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines
US8918591B2 (en) * 2010-10-29 2014-12-23 Freescale Semiconductor, Inc. Data processing system having selective invalidation of snoop requests and method therefor
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US9170955B2 (en) * 2012-11-27 2015-10-27 Intel Corporation Providing extended cache replacement state information
US9317102B2 (en) 2013-01-03 2016-04-19 Apple Inc. Power control for cache structures
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US9213643B2 (en) 2013-03-13 2015-12-15 Applied Micro Circuits Corporation Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
US9361236B2 (en) 2013-06-18 2016-06-07 Arm Limited Handling write requests for a data array
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US20160314024A1 (en) * 2015-04-24 2016-10-27 Mediatek Inc. Clearance mode in a multicore processor system

Also Published As

Publication number Publication date
KR102132571B1 (ko) 2020-07-09
CN109690502A (zh) 2019-04-26
WO2018049010A1 (en) 2018-03-15
JP2019534501A (ja) 2019-11-28
US20180067542A1 (en) 2018-03-08
JP6748298B2 (ja) 2020-08-26
KR20190046840A (ko) 2019-05-07
EP3510487B1 (en) 2023-02-22
BR112019004001A2 (pt) 2019-05-28
EP3510487A1 (en) 2019-07-17
US10606339B2 (en) 2020-03-31

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: AS CLASSIFICACOES ANTERIORES ERAM: G06F 12/0831 , G06F 1/32

Ipc: G06F 1/3206 (2019.01), G06F 1/3234 (2019.01), G06F