JP2019523429A5 - - Google Patents

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Publication number
JP2019523429A5
JP2019523429A5 JP2019522635A JP2019522635A JP2019523429A5 JP 2019523429 A5 JP2019523429 A5 JP 2019523429A5 JP 2019522635 A JP2019522635 A JP 2019522635A JP 2019522635 A JP2019522635 A JP 2019522635A JP 2019523429 A5 JP2019523429 A5 JP 2019523429A5
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JP
Japan
Prior art keywords
signal
output
input
multiplexer
coupled
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JP2019522635A
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English (en)
Japanese (ja)
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JP7372505B2 (ja
JP2019523429A (ja
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Priority claimed from US15/211,782 external-priority patent/US10014899B2/en
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Publication of JP2019523429A publication Critical patent/JP2019523429A/ja
Publication of JP2019523429A5 publication Critical patent/JP2019523429A5/ja
Priority to JP2023082708A priority Critical patent/JP7678459B2/ja
Application granted granted Critical
Publication of JP7372505B2 publication Critical patent/JP7372505B2/ja
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JP2019522635A 2016-07-15 2017-07-17 電子回路のビルトインセルフテストのためのシステム及び方法 Active JP7372505B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023082708A JP7678459B2 (ja) 2016-07-15 2023-05-19 電子回路のビルトインセルフテストのためのシステム及び方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/211,782 2016-07-15
US15/211,782 US10014899B2 (en) 2016-07-15 2016-07-15 System and method for built-in self-test of electronic circuits
PCT/US2017/042403 WO2018014024A1 (en) 2016-07-15 2017-07-17 System and method for built-in self-test of electronic circuits

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023082708A Division JP7678459B2 (ja) 2016-07-15 2023-05-19 電子回路のビルトインセルフテストのためのシステム及び方法

Publications (3)

Publication Number Publication Date
JP2019523429A JP2019523429A (ja) 2019-08-22
JP2019523429A5 true JP2019523429A5 (enExample) 2020-08-20
JP7372505B2 JP7372505B2 (ja) 2023-11-01

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ID=60942142

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2019522635A Active JP7372505B2 (ja) 2016-07-15 2017-07-17 電子回路のビルトインセルフテストのためのシステム及び方法
JP2023082708A Active JP7678459B2 (ja) 2016-07-15 2023-05-19 電子回路のビルトインセルフテストのためのシステム及び方法

Family Applications After (1)

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JP2023082708A Active JP7678459B2 (ja) 2016-07-15 2023-05-19 電子回路のビルトインセルフテストのためのシステム及び方法

Country Status (5)

Country Link
US (1) US10014899B2 (enExample)
EP (1) EP3485285B1 (enExample)
JP (2) JP7372505B2 (enExample)
CN (1) CN109477868B (enExample)
WO (1) WO2018014024A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10014899B2 (en) * 2016-07-15 2018-07-03 Texas Instruments Incorporated System and method for built-in self-test of electronic circuits
CN112820344B (zh) * 2019-11-18 2023-04-18 华为技术有限公司 数据信号的裕量检测方法、装置及存储设备
US11619667B2 (en) * 2020-03-31 2023-04-04 Advantest Corporation Enhanced loopback diagnostic systems and methods
JP2023550646A (ja) * 2020-11-24 2023-12-04 テクトロニクス・インコーポレイテッド 高速入出力マージン試験のためのシステム、方法及び装置
KR20220083914A (ko) 2020-12-11 2022-06-21 삼성전자주식회사 내부 루프백 테스트를 수행하는 송수신기 및 그것의 동작 방법
US11835991B2 (en) * 2021-03-22 2023-12-05 Stmicroelectronics International N.V. Self-test controller, and associated method

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JP3474214B2 (ja) 1992-10-22 2003-12-08 株式会社東芝 論理回路及びこの論理回路を備えたテスト容易化回路
US6834367B2 (en) * 1999-12-22 2004-12-21 International Business Machines Corporation Built-in self test system and method for high speed clock and data recovery circuit
EP1146343B1 (en) * 2000-03-09 2005-02-23 Texas Instruments Incorporated Adapting Scan-BIST architectures for low power operation
US7490275B2 (en) 2001-02-02 2009-02-10 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7007213B2 (en) * 2001-02-15 2006-02-28 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
EP1441439A1 (en) * 2003-01-23 2004-07-28 Infineon Technologies AG Analogue amplifier with multiplexing capability
CN100547425C (zh) * 2003-02-10 2009-10-07 Nxp股份有限公司 集成电路的测试
US20050193290A1 (en) * 2004-02-25 2005-09-01 Cho James B. Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer
US7225379B2 (en) 2004-04-23 2007-05-29 Oki Electric Industry Co., Ltd. Circuit and method for testing semiconductor device
JP4811902B2 (ja) * 2004-12-24 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置のテスト方法
ATE436028T1 (de) * 2005-02-01 2009-07-15 Nxp Bv Prüfbare elektronische schaltung
US7735037B2 (en) * 2005-04-15 2010-06-08 Rambus, Inc. Generating interface adjustment signals in a device-to-device interconnection system
US7525348B1 (en) 2005-04-19 2009-04-28 National Semiconductor Corporation Differential voltage comparator
US8472883B2 (en) * 2008-09-23 2013-06-25 Intel Mobile Communications GmbH Self calibration method for radio equipment with receive and transmit circuitry
US8686736B2 (en) * 2010-11-23 2014-04-01 Infineon Technologies Ag System and method for testing a radio frequency integrated circuit
US8536888B2 (en) * 2010-12-30 2013-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Built in self test for transceiver
US8904248B2 (en) * 2012-07-10 2014-12-02 Apple Inc. Noise rejection for built-in self-test with loopback
JP2014174131A (ja) * 2013-03-13 2014-09-22 Fujitsu Semiconductor Ltd 受信回路、半導体集積回路及び試験方法
US9323633B2 (en) * 2013-03-28 2016-04-26 Stmicroelectronics, Inc. Dual master JTAG method, circuit, and system
US8803716B1 (en) * 2013-04-10 2014-08-12 Stmicroelectronics International N.V. Memoryless sliding window histogram based BIST
US9891276B2 (en) * 2015-07-28 2018-02-13 International Business Machines Corporation Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network
TWI580984B (zh) * 2015-10-27 2017-05-01 力晶科技股份有限公司 電壓校正電路及電壓校正系統
US10014899B2 (en) * 2016-07-15 2018-07-03 Texas Instruments Incorporated System and method for built-in self-test of electronic circuits

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