JP7372505B2 - 電子回路のビルトインセルフテストのためのシステム及び方法 - Google Patents
電子回路のビルトインセルフテストのためのシステム及び方法 Download PDFInfo
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- JP7372505B2 JP7372505B2 JP2019522635A JP2019522635A JP7372505B2 JP 7372505 B2 JP7372505 B2 JP 7372505B2 JP 2019522635 A JP2019522635 A JP 2019522635A JP 2019522635 A JP2019522635 A JP 2019522635A JP 7372505 B2 JP7372505 B2 JP 7372505B2
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- 238000012360 testing method Methods 0.000 title claims description 62
- 238000000034 method Methods 0.000 title description 4
- 230000004044 response Effects 0.000 claims description 28
- 230000008859 change Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 22
- 238000005259 measurement Methods 0.000 description 15
- 238000004891 communication Methods 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 101150071746 Pbsn gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3016—Delay or race condition test, e.g. race hazard test
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
- G01R31/31711—Evaluation methods, e.g. shmoo plots
Description
)場合、制御ユニット310は、(a)所定のステップを用いてテスト信号の振幅及び/又はクロックの位相を(540において)選択的に調節し、(b)このような調節された振幅及び/又は位相を備えた(及び任意選択でこのような他のオフセットを備えた)テストパターンを(510において)次の測定のためにレシーバ305に印加する。或いは、制御ユニット310が、(550において)誤りの数が所定の限界を超えると判定する場合、このような数はレシーバ305レンジの外側境界を示し得、そのため、制御ユニット310は、レポートを(560において)生成する。少なくとも一つの例において、レポートは、測定されたデータアイダイアグラム、及び(a)テストパターンの種々の段階におけるデータアイダイアグラムの形状及び形態、及び(b)それらの段階における信号振幅及び/又はクロック位相の値、を含む関連パラメータを含む。
Claims (3)
- 集積回路であって、
少なくとも第1及び第2の入力端子を有するマルチプレクサであって、
前記第1の入力端子において第1の入力信号を受信し、
前記第2の入力端子において第2の入力信号を受信し、
選択信号を受信し、
前記選択信号の第1の組み合わせに応答して前記第1の入力信号を出力し、
前記選択信号の第2の組み合わせに応答して前記第2の入力信号を出力し、
前記選択信号の第3の組み合わせに応答して前記第1及び第2の入力信号のアナログ加算を出力する、
ように結合される、前記マルチプレクサと、
前記マルチプレクサに結合されるトランスミッタであって、
前記第2の入力信号を前記マルチプレクサに提供し、
第1の制御信号に応答して前記第2の入力信号の振幅を選択的に変更する、
ように結合される、前記トランスミッタと、
前記トランスミッタに結合される位相シフタであって、第2の制御信号に応答して前記トランスミッタへのクロック信号の位相を選択的に変更するように構成され、前記クロック信号の前記位相を選択的に変えることにより第2の入力信号の位相が選択的に調節可能 である、前記位相シフタと、
前記マルチプレクサに結合される少なくとも1つのレシーバ回路であって、前記マルチ プレクサの出力に応答して少なくとも1つのローカル信号を提供するように構成される、前記少なくとも1つのレシーバ回路と、
前記少なくとも1つのレシーバ回路に結合される誤り検出器であって、前記少なくとも1つのローカル信号が前記少なくとも1つのレシーバ回路の予期される出力に合致するか否かを示すために少なくとも1つの比較信号を生成するように構成される、前記誤り検出器と、
前記誤り検出器に結合される制御ユニットであって、前記誤り検出器からの少なくとも1つの比較信号に応答して前記第1の入力信号と前記選択信号と前記第1及び第2の制御 信号とを提供するように構成される、前記制御ユニットと、
を含む、集積回路。 - 請求項1に記載の集積回路であって、
前記第2の入力信号が所定のテスト信号パターンである、集積回路。 - 請求項2に記載の集積回路であって、
前記所定のテスト信号パターンが擬似ランダムバイナリシーケンスパターンである、集積回路。
Priority Applications (1)
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JP2023082708A JP2023101589A (ja) | 2016-07-15 | 2023-05-19 | 電子回路のビルトインセルフテストのためのシステム及び方法 |
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US15/211,782 | 2016-07-15 | ||
US15/211,782 US10014899B2 (en) | 2016-07-15 | 2016-07-15 | System and method for built-in self-test of electronic circuits |
PCT/US2017/042403 WO2018014024A1 (en) | 2016-07-15 | 2017-07-17 | System and method for built-in self-test of electronic circuits |
Related Child Applications (1)
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JP2023082708A Division JP2023101589A (ja) | 2016-07-15 | 2023-05-19 | 電子回路のビルトインセルフテストのためのシステム及び方法 |
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JP2019523429A JP2019523429A (ja) | 2019-08-22 |
JP2019523429A5 JP2019523429A5 (ja) | 2020-08-20 |
JP7372505B2 true JP7372505B2 (ja) | 2023-11-01 |
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JP2019522635A Active JP7372505B2 (ja) | 2016-07-15 | 2017-07-17 | 電子回路のビルトインセルフテストのためのシステム及び方法 |
JP2023082708A Pending JP2023101589A (ja) | 2016-07-15 | 2023-05-19 | 電子回路のビルトインセルフテストのためのシステム及び方法 |
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Country Status (5)
Country | Link |
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US (1) | US10014899B2 (ja) |
EP (1) | EP3485285B1 (ja) |
JP (2) | JP7372505B2 (ja) |
CN (1) | CN109477868B (ja) |
WO (1) | WO2018014024A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US10014899B2 (en) | 2016-07-15 | 2018-07-03 | Texas Instruments Incorporated | System and method for built-in self-test of electronic circuits |
CN112820344B (zh) * | 2019-11-18 | 2023-04-18 | 华为技术有限公司 | 数据信号的裕量检测方法、装置及存储设备 |
US11619667B2 (en) * | 2020-03-31 | 2023-04-04 | Advantest Corporation | Enhanced loopback diagnostic systems and methods |
KR20220083914A (ko) | 2020-12-11 | 2022-06-21 | 삼성전자주식회사 | 내부 루프백 테스트를 수행하는 송수신기 및 그것의 동작 방법 |
US11835991B2 (en) * | 2021-03-22 | 2023-12-05 | Stmicroelectronics International N.V. | Self-test controller, and associated method |
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2016
- 2016-07-15 US US15/211,782 patent/US10014899B2/en active Active
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2017
- 2017-07-17 EP EP17828610.0A patent/EP3485285B1/en active Active
- 2017-07-17 CN CN201780043151.7A patent/CN109477868B/zh active Active
- 2017-07-17 JP JP2019522635A patent/JP7372505B2/ja active Active
- 2017-07-17 WO PCT/US2017/042403 patent/WO2018014024A1/en unknown
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- 2023-05-19 JP JP2023082708A patent/JP2023101589A/ja active Pending
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US20010016929A1 (en) | 1999-12-22 | 2001-08-23 | International Business Machines Corporation | Built-in self test system and method for high speed clock and data recovery circuit |
US20050193290A1 (en) | 2004-02-25 | 2005-09-01 | Cho James B. | Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer |
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Publication number | Publication date |
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EP3485285A4 (en) | 2019-08-21 |
EP3485285B1 (en) | 2023-05-03 |
CN109477868A (zh) | 2019-03-15 |
US20180019781A1 (en) | 2018-01-18 |
JP2019523429A (ja) | 2019-08-22 |
US10014899B2 (en) | 2018-07-03 |
WO2018014024A1 (en) | 2018-01-18 |
EP3485285A1 (en) | 2019-05-22 |
CN109477868B (zh) | 2022-04-05 |
JP2023101589A (ja) | 2023-07-21 |
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