JP2019145605A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2019145605A JP2019145605A JP2018026770A JP2018026770A JP2019145605A JP 2019145605 A JP2019145605 A JP 2019145605A JP 2018026770 A JP2018026770 A JP 2018026770A JP 2018026770 A JP2018026770 A JP 2018026770A JP 2019145605 A JP2019145605 A JP 2019145605A
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- Prior art keywords
- silicon nitride
- nitride film
- opening
- layer
- gate layer
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- 238000000034 method Methods 0.000 title claims abstract description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 176
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 174
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 13
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 8
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- 229920002120 photoresistant polymer Polymers 0.000 description 22
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- 239000007789 gas Substances 0.000 description 17
- 230000001681 protective effect Effects 0.000 description 9
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 8
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- 238000002835 absorbance Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
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- 238000002161 passivation Methods 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
Claims (7)
- 基板上に半導体積層体を成長する工程と、
第1成膜温度、10Pa以上100Pa以下の条件にて、前記半導体積層体上に第1窒化ケイ素膜をLPCVD法によって形成する工程と、
前記第1成膜温度よりも低い第2成膜温度にて、前記第1窒化ケイ素膜上に第2窒化ケイ素膜をプラズマCVD法によって形成する工程と、
フッ素系エッチングガスを用いた反応性イオンエッチングによって、前記第2窒化ケイ素膜に第2開口部を形成し、前記第1窒化ケイ素膜に前記第2開口部に重なる第1開口部を形成する工程と、
前記第1開口部内に、前記半導体積層体に接触するNiを含み、前記第2開口部の開口幅よりも狭い幅を有し前記第2窒化ケイ素膜と離間する第1ゲート層を形成する工程と、
前記第1ゲート層及び前記第2開口部を覆う第2ゲート層を形成する工程と、
を備える半導体装置の製造方法。 - 前記第1ゲート層の厚さは、前記第1窒化ケイ素膜と前記第2窒化ケイ素膜との合計厚さよりも小さい、請求項1に記載の半導体装置の製造方法。
- 前記第1成膜温度は、650℃以上であり、
前記第2成膜温度は、350℃以下である、請求項1又は2に記載の半導体装置の製造方法。 - 前記フッ素系エッチングガスに対する前記第1窒化ケイ素膜のエッチングレートは、前記第2窒化ケイ素膜のエッチングレートよりも小さい、請求項1〜3のいずれか一項に記載の半導体装置の製造方法。
- 基板上に設けられた半導体積層体と、
前記半導体積層体上に設けられ、第1開口部を有する第1窒化ケイ素膜と、
前記第1窒化ケイ素膜上に設けられ、前記第1開口部に重なり前記第1開口部よりも幅広の第2開口部を有する第2窒化ケイ素膜と、
前記第1開口部内に設けられ前記半導体積層体に接触するNiを含む第1ゲート層と、
前記第1ゲート層及び前記第2開口部を覆い、Niを含まない第2ゲート層と、
を備え、
前記第1ゲート層は、前記第2窒化ケイ素膜と離間している、
半導体装置。 - 前記第1ゲート層の厚さは、前記第1窒化ケイ素膜と前記第2窒化ケイ素膜との合計厚さよりも小さい、請求項5に記載の半導体装置。
- 前記第1窒化ケイ素膜の屈折率は、2.2以上であって、
前記第2窒化ケイ素膜の屈折率は、2.1未満である、請求項5又は6に記載の半導体装置。
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CN201910122162.5A CN110176492B (zh) | 2018-02-19 | 2019-02-19 | 半导体器件及其形成方法 |
US16/279,649 US11374098B2 (en) | 2018-02-19 | 2019-02-19 | High electron mobility transistor including a gate electrode layer spaced apart from a silicon nitride film |
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