JP2019057663A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of preventing peeling of a wiring member from a sealing resin body and improve reliability.SOLUTION: A semiconductor device comprises: an insulation substrate including a ceramic layer; a semiconductor element jointed to the insulation substrate through a joint material; a wiring member which includes a first copper layer, an Invar layer, and a second copper layer, and in which the first copper layer is jointed to the semiconductor element through the joint material; a case that surrounds the semiconductor element and the wiring member, and is fixed to the insulation substrate; and a sealing resin body that is filled into the inner side of the case, and seals the semiconductor element and the wiring member. The wiring member is a joint part with the semiconductor element, and the second copper layer is removed. The sealing resin body is a removing part of the second copper layer, and is contacted to the Invar layer.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device on which a power semiconductor element is mounted.

  In recent years, the capacity of semiconductor devices mounted with power semiconductor elements has been increasing. In order to cause a large current to flow through the power semiconductor element, it is required that the wiring members inside the apparatus also support a large current. Aluminum wire bonds have been widely used as wiring members for semiconductor elements. In order to pass a large current through the aluminum wire bond, it is necessary to increase the diameter of the wire bond or increase the number of wire bonds. In a semiconductor element, there is a limit in a region where an aluminum wire bond can be connected.

  The wiring member is bonded to the upper surface of the semiconductor element. Recently, a system in which a plate-like wiring member is joined to the upper surface of a chip of a semiconductor element using solder has been used (for example, see Patent Document 1). The plate-like wiring member is made of copper or a copper-based material. As a result, it is said that a power semiconductor device mounted with a power semiconductor element can improve long-term reliability against a high temperature environment.

JP 2008-41851 A

  In addition, in the said patent document, detailed description is not found regarding sealing resin. Silicone gel is often used as a sealing resin for power semiconductor devices because it generates low stress. One purpose of sealing the semiconductor element with silicone gel is to ensure the insulation of the semiconductor device. When the semiconductor element is sealed with silicone gel, the wiring material made of copper is easily oxidized in a high temperature environment. When copper is oxidized, peeling occurs between the wiring material and the silicone gel. From the periphery of the separated wiring member, gas enters and bubbles are generated. If the bubbles expand, it becomes difficult to ensure the insulation of the semiconductor device.

  As one of the measures for suppressing the peeling of the silicone gel, a method of applying nickel plating to the copper surface of the wiring member has been devised. In this method, it is necessary to perform a plating process on the wiring member in the manufacturing process. The present invention has been made in view of the problems of the semiconductor device as described above. That is, it is an object of the present invention to provide a semiconductor device that can ensure insulation even when used in a high temperature environment without peeling off the wiring member and the silicone gel.

  A semiconductor device according to the present invention includes an insulating substrate having a ceramic layer, a semiconductor element bonded to the insulating substrate via a bonding material, a first copper layer, an invar layer, and a second copper layer. A wiring member in which the first copper layer is bonded to the semiconductor element via a bonding material, and surrounds the semiconductor element and the wiring member, and is fixed to the insulating substrate. And a sealing resin body that is filled inside the case and seals the semiconductor element and the wiring member, and the wiring member is a joint portion with the semiconductor element, The second copper layer is removed, and the sealing resin body is in contact with the invar layer at the removed portion of the second copper layer.

  A semiconductor device according to the present invention includes an insulating substrate having a ceramic layer, a semiconductor element bonded to the insulating substrate via a bonding material, a first copper layer, an invar layer, and a second copper layer. A wiring member in which the first copper layer is bonded to the semiconductor element via a bonding material, and surrounds the semiconductor element and the wiring member, and is fixed to the insulating substrate. And a sealing resin body that is filled inside the case and seals the semiconductor element and the wiring member, and the wiring member is a joint portion with the semiconductor element, The second copper layer is removed, and the sealing resin body is in contact with the invar layer at the removed portion of the second copper layer. As a result, even when used in a high temperature environment, the wiring member on the semiconductor element is prevented from being peeled off from the sealing resin body (silicone gel), and a semiconductor device having excellent insulation reliability can be provided. It becomes like this.

1 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a first embodiment. 1 is a cross-sectional configuration diagram illustrating a main part of a semiconductor device according to a first embodiment. FIG. 3 is a first diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a second diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a third diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a fourth diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a fifth diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is a figure showing the cross-sectional structure of the semiconductor device in connection with a comparative example. 6 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a second embodiment. FIG. FIG. 6 is a cross-sectional configuration diagram illustrating a main part of a semiconductor device according to a second embodiment. FIG. 10 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a third embodiment. FIG. 10 is a cross-sectional configuration diagram illustrating a main part of a semiconductor device according to a third embodiment. FIG. 10 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a fourth embodiment. It is a figure showing the result of the continuous electricity test performed with respect to the semiconductor device actually produced.

  A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected about the same or similar component, and the size and scale of each corresponding component are independent. For example, when the same component part that is not changed is illustrated in cross-sectional views in which a part of the configuration is changed, the size and scale of the same component part may be different. In addition, the configuration of the semiconductor device actually includes a plurality of members, but for the sake of simplicity, only the portions necessary for the description are shown, and the other portions are omitted.

Embodiment 1 FIG.
Hereinafter, the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. First, the main configuration of the power semiconductor device 100 according to the first embodiment will be described with reference to FIG. The semiconductor device 100 according to the present embodiment includes a power module 101,
And a heat sink 11. The heat sink 11 and the power module 101 are joined by a joining material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 71, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3. The semiconductor element 1 and the wiring member 71 are joined by a joining material such as a solder material. One surface of the insulating substrate 3 is exposed.

  Next, the electrical connection between the power module 101 and the outside will be described. The semiconductor element 1 includes an active surface on the front surface side and a back surface on the opposite side. The back surface of the semiconductor element 1 is bonded to the wiring pattern layer of the insulating substrate 3 with a bonding material such as a solder material. On the wiring pattern layer of the insulating substrate 3, a wiring terminal member 5a serving as a main terminal is connected via a bonding material such as a solder material. The wiring terminal member 5a is integrated with the insert-molded resin case 4. The wiring terminal member 5a exposed to the outside from the resin case 4 serves as an external terminal.

  A wiring member 71 serving as a main terminal is bonded to the active surface of the semiconductor element 1 via a bonding material such as a solder material. The wiring member 71 is bent to serve as an external terminal. The wiring member 71 according to the present embodiment has a three-layer structure composed of copper layer / invar layer / copper layer. Examples of the material of the bonding wire 6 include aluminum, copper, and gold. Among these, aluminum with high bonding reliability is preferable. The semiconductor element 1 also requires wiring related to a signal for switching (signal wiring) and wiring related to control such as monitoring of temperature and current (control wiring).

  Since these wirings do not have a large amount of flowing current, they are connected to the wiring terminal member 5 b from the semiconductor element 1 through the bonding wires 6. The wiring terminal member 5b which becomes a signal terminal is integrated with the resin case 4 which is insert-molded. A portion of the wiring terminal member 5b exposed from the resin case 4 serves as an external terminal. The resin case 4 is bonded to the surface wiring pattern layer of the insulating substrate 3 with an adhesive or the like. A sealing resin body 9 is filled inside the resin case 4. The semiconductor element 1, the wiring member 71, the bonding wire 6, and the like are sealed with a sealing resin body 9 so as to cover them.

  Next, the material of each member described above will be described in detail. The semiconductor element 1 is a chip-like member on which a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is mounted. The semiconductor element 1 also includes a chip-like member on which a rectifying element such as a diode is mounted. The IGBT is an element that is driven by passing a large current through a load. The semiconductor element 1 on which the IGBT is mounted operates as a power semiconductor element.

  The semiconductor device 100 on which the power semiconductor element is mounted is a so-called power module. The semiconductor chip constituting the semiconductor element 1 is preferably formed of, for example, silicon (Si), but is not limited to silicon. For example, if the semiconductor chip of the semiconductor element 1 is formed of any material selected from the group consisting of silicon carbide (SiC), gallium nitride-based materials (for example, gallium nitride (GaN)), and diamond, preferable.

These semiconductor chips are so-called wide band gap semiconductor materials having a wider band gap than silicon. The semiconductor element 1 formed using such a wide band gap semiconductor material can be applied to an operation at a higher temperature than a silicon element such as a MOSFET. That is, the wide band gap semiconductor material is a semiconductor suitable for flowing a large current.

  The resin case 4 is integrally formed with a wiring terminal member 5a serving as a main terminal and a wiring terminal member 5b serving as a signal terminal. The resin case 4 is provided in order to prevent resin leakage when a sealing resin such as silicone gel is injected. The melting point of the resin case 4 is desirably higher than the temperature of the power module when the semiconductor element 1 operates. Materials satisfying this condition include poly p-phenylene sulfide resin (PPS), polybutylene terephthalate resin (PBT), nylon resin, and liquid crystal polymer (LCP). These materials are usually often used as cases.

  The wiring terminal member 5 is made of a metal having good conductivity. Among these, a copper material is optimal in terms of electrical resistance, workability, and cost. The entire inside of the power module 101 is sealed with a sealing resin body 9. A silicone-based soft resin is suitable for the sealing resin body 9 so that the generated stress does not increase after the resin is cured. As the silicone-based soft resin, a silicone gel having a penetration of JIS_K — 6249 and 30 to 80 is preferable. Since the sealing resin body 9 is filled in the resin case 4, it is possible to ensure internal insulation and prevent foreign matter from entering from the outside.

  The power module 101 is bonded to the heat sink 11 including the fins 11a via a bonding material in order to release heat generated when the semiconductor element 1 operates. The heat sink 11 that requires high thermal conductivity may be water-cooled or air-cooled. The heat sink 11 is preferably formed of any one selected from the group consisting of copper, aluminum, copper or an aluminum alloy. Among these, the material of the heat sink 11 is preferably aluminum or an alloy thereof that is lightweight and excellent in workability.

  The heat sink 11 joined to the power module 101 is often provided with a plurality of fins 11 a in order to improve the cooling performance of the semiconductor device 100. Since the heat sink 11 has a complicated shape, it is manufactured by die casting or extrusion. As an aluminum alloy suitable for die casting or extrusion molding, Al-Si-Cu-based ADC10 and ADC12, Al-Mg-Si-based A6061 and A6063, and the like are preferable.

FIG. 2 shows the structure of the wiring member 71 in detail. The semiconductor element 1 includes an active surface 1x on the front surface side and a back surface 1y on the opposite side of the active surface 1x. The back surface 1y of the semiconductor element 1 is bonded to the surface wiring pattern layer 3a of the insulating substrate 3 with a bonding material 2a. The semiconductor element 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor) or MOSFE.
It is a chip-like member on which a switching element 1a such as T (Metal Oxide Semiconductor Field Effect Transistor) and a rectifying element 1b such as a diode are mounted. Since the IGBT is an element that is driven by flowing a large current, the semiconductor element 1 operates as a power semiconductor element. The semiconductor device 100 on which this is mounted is a so-called power module.

A wiring member 71 serving as a main terminal is bonded to the active surface 1x of the semiconductor element 1 via a bonding material 8 such as a solder material. The plate-shaped wiring member 71 connects, as a main terminal, the upper surface (active surface 1x) of the switching element 1a and the upper surface (active surface 1x) of the rectifying element 1b. The wiring member 71 is bent to serve as an external terminal. The wiring member 71 has a three-layer structure including a copper-based wiring member 71a (first copper layer), an invar wiring member 71b (invar layer), and a copper-based wiring member 71c (second copper layer). Yes. The copper-based wiring member 71a and the copper-based wiring member 71c are made of an alloy made of copper having good electrical conductivity. The invar wiring member 71b is made of an alloy (invar) made of iron nickel (Ni 36 wt%) having a low thermal expansion coefficient.

  The semiconductor element 1 (the switching element 1 a and the rectifying element 1 b) and the wiring member 71 are joined by a joining material 8. The wiring member 71 connecting the upper surfaces of the switching element 1a and the rectifying element 1b uses CIC (Cu / Invar / Cu). A copper-based wiring member 71 a of the wiring member 71 is connected to the semiconductor element 1. The copper-based wiring member 71 c that is the uppermost layer of the wiring member 71 is removed at a portion where the semiconductor element 1 is present. That is, the copper-based wiring member 71 c is removed at the joint between the wiring member 71 and the semiconductor element 1. In this removal portion, the invar surface of the wiring member 71 is exposed, and the invar wiring member 71 b (invar layer) is in contact with the sealing resin body 9. The composition ratio of the copper layer / invar layer / copper layer is not particularly limited, but in order to reduce the difference in thermal expansion coefficient with the insulating substrate 3, it should be 1/1/1 thick. Is preferred

  That is, the wiring member 71 removes Cu (second copper layer) on the opposite surface connected to the semiconductor element on the upper surface (active surface 1x) of the semiconductor element to expose the invar surface. A method for removing the copper layer from the wiring member 71 is not particularly limited, and for example, there is a method of removing by etching. The bonding material 8 connects the semiconductor element 1 and the wiring member 71. As the bonding material 8, as in the bonding material 2 a, any one selected from the group consisting of solder, a sinterable filler containing silver as a main component, a brazing material containing silver as a main component, and a material in which copper is dispersed in tin. It is preferable that These are bonding materials having high conductivity.

In the figure, the switching element 1a and the rectifying element 1b are arranged one by one at intervals, but the present invention is not limited to this. The number of semiconductor elements 1 arranged is arbitrary. That is, only one semiconductor element 1 or three or more semiconductor elements 1 may be arranged. The semiconductor element 1 may use RC-IGBT (Reverse Conducting IGBT). In the RC-IGBT, the IGBT and the diode are contained in one semiconductor chip. The active surface 1x opposite to the side to be joined to the insulating substrate 3 of the semiconductor element 1 is partially coated with nickel-gold plating 1d.

  The insulating substrate 3 includes a front surface wiring pattern layer 3a, a ceramic layer 3b, and a back surface wiring pattern layer 3c. The front surface wiring pattern layer 3a and the back surface wiring pattern layer 3c are made of a conductive material such as copper or aluminum, or an alloy material containing them as a main component. The ceramic layer 3b of the insulating substrate 3 serves as a core material for ensuring insulation. As the ceramic layer 3b, a ceramic material such as aluminum nitride, silicon nitride, boron nitride, aluminum oxide (alumina) having excellent thermal conductivity can be used. The front surface wiring pattern layer 3a and the back surface wiring pattern layer 3c are made of a brazing material or the like and integrated with the ceramic layer 3b. The insulating substrate 3 does not need to have a planar shape as shown in the figure, and may have an opening. Moreover, you may provide the protrusion as thickness adjustment of the joining material 2a.

  Next, an example of a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. First, the method for manufacturing the semiconductor device 100 will be described with reference to FIG. The switching element 1a and the rectifying element 1b are joined to the insulating substrate 3 (surface wiring pattern layer 3a) with a gap between each other via the joining material 2a. This process is called die bonding. As the switching element 1a, for example, a semiconductor chip made of silicon and mounted with an IGBT is used. As the rectifying element 1b, for example, a semiconductor chip made of silicon and equipped with a diode is used.

In the figure, the plurality of semiconductor elements are bonded to the surface wiring pattern layer 3a of the insulating substrate 3 at intervals. Here, for example, IGBT (rated 1200V, 3
00A) has a switching element 1a having a size in plan view of 13 mm × 13 mm × 0.12 mm. For example, the rectifying element 1b on which a diode (rated 1200V, 300A) is mounted has a size of 13 mm × 10 mm × 0.12 mm in plan view.

  The insulating substrate 3 (size: 40 mm × 20 mm) includes a surface wiring pattern layer 3a made of oxygen-free copper, a ceramic layer 3b made of silicon nitride for ensuring insulation, and a back wiring pattern layer 3c made of oxygen-free copper, It consists of three layers. The thickness of the front surface wiring pattern layer 3a, the thickness of the ceramic layer 3b, and the thickness of the back surface wiring pattern layer 3c are 0.8 mm, 0.32 mm, and 0.8 mm, respectively. The front surface wiring pattern layer 3a and the ceramic layer 3b, and the ceramic layer 3b and the back surface wiring pattern layer 3c are joined with an Ag-based brazing material.

  The front surface wiring pattern layer 3a and the back surface wiring pattern layer 3c are configured by one pattern in which the circuit is not divided. The semiconductor element 1 (the switching element 1a and the rectifying element 1b) is fixed to the desired position of the insulating substrate 3 with the bonding material 2a. As the bonding material 2a, for example, a solder material not containing lead (95% by weight of tin and 5% by weight of bismuth) is used. The thickness of the bonding material 2a is, for example, 0.2 mm.

  Next, with reference to FIG. 4, the method for manufacturing the semiconductor device 100 will be further described. The wiring terminal member 5 a serving as the main terminal and the wiring terminal member 5 b serving as the signal terminal are integrally formed with the resin case 4. The resin case 4 in which the wiring terminal member 5a and the wiring terminal member 5b are integrally formed is bonded onto the surface wiring pattern layer 3a of the insulating substrate 3 using a silicone-based adhesive. The material of the resin case 4 is preferably LCP (Liquid Crystal Polymer), which has high heat resistance, in consideration of the next soldering process. The wiring terminal member 5a and the wiring terminal member 5b are both oxygen-free copper.

  Next, with reference to FIG. 5, the method for manufacturing the semiconductor device 100 will be further described. The wiring terminal member 5a and the surface wiring pattern layer 3a are bonded via the bonding material 2b. As the bonding material 2b, for example, a solder material not containing lead (99.25% by weight of tin and 0.75% by weight of copper) is used. The wiring terminal member 5 b serving as a signal terminal is integrally formed with the resin case 4. Thereafter, the switching element 1 a and the wiring terminal member 5 b are electrically connected by the bonding wire 6. The bonding wire 6 made of aluminum used here has a cross section that intersects the extending direction of, for example, a substantially circular shape having a diameter of 0.20 mm. Examples of the material of the bonding wire 6 include aluminum, copper, and gold. Among these, aluminum with high bonding reliability is preferable.

  The bonding material 2a connects the semiconductor element 1 and the insulating substrate 3 (surface wiring pattern layer 3a). The bonding material 2a includes solder, a sinterable filler containing silver as a main component, a brazing material containing silver as a main component, a material in which copper is dispersed in tin, gold tin containing gold as a main component, and gold such as gold germanium. It is preferably any one selected from the group consisting of alloys. These are bonding materials having high thermal conductivity and high conductivity. Further, the bonding material 2b connects the wiring terminal member 5a and the surface wiring pattern layer 3a. The bonding material 2b is preferably any one selected from the group consisting of solder, a sinterable filler containing silver as a main component, a brazing material containing silver as a main component, and a material in which copper is dispersed in tin. These are bonding materials having high conductivity.

Next, with reference to FIG. 6, the method for manufacturing the semiconductor device 100 will be further described. The wiring member 71 has a three-layer structure including a copper-based wiring member 71a (first copper layer), an invar wiring member 71b (invar layer), and a copper-based wiring member 71c (second copper layer). Yes. The nickel-gold plated portion of the semiconductor element 1 is electrically connected to the wiring member 71 by the bonding material 8. For the bonding material 8, for example, a solder material not containing lead (99.25% by weight of tin and 0.75% by weight of copper) is used. The thickness of the wiring member 71 is, for example, 1.0 mm. The wiring member 71 uses a three-layer structure material in which a copper layer / invar layer / copper layer has a 1/1/1 thickness.

  Thereby, the switching element 1 a and the rectifying element 1 b are electrically connected to each other via the wiring member 71. In the wiring member 71, the copper wiring member 71 c is removed from the upper part of the semiconductor element 1. At the same time, the heat sink 11 and the insulating substrate 3 (back wiring pattern layer 3 c) are bonded using the bonding material 10. The thickness of the bonding material 10 is, for example, 0.4 mm. The material of the heat sink 11 is an aluminum alloy, for example, Al-Mg-Si-based A6063. For the bonding material 10, for example, a solder material not containing lead (92.5% by weight of tin, 3.9% by weight of silver, 0.6% by weight of copper, and 3% by weight of bismuth) is used. The heat sink 11 is produced by extrusion molding.

  The bonding material 10 is formed of a material selected from the group consisting of solder, a sinterable filler mainly composed of silver, a brazing material mainly composed of silver, and a material in which copper is dispersed in tin. Is preferred. The semiconductor element 1 and the heat sink 11 are preferably applied with a method of properly joining them with these materials. Since the semiconductor element 1 is joined to the heat sink 11 with a metal material having high thermal conductivity, the thermal resistance between the semiconductor element 1 and the heat sink 11 can be reduced.

  Next, with reference to FIG. 7, the method for manufacturing the semiconductor device 100 will be further described. For the sealing resin body 9, for example, a silicone-based soft resin is used so that the generated stress does not increase after the resin is cured. The sealing resin is cast so as to be filled in the resin case 4 and cured. As the sealing resin, it is preferable to use an addition reaction type silicone gel having a penetration of 60. As a result, the power module 101 whose interior is insulated is completed. The sealing resin body 9 seals the entire module. Filling the inside of the resin case 4 with the sealing resin body 9 makes it possible to ensure internal insulation and prevent foreign material from entering.

Next, the function and effect of the semiconductor device according to this embodiment will be described with reference to a comparative example. FIG. 8 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a comparative example. A semiconductor device 100 according to the comparative example includes a power module 101, a heat sink 11, and the like. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 74, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3.

The wiring member 74 has a three-layer structure including a copper-based wiring member 74a, an invar wiring member 74b, and a copper-based wiring member 74c. In the comparative example, the copper wiring member 74c above the semiconductor element 1 remains without being removed. Inside the power module 101, heat generated on the surface of the semiconductor element 1 is released to the heat sink 11 through the bonding material 2 a, the insulating substrate 3, and the bonding material 10. However, the heat generated in the semiconductor element 1 also spreads to the wiring member 74 through the bonding material 8.

In the case of the semiconductor device of the comparative example, when the wiring member 74 reaches a temperature exceeding 130 ° C., the copper surface of the copper-based wiring member 74 c is gradually oxidized at the junction between the wiring member 74 and the semiconductor element 1. When the copper surface of the copper-based wiring member 74c is oxidized, the adhesive force at the adhesive interface between the sealing resin body 9 and the silicone gel is reduced, and peeling occurs. Once peeling occurs, water, air, etc. present in the silicone gel enter the gas as gas and form bubbles. The silicone gel of the sealing resin body 9 ensures insulation by being in close contact with the wiring member, and it is difficult to ensure insulation that is the original purpose.

  On the other hand, in the semiconductor device according to the present embodiment, the surface on the semiconductor element 1 where the wiring member 71 is in contact with the sealing resin body 9 (silicone gel) is an invar wiring member 71b. Invar does not oxidize even at high temperatures above 130 ° C. At the interface, the sealing resin body 9 (silicone gel) is not peeled off, and insulation can be ensured. Since the wiring member 71 is composed of a copper layer with good electrical conductivity and an invar layer with low thermal expansion, a large current can flow through the wiring member 71. Furthermore, the thermal expansion coefficient is close to that of the semiconductor element 1 and the insulating substrate 3, and the temperature cycle reliability is improved.

  The semiconductor device according to the present invention uses Cu / Invar / Cu (CIC), which is a Cu-based material, as a wiring member on the upper surface of the semiconductor element, and Cu on the opposite surface of the upper surface of the semiconductor element connected to the semiconductor element. Is removed to expose the Invar surface. According to the present invention, the CIC member having a small difference from the thermal expansion coefficient of the semiconductor element and the wiring substrate on which the semiconductor element is mounted is used to remove Cu on the upper surface of the semiconductor element opposite to the semiconductor element. Therefore, even when used in a high temperature environment, the semiconductor device has excellent insulation reliability because the wiring member on the semiconductor element is prevented from peeling off from the silicone gel (sealing resin) even when used in a high temperature environment. Can be provided.

  The semiconductor device according to the present embodiment is a semiconductor device in which a semiconductor element is bonded to an insulating substrate via a bonding material on the back surface opposite to the active surface of the semiconductor element, and the entire semiconductor element is covered with a sealing material. A wiring member is bonded to the active surface side of the wiring member via a bonding material, and the wiring member is composed of three layers of copper layer / invar layer / copper layer, and the portion where the semiconductor element is bonded is copper layer / invar The semiconductor device is characterized in that the two surfaces of which are in contact with the sealing material are invar.

  That is, the semiconductor device according to the present embodiment includes an insulating substrate having a ceramic layer, a semiconductor element bonded to the insulating substrate through a bonding material, a first copper layer, an invar layer, and a second layer. A wiring member in which the first copper layer is bonded to the semiconductor element via a bonding material, and surrounds the semiconductor element and the wiring member, and the insulating substrate. And a sealing resin body that fills the inside of the case and seals the semiconductor element and the wiring member, and the wiring member is connected to the semiconductor element. The second copper layer is removed at the joint, and the invar layer is in contact with the sealing resin body. As a result, the reliability of the temperature cycle is excellent, and even when used in a high temperature environment, the wiring member on the semiconductor element is suppressed from peeling from the sealing resin body (silicone gel), and the insulation reliability is excellent. A semiconductor device can be provided.

Embodiment 2. FIG.
A semiconductor device 100 according to the second embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11, and the like. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 72, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material.

  The semiconductor element 1 and the wiring member 72 are bonded with a bonding material such as a solder material. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the configuration of the wiring member. In the semiconductor device 100 according to the present embodiment, the wiring member 72 has a copper-based wiring member 72a (copper layer) on the side connected to the semiconductor element 1, and an invar wiring member 72b (invar layer) on the side in contact with the sealing resin body 9. It has a two-layer structure. For example, the total thickness of the copper layer / invar layer is 1 mm, and the thickness ratio of the copper layer / invar layer is 2/1. One surface of the insulating substrate 3 is exposed.

FIG. 10 shows in detail the structure of the wiring member 72 according to the present embodiment. The back surface 1y of the semiconductor element 1 is bonded to the insulating substrate 3 (surface wiring pattern layer 3a) with a bonding material 2a. The wiring member 72 according to the present embodiment is bonded to the active surface 1x of the semiconductor element 1 via the bonding material 8. The wiring member 72 is bent to serve as an external terminal. The wiring member 72 has a two-layer structure including a copper-based wiring member 72a (copper layer) and an invar wiring member 72b (invar layer). The copper-based wiring member 72a is made of an alloy made of copper having good electrical conductivity. The invar wiring member 72b is made of an alloy (invar) made of iron nickel (Ni 36% by weight) having a low thermal expansion coefficient. The wiring member 72 serving as a main terminal connects the upper surface of the switching element 1a and the upper surface of the rectifying element 1b.

  The semiconductor element 1 and the wiring member 72 are joined by a joining material 8. The sealing resin body 9 uses a silicone gel having a penetration of 60. As in the first embodiment, the wiring member 72 on the semiconductor element 1 has an invar wiring member 72b at a portion in contact with the sealing resin body 9. Therefore, even when the semiconductor element 1 generates heat during operation and the wiring member 72 becomes high temperature, the insulation can be ensured without peeling off the interface. In the semiconductor device according to the present embodiment, a wiring member is bonded to the active surface side of the semiconductor element via a bonding material, and the wiring member is composed of two layers of copper layer / invar layer, and the sealing The surface in contact with the resin is invar.

  That is, the semiconductor device according to the present embodiment includes an insulating substrate having a ceramic layer, a semiconductor element bonded to the insulating substrate through a bonding material, a copper layer, and an invar layer. A wiring member in which the copper layer is bonded to the semiconductor element via a bonding material, a case that surrounds the semiconductor element and the wiring member, and is fixed to the insulating substrate, and an inner side of the case And a sealing resin body that seals the semiconductor element and the wiring member, and the sealing resin body is in contact with an invar layer of the wiring member It is what. As a result, the reliability of the temperature cycle is excellent, and even when used in a high temperature environment, the wiring member on the semiconductor element is suppressed from peeling from the sealing resin body (silicone gel), and the insulation reliability is excellent. A semiconductor device can be provided.

Embodiment 3 FIG.
A semiconductor device 100 according to the third embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11, and the like. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 73, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3.

The semiconductor element 1 and the wiring member 73 are bonded with a bonding material such as a solder material. The semiconductor device 100 according to the present embodiment differs from the semiconductor device 100 according to the first embodiment in the configuration of the wiring member. In the semiconductor device according to the present embodiment, the wiring member 73 is composed of a single layer of copper (or copper-based alloy). The wiring member 73 is bonded to the semiconductor element 1 via the bonding material 8. On the opposite side (upper side) of the wiring member 73 from the semiconductor element 1, a plate-like metal plate 13 (invar member) is fixed via a bonding material. One surface of the insulating substrate 3 is exposed.

  FIG. 12 shows in detail the structure of the wiring member 73 according to the present embodiment. The back surface 1y of the semiconductor element 1 is bonded to the insulating substrate 3 (surface wiring pattern layer 3a) with a bonding material 2a. The wiring member 73 serving as the main terminal is bonded to the active surface 1 x of the semiconductor element 1 via the bonding material 8. The wiring member 73 is bent to serve as an external terminal. The wiring member 73 has a single-layer structure made of an alloy made of copper having good electrical conductivity. The wiring member 73 connects the upper surface of the switching element 1a and the upper surface of the rectifying element 1b. The bonding material 12 bonds the metal plate 13 and the wiring member 73. The material of the metal plate 13 is invar.

  As in the first and second embodiments, a wiring member 73 is fixed on the semiconductor element 1 with a bonding material 8. Since the metal plate 13 (invar member) made of invar on the wiring member 73 is in contact with the silicone gel of the sealing resin body 9, even when the semiconductor element 1 generates heat during operation and becomes high temperature, the interface remains. Insulating properties can be ensured without peeling. The bonding material 12 includes solder, a sinter filler mainly composed of silver, a brazing material mainly composed of silver, a material in which copper is dispersed in tin, gold tin mainly composed of gold, and gold such as gold germanium. It is preferably any one selected from the group consisting of alloys.

  In the semiconductor device according to the present embodiment, a wiring member is bonded to the active surface side of the semiconductor element via a bonding material, and the wiring member is formed of a single layer of copper. A metal plate made of Invar is bonded to the side opposite to the surface to be connected.

  That is, the semiconductor device according to this embodiment is bonded to the semiconductor element through an insulating substrate having a ceramic layer, a semiconductor element bonded to the insulating substrate through a bonding material, and a bonding material. A copper wiring member, an invar member bonded to the wiring member via a bonding material, a case surrounding the semiconductor element and the wiring member, and being fixed to the insulating substrate; A sealing resin body that fills the inside of the case and seals the semiconductor element and the wiring member, and the invar member is disposed at a joint portion between the wiring member and the semiconductor element. The sealing resin body is in contact with an invar member disposed at a joint portion between the wiring member and the semiconductor element. As a result, the reliability of the temperature cycle is excellent, and even when used in a high temperature environment, the wiring member on the semiconductor element is suppressed from peeling from the sealing resin body (silicone gel), and the insulation reliability is excellent. A semiconductor device can be provided.

Embodiment 4 FIG.
A semiconductor device 100 according to the fourth embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11, and the like. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 71, and the like.

The wiring member 71 has a three-layer structure including a copper-based wiring member 71a (first copper layer), an invar wiring member 71b (invar layer), and a copper-based wiring member 71c (second copper layer). Yes. The copper-based wiring member 71a and the copper-based wiring member 71c are made of an alloy made of copper having good electrical conductivity. The invar wiring member 71b is made of an alloy (invar) made of iron nickel (Ni 36 wt%) having a low thermal expansion coefficient.

  The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3. The resin case 4 is fixed on the heat sink 11 with an adhesive. The wiring terminal member 5a is a bonding material and is bonded to the insulating substrate 3 (surface wiring pattern layer 3a). The semiconductor device 100 according to the present embodiment is different in the configuration of the resin case 4 from the semiconductor device 100 according to the first embodiment. In the resin case 4 according to the present embodiment, only the wiring terminal member 5b is integrally formed.

  Even in the semiconductor device according to the present embodiment, the temperature cycle reliability is excellent, and even when used in a high temperature environment, the wiring member on the semiconductor element is suppressed from being peeled off from the silicone gel as the sealing resin. A semiconductor device with excellent reliability can be provided. The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  Next, results of actual evaluation of the semiconductor device 100 according to the present embodiment will be described. The semiconductor device 100 manufactured in Embodiment 1 is referred to as Example 1. The semiconductor device 100 manufactured in Embodiment 2 is referred to as Example 2. The semiconductor device 100 manufactured in Embodiment 3 is referred to as Example 3. The semiconductor device shown in FIG. 8 is used as a comparative example. In the comparative example, the thickness of the wiring member 74 was 0.64 mm.

  In the continuous energization test, a gate voltage of 15 V was applied to the switching element 1a (IGBT), and a constant current value (200 A in this case) was passed. The temperature of the switching element 1a was 150 ° C. and became a steady state. A continuous energization test was conducted to maintain this state for a specified time. The continuous energization test was carried out for up to 300 hours, and at that time, it was confirmed whether or not peeling occurred in the silicone resin sealing resin body 9.

  FIG. 14 shows the results of the continuous energization test. In the continuous energization test performed this time, energization was performed for up to 300 hours, and at that time, it was evaluated whether or not peeling occurred in the sealing resin body 9 made of silicone gel. In the semiconductor device of the comparative example, the sealing resin body 9 peeled off from the wiring member 74 in 150 hours, and bubbles were generated. On the other hand, in the semiconductor device of Example 1 to the semiconductor device of Example 3, peeling of the sealing resin body 9 and generation of bubbles were not confirmed. As a result, it was possible to verify that the semiconductor device according to the present embodiment has sufficient insulation.

  In the above description, the embodiment of the present invention has been described. However, the present invention is not limited to the above-described embodiment, and various processing changes can be made. Also, within the scope of the present invention, the present invention can be freely combined with each other, or each embodiment can be appropriately modified or omitted.

DESCRIPTION OF SYMBOLS 1 Semiconductor element, 1a switching element, 1b rectifier, 1x active surface, 1y back surface, 2a bonding material, 2b bonding material, 3 insulating substrate, 3a surface wiring pattern layer, 3b ceramic layer, 3c back wiring pattern layer, 4 resin Case 5 Wiring terminal member 5a Wiring terminal member 5b Wiring terminal member 6 Bonding wire 8 Bonding material 9 Sealing resin body 10 Bonding material 11 Heat sink 11a Fin 12 Bonding material 13 Metal plate 71 Wiring member, 71a Copper wiring member, 71b Invar wiring member, 71c Copper wiring member, 72 Wiring member, 72a Copper wiring member, 72b Invar wiring member, 73 Wiring member, 74 Wiring member, 74a Copper wiring member, 74b Invar wiring member, 74c
Copper-based wiring member, 100 semiconductor device, 101 power module

Embodiment 1 FIG.
Referring to FIG, with the semiconductor device relating to the first embodiment will be described. First, the main configuration of the power semiconductor device 100 according to the first embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11 , and the like. The heat sink 11 and the power module 101 are joined by a joining material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 71, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3. The semiconductor element 1 and the wiring member 71 are joined by a joining material such as a solder material. One surface of the insulating substrate 3 is exposed.

Next, the function and effect of the semiconductor device according to this embodiment will be described with reference to a comparative example. FIG. 8 is a diagram illustrating a cross-sectional structure of a semiconductor device according to a comparative example. A semiconductor device 100 according to the comparative example includes a power module 101, a heat sink 11 , and the like. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 74, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3.

Embodiment 2. FIG.
A semiconductor device 100 according to the second embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11 , and the like. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 72, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material.

Embodiment 3 FIG.
A semiconductor device 100 according to the third embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11 , and the like. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 73, and the like. The insulating substrate 3 has a three-layer structure including a wiring pattern layer / ceramic layer / wiring pattern layer. Insulation between the semiconductor element 1 and the heat sink 11 is ensured by a ceramic layer of the insulating substrate 3.

Embodiment 4 FIG.
A semiconductor device 100 according to the fourth embodiment will be described with reference to FIG. A semiconductor device 100 according to the present embodiment includes a power module 101, a heat sink 11 , and the like. The heat sink 11 is bonded to the power module 101 with a bonding material such as a solder material. The power module 101 includes a semiconductor element 1, an insulating substrate 3, a resin case 4, a wiring terminal member 5a, a wiring terminal member 5b, a bonding wire 6, a sealing resin body 9, a wiring member 71, and the like.

Claims (7)

An insulating substrate having a ceramic layer;
A semiconductor element bonded to the insulating substrate via a bonding material;
A wiring member having a first copper layer, an invar layer, and a second copper layer, wherein the first copper layer is bonded to the semiconductor element via a bonding material;
A case surrounding the semiconductor element and the wiring member and fixed to the insulating substrate;
A sealing resin body filled inside the case and sealing the semiconductor element and the wiring member;
In the wiring member, the second copper layer is removed at the junction with the semiconductor element,
The sealing resin body is in contact with the invar layer at the removal portion of the second copper layer. An insulating substrate having a ceramic layer;
A semiconductor element bonded to the insulating substrate via a bonding material;
A wiring member having a copper layer and an invar layer, wherein the copper layer is bonded to the semiconductor element via a bonding material;
A case surrounding the semiconductor element and the wiring member and fixed to the insulating substrate;
A sealing resin body filled inside the case and sealing the semiconductor element and the wiring member;
The semiconductor device, wherein the sealing resin body is in contact with an invar layer of the wiring member. An insulating substrate having a ceramic layer;
A semiconductor element bonded to the insulating substrate via a bonding material;
A copper wiring member bonded to the semiconductor element via a bonding material;
An invar member joined to the wiring member via a joining material;
A case surrounding the semiconductor element and the wiring member and fixed to the insulating substrate;
A sealing resin body filled inside the case and sealing the semiconductor element and the wiring member;
The invar member is disposed at a joint portion between the wiring member and the semiconductor element,
The semiconductor device, wherein the sealing resin body is in contact with an invar member disposed at the joint.   The semiconductor device according to claim 1, wherein the sealing resin body is made of silicone gel.   The semiconductor device according to claim 1, wherein the semiconductor element includes a switching element and a rectifying element.   The semiconductor device according to claim 5, wherein the switching element and the rectifying element are connected by the wiring member.   The semiconductor device according to claim 1, wherein the insulating substrate is bonded to a heat sink via a bonding material.

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