JP4171355B2 - Molded power device - Google Patents

Molded power device Download PDF

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Publication number
JP4171355B2
JP4171355B2 JP2003178147A JP2003178147A JP4171355B2 JP 4171355 B2 JP4171355 B2 JP 4171355B2 JP 2003178147 A JP2003178147 A JP 2003178147A JP 2003178147 A JP2003178147 A JP 2003178147A JP 4171355 B2 JP4171355 B2 JP 4171355B2
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Japan
Prior art keywords
metal layer
layer
solder
metal
stress
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Expired - Fee Related
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JP2003178147A
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Japanese (ja)
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JP2005019447A (en
Inventor
尚彦 平野
信之 加藤
孝紀 手嶋
善次 坂本
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Denso Corp
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Denso Corp
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Priority to JP2003178147A priority Critical patent/JP4171355B2/en
Priority to US10/859,130 priority patent/US7193326B2/en
Priority to DE102004030056.9A priority patent/DE102004030056B4/en
Priority to CNB2004100616490A priority patent/CN100353541C/en
Publication of JP2005019447A publication Critical patent/JP2005019447A/en
Priority to US11/702,498 priority patent/US7468318B2/en
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Publication of JP4171355B2 publication Critical patent/JP4171355B2/en
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Description

【０００１】
【発明の属する技術分野】
本発明は、絶縁ゲート型バイポーラトランジスタ（以下ＩＧＢＴと記す）などの半導体素子を備える半導体チップを樹脂モールドしたモールド型半導体装置に関するものである。
【０００２】
【従来の技術】
従来、半導体素子が形成された半導体チップを樹脂にて封止した半導体パッケージが提案されている（特許文献１参照）。図５に、この従来の半導体パッケージ３６を示す。
【０００３】
半導体パッケージ３６は、半導体基板上にＩＧＢＴを備えた半導体チップ３７と、ＩＧＢＴのコレクタ電極に接続される下側ヒートシンク３８と、ＩＧＢＴのエミッタ電極に接続される上側ヒートシンク３９と、半導体装置３７の上面に設置された内部ヒートシンク４０とを備えて構成されている。各部材は、はんだ４１を介して電気的に接続されている。また、半導体チップ３７のゲート電極とリードフレーム４２とが、ゲートワイヤ４３を介して接続されている。そして、下側および上側ヒートシンク３８、３９のそれぞれの片面とリードフレーム４２の一部が露出するように樹脂４４にて封止され、半導体パッケージ３６が形成されている。
【０００４】
【特許文献１】
特開２００３−１１００６４号公報
【０００５】
【発明が解決しようとする課題】
上述した半導体パッケージ３６は、各部材を型内に設置したのち、溶かした樹脂４４をその型に流し込むことで形成される。このとき、樹脂４４が１８０℃とされることから、樹脂４４の熱により、半導体パッケージ３６を構成する各部材が高温になる。このとき、各部材の線膨張係数の差によって応力が発生するが、各部材を接合しているはんだ４１によりその応力が吸収される。
【０００６】
しかしながら、線膨張係数の差によって発生した応力が大きい場合、はんだ４１がその応力を吸収しきれなくなり、この応力がＩＧＢＴのエミッタ電極やＩＧＢＴが形成された半導体基板に印加されることになる。そして、エミッタ電極や半導体基板がこの応力を受けると、エミッタ電極の電極材料となるＡｌ層にクラックが入り、エミッタ電極が半導体基板からはく離するという問題が生じる。このような場合、ＩＧＢＴが動作しなくなったり、動作したとしても、剥離箇所でのギャップにより熱伝導が良好に行われなくなり、放出されるはずの熱がＩＧＢＴから放出されず、ＩＧＢＴが破壊されたりするという問題も生じる。
【０００７】
また、当該半導体パッケージ３６の実際の使用時においては、半導体素子の動作によって高温になったり、使用雰囲気の温度変動によって低温にさらされたりするため、当該半導体パッケージ３６には大きな熱サイクルが印加される。この熱サイクルによっても同様に電極部には応力、あるいは歪みが生じ、前述と同様、電極の剥離、ひいてはＩＧＢＴの動作不良や破壊に至るという問題も懸念される。
【０００８】
また、近年では、鉛フリーはんだなどの硬い材質のはんだが用いられるようになっている。このような硬いはんだを使用した場合、上記した問題がより生じ易くなる。
【０００９】
本発明は上記点に鑑みて、さまざまな熱変化によって生じる応力により半導体素子が破壊されることを防止できるモールド型半導体装置を提供することを目的とする。
【００１０】
【課題を解決するための手段】
上記目的を達成するべく、本発明者らは、モールド型パワーデバイス（モールド型半導体装置）における半導体チップの電極材料と、この電極材料に接続されるはんだの材料との関係に着目した。その結果、半導体チップの電極材料とはんだの材料それぞれの降伏応力の関係において、はんだの材料の方が半導体チップの電極材料よりも降伏応力が小さくなるようにすることで、熱サイクルによって生じる応力をはんだによって吸収でき、電極材料にクラックが生じることを防止できるという効果を得られることが確認された。
【００１１】
より詳しくは、半導体チップの電極材料が多層構造で構成される場合、はんだの材料の降伏応力が好ましくは多層構造を構成する各層の電極材料よりも小さく、少なくともの半導体チップに接続される下層側の電極材料よりも小さくなっていれば、上記した効果を得られることが分かった。
【００１２】
また、半導体チップの電極材料には様々な種類があり、その種類毎に降伏応力が異なるが、半導体チップの電極材料として選択されたものの降伏応力に対して、はんだの材料の降伏応力が小さければ、上記した効果が得られることも確認している。すなわち、半導体チップの電極材料として、例えばＡｌ層とＮｉ層とＡｕ層という３層構造が採用された場合、半導体チップに直接接続される最下層がＡｌ層となる。このため、比較的降伏応力が小さいＡｌ層よりも更にはんだの材料の降伏応力が小さくなっていることが要求される。また、半導体チップの電極材料として、例えばＣｕ層とＮｉ層とＡｕ層という３層構造とされた場合、半導体チップに直接接続される最下層がＣｕ層となる。この場合、比較的降伏応力が大きなＣｕ層よりもはんだの材料の降伏応力が小さくなっていれば良いため、はんだの材料の選択肢が広がることになる。
【００１３】
なお、ここでいう降伏応力とは、降伏現象、つまり、材料に負荷される応力が弾性限界を超えてある値に達すると応力の増加がほとんどないまま急激に塑性歪みが発生するという現象を引き起こすのに必要な応力を指す。一般的に、降伏に伴い応力が極大を示す場合には、極大点の応力が降伏応力とされるが、極大が明瞭に現われないような場合、０．２％の永久歪みを生じる応力（０．２％耐力）が実用的に降伏応力として扱われる。本明細書中においては、はんだや電極材料等の金属が明瞭に極大が現われない場合の一例であることから、０．２％耐力が降伏応力と定義されるものとして説明している。
【００１４】
以上のような検討結果に基づき、請求項１に記載の発明では、半導体素子が形成された半導体チップ（１）の表面に金属層（１３）およびＰｂフリーはんだ（１４）を介して金属部材（２４）が接合されてなるモールド型パワーデバイスにおいて、Ｐｂフリーはんだの降伏応力を、金属層の降伏応力よりも小さくしたことを特徴としている。
【００１５】
このように、金属層よりも降伏応力が小さいはんだ材料で金属層に接続されるＰｂフリーはんだを構成することで、熱サイクルによって生じる応力をＰｂフリーはんだによって吸収でき、電極材料にクラックが生じることを防止できる。請求項１に示すように、ＰｂフリーはんだをＳｎ−Ｃｕ−Ｎｉの３元系のはんだ材料で構成すれば、金属層よりも降伏応力を小さくすることが可能となる。
【００１６】
請求項１に記載の発明では、金属層は、半導体素子の表面に形成され、半導体素子と電気的接続がなされる第１金属層（１３ａ）を有しており、Ｐｂフリーはんだの降伏応力を、少なくとも第１金属層の降伏応力よりも小さくしたことを特徴としている。このように、Ｐｂフリーはんだの降伏応力が半導体素子と電気的接続がなされる第１金属層の金属材料の降伏応力よりも小さくなっていれば、上記の効果を得ることができる。
【００１７】
請求項１に示すように、金属層は、第１、第２金属層を含む多層金属層で構成され、第１金属層はＡｌを含む金属材料で、第２金属層はＮｉを含む金属材料で構成される。この場合にも、Ｐｂフリーはんだの降伏応力が第１金属層よりも小さければ良い。
【００１８】
請求項１に記載の発明では、Ａｌ層の厚みは、少なくとも２μｍとされていることを特徴としている。このように、Ａｌ層の厚みを２μｍ以上とすることにより、応力による歪みの影響により半導体基板自体に亀裂が生じることを防止することができる。
【００２０】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。
【００２１】
【発明の実施の形態】
（第１実施形態）
図１は、本発明の一実施形態が適用された半導体チップ１の断面構造を示す図である。また、図２は、半導体チップ１が樹脂モールドされたモールド型パワーデバイスの断面構造を示す図である。以下、これらの図に基づいて半導体チップ１およびモールド型パワーデバイスの構成について説明する。
【００２２】
半導体チップ１は、ｐ+型基板２の主表面上にｎ-型ドリフト層３を形成した半導体基板を用いて形成されたものであり、半導体チップ１は、セル部と、セル部の外周に形成された外周耐圧部とが備えられた構成となっている。
【００２３】
セル部には、多数のＩＧＢＴが形成されている。ｎ-型ドリフト層３の表層部にはｐ型ベース層４が形成され、ｐ型ベース層４の表層部にはｎ+型ソース層６が形成されている。これら、ｎ+型ソース層６とｐ型ベース層４とを貫通してｎ-型ドリフト層３に達するようにトレンチ７が形成され、このトレンチ７の内壁表面にゲート絶縁膜８とゲート層９とが順に形成され、これらトレンチ７、ゲート絶縁膜８、ゲート層９からなるトレンチゲート構造が構成されている。また、ｎ+型ソース層６の一部とトレンチゲート構造とが絶縁膜１２ａにて覆われている。ｐ+型基板２の裏面には、当該裏面と接するようにコレクタ電極１８が形成されている。
【００２４】
さらに、ＩＧＢＴの表面にエミッタ電極１３が形成されている。このエミッタ電極１３は、例えばＡｌ−Ｓｉ−Ｃｕ等のＡｌを主成分とするＡｌ合金からなる第１金属層１３ａと、Ｎｉからなる第２金属層１３ｂと、Ａｕからなる第３金属層１３ｃとを有した多層金属層から構成されている。このエミッタ電極１３における第３金属層１３ｃの表面にＰｂフリーのはんだ１４が接続された構成となっている。なお、図１においてエミッタ電極１３は、便宜上はんだ１４を溶融する前の状態で示している。
【００２５】
第１金属層１３ａは、複数のトレンチゲート構造上にまたがるように形成され、ｐ型ベース層４とｎ+型ソース層６に接するように形成され、多数のＩＧＢＴを共通に接続している。この第１金属層１３ａは、例えばスパッタリングにより形成され、膜厚が約２μｍ以上とされている。これは、第１金属層１３ａが２μｍ未満になると、応力による歪みの影響が第１金属層１３ａではなく半導体基板そのものに作用してしまうからである。このため、応力による歪みの影響によって半導体基板自体に亀裂が生じたりすることを防止するために、第１金属膜１３ａを上記の膜厚に設定している。第１金属層１３ａは、上述したようにＡｌ合金で構成されており、材質としての降伏応力がはんだ１４よりも高いものとなっている。
【００２６】
第２金属層１３ｂは、第１金属層１３ａを構成する金属と第３金属層１３ｃの双方と接合性が良好なＮｉで構成され、例えば、湿式プロセス、具体的には湿式無電解メッキにより５μｍ程度の膜厚で形成されている。この第２金属層１３ｂを構成するＮｉは、はんだ１４と比べて硬い材料であり、その降伏応力もはんだ１４よりも高いものとなっている。
【００２７】
第３金属層１３ｃは、Ｎｉの酸化を抑制してはんだ１４の濡れ性が良好となるように、例えばめっき形成されたＡｕで構成されている。この第３金属層１３ｃは、例えば０．１μｍ程度の膜厚とされているが、はんだ１４が溶融してはんだのＳｎと第２金属層１３ｂのＮｉが合金層を形成する際に散逸してしまい、ほとんど厚みが残らない場合もある。この第３金属層１３ｃを構成するＡｕは、柔らかい材料であるが、第１、第２金属層１３ａ、１３ｂと比べて非常に薄く、またはんだ溶融後にはほとんど層状に存在していないため、線膨張係数の相違に基づいて生じる応力による歪みの影響を考える上では、考慮に入れる必要はない。
【００２８】
はんだ１４は、Ｓｎ−Ｃｕ−Ｎｉの３元系はんだ材で構成されており、その組成は、例えば、Ｃｕが０．５〜２．０重量％程度、Ｎｉが０．０５〜０．１重量％程度、Ｓｎが残部、および微量な混入成分からなっている。このような組成比で構成されたはんだ１４は、降伏応力が小さく、具体的には第１金属層１３ａよりも小さくなる。
【００２９】
図３に、素子電極材となる第１金属層１３ａの材料と本実施形態に示されるはんだ１４および従来の代表的なＰｂフリーはんだ材それぞれの温度（℃）と降伏応力［ＭＰａ］との関係を示す。ただし、この図は、各材料を同一の形態で、−４０〜１５０℃の温度域において、比較評価した一例である。サンプル形状は一般的な引張試験やねじり試験に用いられる形状等を参照すればよい。なお、ここでいう従来の代表的なＰｂフリーはんだ材とは、Ｓｎ−Ａｇ−Ｃｕの３元系はんだ材を指している。
【００３０】
この図から分かるように、第１金属層１３ａの材料とはんだ１４の材料それぞれの降伏応力の関係は、モールド型パワーデバイスが使用され得るあらゆる温度域において、第１金属層１３ａの方がはんだ１４よりも大きくなっている。本実施形態では、このような材質を用いてはんだ１４を形成している。
【００３１】
このような材質を用いてはんだ１４を形成した場合に、半導体基板表面近傍でどの程度の大きさのせん断応力が発生するかを調べてみた。具体的には、第１金属層１３ａとしてＡｌ−Ｓｉ−Ｃｕを用い、モールド型パワーデバイスが使用され得る温度域において第１金属層１３ａよりも降伏応力が小さくなるＳｎ−Ｃｕ−Ｎｉの３元系はんだ材ではんだ１４を形成した場合と、モールド型パワーデバイスが使用され得る温度域の一部において第１金属層１３ａよりも降伏応力が小さくなるＳｎ−Ａｇ−Ｃｕの３元系はんだ材ではんだ１４を形成した場合、それぞれで半導体基板表面近傍で生じるせん断応力を比較してみた。その結果を図４に示す。
【００３２】
この図に示されるように、Ｓｎ−Ｃｕ−Ｎｉの３元系はんだ材ではんだ１４を形成した場合には、Ｓｎ−Ａｇ−Ｃｕの３元系はんだ材を用いた場合と比べて、せん断応力が小さくなっていることが分かる。このように、本実施形態では、第１金属層１３ａとしてＡｌ合金を用いた場合において、モールド型デバイスが使用され得る温度域において第１金属層１３ａよりも降伏応力が小さくなるＳｎ−Ｃｕ−Ｎｉの３元系はんだ材ではんだ１４を形成している。このため、半導体基板表面近傍に生じるせん断応力も小さなものとなっている。
【００３３】
一方、外周耐圧部には、ｎ-型ドリフト層３の表層部に形成されたｐ型層５と、ＬＯＣＯＳ酸化膜１１および絶縁膜１２ｂを介して、ｐ型層５の上に形成されたフィールドプレートとしての第１の電極１５とが備えられている。また、ｎ-型ドリフト層３の表層部に形成されたｎ+型層１０と、このｎ+型層１０と接するように形成された最外周リングとしての第２の電極１６が備えられている。これら第１、第２の電極１５、１６により、半導体チップ１にサージが印加されたときにＩＧＢＴ内部に発生する電界集中を緩和させ、電界強度を低下させられるようになっている。そして、第１、第２の電極１５、１６を覆うパッシベーション膜１７が形成され、外周耐圧部の表面が保護されている。
【００３４】
このように構成された半導体チップ１が樹脂部２０にて封止されて、図２に示す半導体パッケージ２１が形成されている。
【００３５】
図２に示されるように、半導体パッケージ２１は、半導体チップ１と共に、下側ヒートシンク２２、上側ヒートシンク２３、内部ヒートシンク２４、ゲートワイヤ２５およびリード端子２６が樹脂部２０に封止された構成となっている。半導体チップ１に形成されたＩＧＢＴのゲート電極パッドとリード端子２６とがゲートワイヤ２５を介してワイヤボンディングされ、リード端子２６の一部が樹脂部２０から露出させられている。これにより、リード端子２６を介して、外部からＩＧＢＴにゲート駆動電圧を印加できるようになっている。なお、ゲート電極パッドも、エミッタ電極部１３と同様、下層側からＡｌ合金層、Ｎｉメッキ層、Ａｕメッキ層からなり、各トレンチゲート構造のゲート層９に接続している。Ａｕ層は上記の如く約０．１μｍ（０．２μｍ以下）であり、Ａｌワイヤからなるゲートワイヤ２５とのボンディング性も良好である。
【００３６】
また、下側ヒートシンク２２の上面と半導体チップ１の下面との間がはんだ２７により、半導体チップ１の上面と内部ヒートシンク２４の下面との間がはんだ１４により、さらに、内部ヒートシンク２４の上面と上側ヒートシンク２３の下面との間がはんだ２８により、それぞれ電気的に接続されている。このため、半導体チップ１に形成されたＩＧＢＴのエミッタ電極１３は内部ヒートシンク２４および上側ヒートシンク２３を介して、また、ＩＧＢＴのコレクタ電極１８は下側ヒートシンク２２を介して外部と電気的に接続できるようになっている。
【００３７】
下側および上側ヒートシンク２２、２３は、それぞれＩＧＢＴのコレクタ電極１８およびエミッタ電極１３を通じて伝わってくる熱を逃がすと共に、ＩＧＢＴの電流経路を構成するものであり、熱伝導性が良く、電気抵抗が低いＣｕなどで構成されている。これら下側および上側ヒートシンク２２、２３は共に、一面が樹脂部２０から露出させられ、半導体チップ１から発せられる熱を放出し易くした構成とされている。
【００３８】
内部ヒートシンク２４は半導体チップ１のエミッタ電極１６から伝わってくる熱を上側ヒートシンク２３側へ逃がすと共に、エミッタ電極１３と上側ヒートシンク２３との電気的接続を図るものであり、例えばＣｕなどで構成される。
【００３９】
このように構成されたモールド型パワーデバイスにおいては、上述したように、半導体チップ１に形成されたＩＧＢＴとの電気的接合を行うためのはんだ１４が第１金属層１３ａよりも降伏応力が小さなＳｎ−Ｃｕ−Ｎｉの３元系はんだ材で構成されている。このため、半導体基板表面近傍に発生し得るせん断応力も小さなものとなり、半導体チップ１を樹脂部２０にて封止したとしても、第１金属層１３ａにクラックが発生することを防止することができる。したがって、エミッタ電極１３の剥離やＩＧＢＴの破壊を防止することができる。また、ＩＧＢＴの表面が破壊されることによって引き起こされる不具合、例えば電流が流れなくなったり、熱の流れが止まるなどによって素子そのものが破壊されたりすることも防止することができる。
【００４０】
参考として、−４０℃〜１２５℃の加熱冷却を３０００サイクル繰り返すという液相冷熱サイクル試験により、本実施形態のようにＳｎ−Ｃｕ−Ｎｉの３元系はんだ材ではんだ１４を形成した場合とＳｎ−Ａｇ−Ｃｕの３元系はんだ材を用いた場合、それぞれの場合における半導体基板表面近傍の様子を調べた。その結果、Ｓｎ−Ａｇ−Ｃｕの３元系はんだ材を用いた場合には、ＩＧＢＴの表面に形成される電極層にクラックが発生してＩＧＢＴが破壊されていた。これに対し、本実施形態のようにＳｎ−Ｃｕ−Ｎｉの３元系はんだ材を用いた場合には、ＩＧＢＴの表面に形成される第１電極層１３ａにクラックが発生せず、ＩＧＢＴも全く破壊されていなかった。この結果からも、本実施形態の構成を採用することで、エミッタ電極１３の剥離やＩＧＢＴの破壊を防止できるといえる。
【００４１】
（他の実施形態）
上記第１実施形態では、第１金属層１３ａをＡｌ−Ｓｉ−ＣｕからなるＡｌを主成分とするＡｌ合金で構成した場合において、それよりも降伏応力が小さくなる材質であるＳｎ−Ｃｕ−Ｎｉではんだ１４を形成する場合について説明している。Ａｌ合金としてはＡｌ-Ｃｕ、Ａｌ−Ｓｉもしくは他の添加元素を含むものが採用可能である。また純Ａｌを採用してもよい。要は、はんだ１４の材質の降伏応力が半導体素子と電気的に接続される第１金属層１３ａの材質よりも小さくなればよく、第１金属層１３ａとはんだ１４とは他の組み合わせも適用可能である。
【００４２】
例えば、第１金属層１３ａがＡｌを主成分とする金属材料で構成される場合、はんだ１４をＳｎ−ＣｕやＳｎ−Ｎｉの２元系の金属材料またはＳｎ−Ｃｕ−Ｎｉの３元系の金属材料で構成することが可能である。
【００４３】
また、上記実施例では、第１金属層１３ａを直接半導体基板（Ｓｉ）に接触する電極層として説明するものであったが、バリアメタルをＡｌ合金とＳｉとの間に挿入してエミッタ電極を構成する場合もある。その場合も本発明は適用可能である。すなわち、エミッタ電極を構成する全ての積層金属膜の何れよりも降伏応力が小さくなる材質をはんだ材料に選ぶようにすればよい。
【００４４】
また、第１金属層１３ａはＡｌを主成分とする金属材料に限定されるものでもない。第１金属層１３ａがＣｕを主成分とする金属材料で構成される場合には、はんだ１４をＳｎ−Ａｇの２元系の金属材料またはＳｎ−Ａｇ−Ｃｕの３元系の金属材料で構成することも可能である。
【００４５】
また、半導体素子としてＩＧＢＴを例に挙げて説明したが、他の半導体素子についても適用可能である。例えば、縦型ＭＯＳＦＥＴ、ダイオードやバイポーラトランジスタに対しても本発明を適用可能である。
【図面の簡単な説明】
【図１】本発明の第１実施形態が適用された半導体チップの断面構成を示す図である。
【図２】図１に示す半導体チップを樹脂封止したモールド型パワーデバイスの断面構成を示す図である。
【図３】第１電極層を構成する金属材料とＳｎ−Ａｇ−Ｃｕのはんだ材およびＳｎ−Ｃｕ−Ｎｉのはんだ材との温度と降伏応力の関係を示した図である。
【図４】Ｓｎ−Ａｇ−Ｃｕのはんだ材とＳｎ−Ｃｕ−Ｎｉのはんだ材それぞれにおける半導体基板表面近傍に発生するせん断応力を調べた結果を示す図である。
【図５】従来のモールド型パッケージの断面構成を示した図である。
【符号の説明】
１…半導体チップ、２…ｐ+型基板、３…ｎ-型ドリフト層、
１３…エミッタ電極、１３ａ…第１金属層、１３ｂ…第２金属層、
１３ｃ…第３金属層、１４…はんだ、２０…樹脂部、
２１…モールド型パワーデバイス、２２…下側ヒートシンク、
２３…上側ヒートシンク、２４…内部ヒートシンク。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a molded semiconductor device in which a semiconductor chip including a semiconductor element such as an insulated gate bipolar transistor (hereinafter referred to as IGBT) is resin-molded.
[0002]
[Prior art]
Conventionally, a semiconductor package in which a semiconductor chip on which a semiconductor element is formed is sealed with a resin has been proposed (see Patent Document 1). FIG. 5 shows this conventional semiconductor package 36.
[0003]
The semiconductor package 36 includes a semiconductor chip 37 having an IGBT on a semiconductor substrate, a lower heat sink 38 connected to the collector electrode of the IGBT, an upper heat sink 39 connected to the emitter electrode of the IGBT, and an upper surface of the semiconductor device 37. And an internal heat sink 40 installed in the. Each member is electrically connected via a solder 41. The gate electrode of the semiconductor chip 37 and the lead frame 42 are connected via the gate wire 43. The semiconductor package 36 is formed by sealing with a resin 44 so that one side of each of the lower and upper heat sinks 38 and 39 and a part of the lead frame 42 are exposed.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2003-110064
[Problems to be solved by the invention]
The semiconductor package 36 described above is formed by pouring molten resin 44 into the mold after each member is placed in the mold. At this time, since the resin 44 is set to 180 ° C., each member constituting the semiconductor package 36 is heated by the heat of the resin 44. At this time, a stress is generated due to a difference in coefficient of linear expansion of each member, but the stress is absorbed by the solder 41 joining each member.
[0006]
However, when the stress generated by the difference in linear expansion coefficient is large, the solder 41 cannot absorb the stress, and this stress is applied to the semiconductor substrate on which the IGBT emitter electrode and IGBT are formed. When the emitter electrode and the semiconductor substrate are subjected to this stress, there arises a problem that the Al layer as the electrode material of the emitter electrode is cracked and the emitter electrode is peeled off from the semiconductor substrate. In such a case, even if the IGBT does not operate or operates, heat conduction is not satisfactorily performed due to the gap at the peeling site, and heat that should be released is not released from the IGBT, and the IGBT is destroyed. Problem arises.
[0007]
Further, when the semiconductor package 36 is actually used, the semiconductor package 36 is heated to a high temperature due to the operation of the semiconductor element, or is exposed to a low temperature due to temperature fluctuations in the use atmosphere. The This thermal cycle similarly causes stress or distortion in the electrode portion, and there is a concern that the electrode may be peeled off and eventually cause malfunction or destruction of the IGBT, as described above.
[0008]
In recent years, a hard material solder such as lead-free solder has been used. When such a hard solder is used, the above-described problem is more likely to occur.
[0009]
An object of the present invention is to provide a mold type semiconductor device capable of preventing a semiconductor element from being destroyed by stresses caused by various thermal changes.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present inventors paid attention to the relationship between the electrode material of the semiconductor chip in the mold type power device (mold type semiconductor device) and the solder material connected to the electrode material. As a result, in the relationship between the yield stress of each of the semiconductor chip electrode material and the solder material, the stress generated by the thermal cycle is reduced by making the solder material have a smaller yield stress than the semiconductor chip electrode material. It was confirmed that the effect of being able to be absorbed by the solder and preventing the electrode material from cracking can be obtained.
[0011]
More specifically, when the electrode material of the semiconductor chip has a multi-layer structure, the yield stress of the solder material is preferably smaller than the electrode material of each layer constituting the multi-layer structure, and the lower layer side connected to at least the semiconductor chip It was found that the effects described above can be obtained if the electrode material is smaller than the above electrode material.
[0012]
In addition, there are various types of semiconductor chip electrode materials, and the yield stress varies depending on the type, but if the yield stress of the solder material is small compared to the yield stress of the semiconductor chip electrode material selected. It has also been confirmed that the effects described above can be obtained. That is, for example, when a three-layer structure of an Al layer, a Ni layer, and an Au layer is employed as the electrode material of the semiconductor chip, the lowermost layer directly connected to the semiconductor chip is the Al layer. For this reason, the yield stress of the solder material is required to be smaller than that of the Al layer having a relatively low yield stress. Further, when the electrode material of the semiconductor chip has a three-layer structure of a Cu layer, an Ni layer, and an Au layer, for example, the lowermost layer directly connected to the semiconductor chip is the Cu layer. In this case, since it is sufficient that the yield stress of the solder material is smaller than that of the Cu layer having a relatively large yield stress, options for the solder material are expanded.
[0013]
The yield stress here refers to the yield phenomenon, that is, when the stress applied to the material reaches a certain value exceeding the elastic limit, it causes a phenomenon in which plastic strain occurs suddenly with almost no increase in stress. It refers to the stress required for Generally, when the stress shows a maximum accompanying yield, the stress at the maximum point is regarded as the yield stress. However, when the maximum does not appear clearly, a stress (0) that causes a permanent strain of 0.2%. .2% yield strength) is practically treated as yield stress. In the present specification, it is an example in which a metal such as solder or electrode material does not clearly show a maximum, and therefore, 0.2% proof stress is defined as a yield stress.
[0014]
Based on the above examination results, in the invention according to claim 1 , the metal member (13) and the Pb-free solder (14) are disposed on the surface of the semiconductor chip (1) on which the semiconductor element is formed via the metal member (13). in mold type power device 24) is formed by bonding, a Pb-free solder yield stress, is characterized in that is smaller than the yield stress of the metal layer.
[0015]
In this way, by configuring the Pb-free solder connected to the metal layer with a solder material whose yield stress is smaller than that of the metal layer, the stress generated by the thermal cycle can be absorbed by the Pb-free solder, and the electrode material is cracked. Can be prevented. As shown in claim 1 , if the Pb-free solder is made of Sn—Cu—Ni ternary solder material, the yield stress can be made smaller than that of the metal layer.
[0016]
In the first aspect of the present invention, the metal layer has the first metal layer (13a) formed on the surface of the semiconductor element and electrically connected to the semiconductor element, and the yield stress of the Pb-free solder is reduced. , At least smaller than the yield stress of the first metal layer. As described above, if the yield stress of the Pb-free solder is smaller than the yield stress of the metal material of the first metal layer that is electrically connected to the semiconductor element, the above effect can be obtained.
[0017]
According to another aspect of the present invention, the metal layer is composed of a multilayer metal layer including first and second metal layers , the first metal layer is a metal material containing Al, and the second metal layer is a metal material containing Ni. in Ru it is configured. Also in this case, it is sufficient that the yield stress of the Pb-free solder is smaller than that of the first metal layer.
[0018]
The invention according to claim 1 is characterized in that the thickness of the Al layer is at least 2 μm. Thus, by setting the thickness of the Al layer to 2 μm or more, it is possible to prevent the semiconductor substrate itself from being cracked due to the influence of strain due to stress.
[0020]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor chip 1 to which an embodiment of the present invention is applied. FIG. 2 is a diagram showing a cross-sectional structure of a molded power device in which the semiconductor chip 1 is resin-molded. Hereinafter, the configuration of the semiconductor chip 1 and the mold type power device will be described based on these drawings.
[0022]
The semiconductor chip 1 is formed using a semiconductor substrate in which an n − type drift layer 3 is formed on the main surface of a p + type substrate 2, and the semiconductor chip 1 is formed on the cell portion and the outer periphery of the cell portion. The outer periphery pressure | voltage resistant part formed is comprised.
[0023]
A number of IGBTs are formed in the cell portion. A p-type base layer 4 is formed on the surface layer portion of the n − -type drift layer 3, and an n + -type source layer 6 is formed on the surface layer portion of the p-type base layer 4. A trench 7 is formed so as to penetrate the n + -type source layer 6 and the p-type base layer 4 and reach the n − -type drift layer 3. A gate insulating film 8 and a gate layer 9 are formed on the inner wall surface of the trench 7. Are formed in order, and a trench gate structure including the trench 7, the gate insulating film 8, and the gate layer 9 is formed. Further, a part of the n + type source layer 6 and the trench gate structure are covered with an insulating film 12a. A collector electrode 18 is formed on the back surface of the p + type substrate 2 so as to be in contact with the back surface.
[0024]
Further, an emitter electrode 13 is formed on the surface of the IGBT. The emitter electrode 13 includes, for example, a first metal layer 13a made of an Al alloy whose main component is Al, such as Al-Si-Cu, a second metal layer 13b made of Ni, and a third metal layer 13c made of Au. It is comprised from the multilayer metal layer which has. A Pb-free solder 14 is connected to the surface of the third metal layer 13 c in the emitter electrode 13. In FIG. 1, the emitter electrode 13 is shown in a state before melting the solder 14 for convenience.
[0025]
The first metal layer 13a is formed so as to straddle a plurality of trench gate structures, is formed so as to be in contact with the p-type base layer 4 and the n + -type source layer 6, and commonly connects a number of IGBTs. The first metal layer 13a is formed by sputtering, for example, and has a thickness of about 2 μm or more. This is because when the first metal layer 13a is less than 2 μm, the influence of strain due to stress acts on the semiconductor substrate itself, not the first metal layer 13a. Therefore, the first metal film 13a is set to the above-described film thickness in order to prevent the semiconductor substrate itself from being cracked due to the influence of strain due to stress. The first metal layer 13 a is made of an Al alloy as described above, and has a higher yield stress than the solder 14 as a material.
[0026]
The second metal layer 13b is made of Ni having good bonding properties with both the metal constituting the first metal layer 13a and the third metal layer 13c, and is, for example, 5 μm by a wet process, specifically wet electroless plating. It is formed with a film thickness of about. Ni constituting the second metal layer 13 b is a harder material than the solder 14, and its yield stress is higher than that of the solder 14.
[0027]
The third metal layer 13c is made of, for example, Au formed by plating so that the oxidation of Ni is suppressed and the wettability of the solder 14 is improved. The third metal layer 13c has a film thickness of, for example, about 0.1 μm, but is dissipated when the solder 14 melts and the solder Sn and Ni of the second metal layer 13b form an alloy layer. As a result, there may be little thickness remaining. Au constituting the third metal layer 13c is a soft material, but is very thin as compared with the first and second metal layers 13a and 13b, or is hardly present in layers after melting. It is not necessary to take into account the influence of strain caused by stress caused by the difference in expansion coefficient.
[0028]
The solder 14 is made of Sn—Cu—Ni ternary solder material, and the composition thereof is, for example, about 0.5 to 2.0% by weight of Cu and 0.05 to 0.1% by weight of Ni. About%, Sn consists of the balance and a trace amount of mixed components. The solder 14 configured with such a composition ratio has a small yield stress, specifically, smaller than the first metal layer 13a.
[0029]
FIG. 3 shows the relationship between the temperature (° C.) and the yield stress [MPa] of the material of the first metal layer 13a serving as the element electrode material, the solder 14 shown in the present embodiment, and the conventional typical Pb-free solder material. Indicates. However, this figure is an example in which each material was compared and evaluated in the same form in a temperature range of −40 to 150 ° C. For the sample shape, a shape used for a general tensile test or torsion test may be referred to. In addition, the conventional typical Pb-free solder material here refers to the Sn-Ag-Cu ternary solder material.
[0030]
As can be seen from this figure, the relationship between the yield stress of the material of the first metal layer 13a and the material of the solder 14 is that the first metal layer 13a is more solderable in any temperature range where the mold type power device can be used. Is bigger than. In this embodiment, the solder 14 is formed using such a material.
[0031]
When the solder 14 was formed using such a material, it was examined how much shear stress was generated in the vicinity of the surface of the semiconductor substrate. Specifically, Sn—Cu—Ni ternary is used in which Al—Si—Cu is used as the first metal layer 13a, and yield stress is smaller than that of the first metal layer 13a in a temperature range where the mold type power device can be used. A Sn-Ag-Cu ternary solder material in which the yield stress is smaller than that of the first metal layer 13a in a part of the temperature range in which the mold type power device can be used. When the solder 14 was formed, the shear stress generated in the vicinity of the surface of the semiconductor substrate was compared. The result is shown in FIG.
[0032]
As shown in this figure, when the solder 14 is formed with the Sn-Cu-Ni ternary solder material, the shear stress is larger than when the Sn-Ag-Cu ternary solder material is used. Can be seen to be smaller. Thus, in the present embodiment, when an Al alloy is used as the first metal layer 13a, Sn—Cu—Ni whose yield stress is smaller than that of the first metal layer 13a in a temperature range where the mold type device can be used. The solder 14 is formed of the ternary solder material. For this reason, the shear stress generated near the surface of the semiconductor substrate is also small.
[0033]
On the other hand, a field formed on the p-type layer 5 through the p-type layer 5 formed in the surface layer portion of the n − -type drift layer 3 and the LOCOS oxide film 11 and the insulating film 12b is formed in the outer peripheral breakdown voltage portion. A first electrode 15 as a plate is provided. In addition, an n + type layer 10 formed in the surface layer portion of the n − type drift layer 3 and a second electrode 16 as an outermost ring formed so as to be in contact with the n + type layer 10 are provided. . These first and second electrodes 15 and 16 alleviate the electric field concentration generated inside the IGBT when a surge is applied to the semiconductor chip 1, thereby reducing the electric field strength. And the passivation film 17 which covers the 1st, 2nd electrodes 15 and 16 is formed, and the surface of an outer periphery pressure | voltage resistant part is protected.
[0034]
The semiconductor chip 1 configured as described above is sealed with the resin portion 20 to form the semiconductor package 21 shown in FIG.
[0035]
As shown in FIG. 2, the semiconductor package 21 has a configuration in which the lower heat sink 22, the upper heat sink 23, the internal heat sink 24, the gate wire 25, and the lead terminal 26 are sealed together with the semiconductor chip 1 in the resin portion 20. ing. The gate electrode pad of the IGBT formed on the semiconductor chip 1 and the lead terminal 26 are wire-bonded via the gate wire 25, and a part of the lead terminal 26 is exposed from the resin portion 20. As a result, a gate drive voltage can be applied to the IGBT from the outside via the lead terminal 26. The gate electrode pad is also made of an Al alloy layer, an Ni plating layer, and an Au plating layer from the lower layer side, like the emitter electrode portion 13, and is connected to the gate layer 9 of each trench gate structure. As described above, the Au layer is about 0.1 μm (0.2 μm or less), and the bonding property with the gate wire 25 made of an Al wire is also good.
[0036]
Also, the space between the upper surface of the lower heat sink 22 and the lower surface of the semiconductor chip 1 is solder 27, the space between the upper surface of the semiconductor chip 1 and the lower surface of the internal heat sink 24 is solder, and the upper surface and upper side of the internal heat sink 24 The lower surface of the heat sink 23 is electrically connected by solder 28. Therefore, the emitter electrode 1 3 of the IGBT formed in the semiconductor chip 1 through the internal heat sink 24 and the upper heatsink 23, also a collector electrode 18 of the IGBT can be electrically connected to the outside via the lower heat sink 22 It is like that.
[0037]
The lower and upper heat sinks 22 and 23 release heat transmitted through the collector electrode 18 and the emitter electrode 13 of the IGBT, respectively, and constitute a current path of the IGBT, and have good thermal conductivity and low electrical resistance. It is made of Cu or the like. Each of the lower and upper heat sinks 22 and 23 is configured such that one surface is exposed from the resin portion 20 and the heat generated from the semiconductor chip 1 is easily released.
[0038]
The internal heat sink 24 releases heat transmitted from the emitter electrode 16 of the semiconductor chip 1 to the upper heat sink 23 side, and also electrically connects the emitter electrode 13 and the upper heat sink 23, and is made of, for example, Cu. .
[0039]
In the mold type power device configured as described above, as described above, the solder 14 for electrical connection with the IGBT formed on the semiconductor chip 1 has a lower yield stress than the first metal layer 13a. -It is comprised with the ternary system solder material of Cu-Ni. For this reason, the shear stress that can be generated in the vicinity of the surface of the semiconductor substrate is small, and even if the semiconductor chip 1 is sealed with the resin portion 20, it is possible to prevent the first metal layer 13a from being cracked. . Therefore, peeling of the emitter electrode 13 and destruction of the IGBT can be prevented. It is also possible to prevent problems caused by the destruction of the surface of the IGBT, for example, the destruction of the element itself due to the fact that the current stops flowing or the heat flow stops.
[0040]
As a reference, when the solder 14 is formed with a Sn—Cu—Ni ternary solder material as in the present embodiment by a liquid phase cooling / heating cycle test in which heating and cooling at −40 ° C. to 125 ° C. are repeated 3000 cycles, Sn is used. When a ternary solder material of -Ag-Cu was used, the state near the surface of the semiconductor substrate in each case was examined. As a result, when Sn—Ag—Cu ternary solder material was used, cracks were generated in the electrode layer formed on the surface of the IGBT and the IGBT was destroyed. On the other hand, when the Sn—Cu—Ni ternary solder material is used as in the present embodiment, no crack is generated in the first electrode layer 13a formed on the surface of the IGBT, and the IGBT is not at all. It was not destroyed. Also from this result, it can be said that by adopting the configuration of this embodiment, peeling of the emitter electrode 13 and destruction of the IGBT can be prevented.
[0041]
(Other embodiments)
In the first embodiment, in the case where the first metal layer 13a is made of an Al alloy mainly composed of Al—Si—Cu, it is Sn—Cu—Ni, which is a material having a lower yield stress. The case where the solder 14 is formed is described. As the Al alloy, an alloy containing Al-Cu, Al-Si, or other additive elements can be used. Pure Al may also be adopted. In short, it is sufficient that the yield stress of the material of the solder 14 is smaller than the material of the first metal layer 13a electrically connected to the semiconductor element, and other combinations of the first metal layer 13a and the solder 14 are applicable. It is.
[0042]
For example, when the first metal layer 13a is made of a metal material mainly composed of Al, the solder 14 is made of a binary metal material of Sn—Cu or Sn—Ni or a ternary system of Sn—Cu—Ni. It can be made of a metal material.
[0043]
In the above embodiment, the first metal layer 13a is described as an electrode layer in direct contact with the semiconductor substrate (Si). However, an emitter electrode is formed by inserting a barrier metal between the Al alloy and Si. May be configured. Even in that case, the present invention is applicable. That is, a material whose yield stress is smaller than any of all the laminated metal films constituting the emitter electrode may be selected as the solder material.
[0044]
The first metal layer 13a is not limited to a metal material mainly composed of Al. When the first metal layer 13a is made of a metal material containing Cu as a main component, the solder 14 is made of a Sn-Ag binary metal material or a Sn-Ag-Cu ternary metal material. It is also possible to do.
[0045]
Moreover, although IGBT was mentioned as an example as a semiconductor element, it is applicable also to another semiconductor element. For example, the present invention can be applied to a vertical MOSFET, a diode, or a bipolar transistor.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor chip to which a first embodiment of the present invention is applied.
FIG. 2 is a view showing a cross-sectional configuration of a mold type power device in which the semiconductor chip shown in FIG. 1 is sealed with resin.
FIG. 3 is a diagram showing the relationship between the temperature and the yield stress of a metal material constituting a first electrode layer, a Sn—Ag—Cu solder material, and a Sn—Cu—Ni solder material.
FIG. 4 is a diagram showing a result of examining a shear stress generated in the vicinity of the surface of a semiconductor substrate in each of a Sn—Ag—Cu solder material and a Sn—Cu—Ni solder material.
FIG. 5 is a diagram showing a cross-sectional configuration of a conventional mold type package.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... p <+> type | mold substrate, 3 ... n < - > type | mold drift layer,
13 ... Emitter electrode, 13a ... First metal layer, 13b ... Second metal layer,
13c ... 3rd metal layer, 14 ... Solder, 20 ... Resin part,
21 ... Mold type power device, 22 ... Lower heat sink,
23 ... Upper heat sink, 24 ... Internal heat sink.

Claims (1)

半導体素子が形成された半導体チップ（１）の表面に金属層（１３）およびＰｂフリーはんだ（１４）を介して金属部材（２４）が接合されてなるモールド型パワーデバイスにおいて、
前記金属層は、前記半導体素子の表面に形成され前記半導体素子と電気的接続がなされる第１金属層（１３ａ）と、前記第１金属層の上に該第１金属層と異なる金属材料で構成された第２金属層（１３ｂ）とを有した多層金属層であって、
前記第１金属層はＡｌを含む金属材料であり厚みが少なくとも２μｍとして構成され、第２金属層はＮｉを含む金属材料で構成されているとともに、
前記Ｐｂフリーはんだは、Ｓｎ−Ｃｕ−Ｎｉの３元系のはんだ材料で構成されることにより、
−４０〜１５０℃の温度域において、前記Ｐｂフリーはんだの降伏応力を前記第１金属層の降伏応力よりも小さくしたことを特徴とするモールド型パワーデバイス。In a molded power device in which a metal member (24) is joined to a surface of a semiconductor chip (1) on which a semiconductor element is formed via a metal layer (13) and Pb-free solder (14),
The metal layer includes a first metal layer (13a) formed on a surface of the semiconductor element and electrically connected to the semiconductor element, and a metal material different from the first metal layer on the first metal layer. A multilayer metal layer having a second metal layer (13b) configured,
The first metal layer is a metal material containing Al and has a thickness of at least 2 μm, the second metal layer is made of a metal material containing Ni,
The Pb-free solder is composed of Sn—Cu—Ni ternary solder material,
A mold type power device , wherein a yield stress of the Pb-free solder is made smaller than a yield stress of the first metal layer in a temperature range of -40 to 150 ° C.
JP2003178147A 2003-06-23 2003-06-23 Molded power device Expired - Fee Related JP4171355B2 (en)

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JP2003178147A JP4171355B2 (en) 2003-06-23 2003-06-23 Molded power device
US10/859,130 US7193326B2 (en) 2003-06-23 2004-06-03 Mold type semiconductor device
DE102004030056.9A DE102004030056B4 (en) 2003-06-23 2004-06-22 Molded semiconductor device
CNB2004100616490A CN100353541C (en) 2003-06-23 2004-06-23 Mold type semiconductor device and method for manufacturing the same
US11/702,498 US7468318B2 (en) 2003-06-23 2007-02-06 Method for manufacturing mold type semiconductor device

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