JP2019054185A - Wafer processing method - Google Patents
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- JP2019054185A JP2019054185A JP2017178721A JP2017178721A JP2019054185A JP 2019054185 A JP2019054185 A JP 2019054185A JP 2017178721 A JP2017178721 A JP 2017178721A JP 2017178721 A JP2017178721 A JP 2017178721A JP 2019054185 A JP2019054185 A JP 2019054185A
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- 238000003672 processing method Methods 0.000 title claims abstract description 7
- 239000003566 sealing material Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000003384 imaging method Methods 0.000 claims abstract description 10
- 230000001678 irradiating effect Effects 0.000 claims abstract description 3
- 238000003331 infrared imaging Methods 0.000 claims description 11
- 239000008393 encapsulating agent Substances 0.000 claims description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 239000006229 carbon black Substances 0.000 abstract description 6
- 230000035699 permeability Effects 0.000 abstract 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 89
- 239000002184 metal Substances 0.000 description 12
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/50—Working by transmitting the laser beam through or within the workpiece
- B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
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- B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
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- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
- B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
Description
本発明は、WL-CSPウェーハの加工方法に関する。 The present invention relates to a method for processing a WL-CSP wafer.
WL-CSP(Wafer-level Chip Size Package)ウェーハとは、ウェーハの状態で再配線層や電極(金属ポスト)を形成後、表面側を樹脂封止し、切削ブレード等で各パッケージに分割する技術であり、ウェーハを個片化したパッケージの大きさが半導体デバイスチップの大きさになるため、小型化及び軽量化の観点からも広く採用されている。 WL-CSP (Wafer-level Chip Size Package) wafer is a technology that forms a redistribution layer and electrodes (metal posts) in the wafer state, then encapsulates the surface side with resin and divides each package with a cutting blade Since the size of the package obtained by dividing the wafer into pieces becomes the size of the semiconductor device chip, it is widely adopted from the viewpoint of miniaturization and weight reduction.
WL-CSPウェーハの製造プロセスでは、複数のデバイスが形成されたデバイスウェーハのデバイス面側に再配線層を形成し、更に再配線層を介してデバイス中の電極に接続する金属ポストを形成した後、金属ポスト及びデバイスを樹脂で封止する。 In the WL-CSP wafer manufacturing process, after forming a redistribution layer on the device surface side of a device wafer on which a plurality of devices are formed, and then forming a metal post that connects to the electrodes in the device via the redistribution layer The metal post and the device are sealed with resin.
次いで、封止材を薄化するとともに金属ポストを封止材表面に露出させた後、金属ポストの端面に電極バンプと呼ばれる外部端子を形成する。その後、切削装置等でWL-CSPウェーハを切削して個々のCSPへと分割する。 Next, after the sealing material is thinned and the metal posts are exposed on the surface of the sealing material, external terminals called electrode bumps are formed on the end faces of the metal posts. After that, the WL-CSP wafer is cut by a cutting device or the like and divided into individual CSPs.
半導体デバイスを衝撃や湿気等から保護するために、封止材で封止することが重要である。通常、封止材として、エポキシ樹脂中にSiCからなるフィラーを混入した封止材を使用することで、封止材の熱膨張率を半導体デバイスチップの熱膨張率に近づけ、熱膨張率の差によって生じる加熱時のパッケージの破損を防止している。 In order to protect the semiconductor device from impact, moisture and the like, it is important to seal with a sealing material. Normally, by using a sealing material in which a filler made of SiC is mixed in an epoxy resin as the sealing material, the thermal expansion coefficient of the sealing material approaches the thermal expansion coefficient of the semiconductor device chip, and the difference in thermal expansion coefficient Prevents damage to the package during heating.
WL-CSPウェーハは、一般的に切削装置を使用して個々のCSPに分割される。この場合、WL-CSPウェーハは、分割予定ラインを検出するために利用するデバイスが樹脂で覆われているため、表面側からデバイスのターゲットパターンを検出することができない。 WL-CSP wafers are generally divided into individual CSPs using a cutting machine. In this case, the WL-CSP wafer cannot detect the target pattern of the device from the front side because the device used to detect the division line is covered with resin.
その為、WL-CSPウェーハの樹脂上に形成された電極バンプをターゲットにして分割予定ラインを割り出したり、樹脂の上面にアライメント用のターゲットを印刷する等して分割予定ラインと切削ブレードとのアライメントをおこなっていた。 Therefore, align the planned dividing line with the cutting blade by indexing the planned dividing line using the electrode bumps formed on the resin of the WL-CSP wafer as the target, or printing the alignment target on the upper surface of the resin. I was doing.
しかし、電極バンプや樹脂上に印刷されたターゲットはデバイスのように高精度には形成されていないため、アライメント用のターゲットとしては精度が低いという問題がある。従って、電極バンプや印刷されたターゲットに基づいて分割予定ラインを割り出した場合、分割予定ラインから外れてデバイス部分を切削してしまうという恐れがあった。 However, since the target printed on the electrode bumps or the resin is not formed with high accuracy like the device, there is a problem that the accuracy is low as an alignment target. Therefore, when the division line is determined based on the electrode bumps or the printed target, there is a risk that the device part is cut off from the division line.
そこで、例えば特開2013−74021号公報では、ウェーハの外周で露出するデバイスウェーハのパターンを基にアライメントする方法が提案されている。 Therefore, for example, Japanese Patent Application Laid-Open No. 2013-740221 proposes an alignment method based on a pattern of a device wafer exposed on the outer periphery of the wafer.
しかし、一般にウェーハの外周ではデバイス精度が悪く、ウェーハの外周で露出するパターンを基にアライメントを実施すると、分割予定ラインとは外れた位置でウェーハを分割してしまう恐れがある上、ウェーハによってはデバイスウェーハのパターンが外周で露出していないものもある。 However, in general, the device accuracy is poor at the outer periphery of the wafer, and if alignment is performed based on the pattern exposed at the outer periphery of the wafer, the wafer may be divided at a position outside the planned dividing line, and depending on the wafer Some device wafer patterns are not exposed on the outer periphery.
本発明はこのような点に鑑みてなされたものであり、その目的とするところは、ウェーハ表面に被覆されたカーボンブラックを含む封止材を通してアライメント工程を実施可能なウェーハの加工方法を提供することである。 The present invention has been made in view of these points, and an object of the present invention is to provide a wafer processing method capable of performing an alignment step through a sealing material containing carbon black coated on the wafer surface. That is.
本発明によると、表面に交差して形成された複数の分割予定ラインによって区画されたチップ領域にそれぞれデバイスが形成されたデバイスウェーハの表面が封止材で封止され、該封止材の該チップ領域にそれぞれ複数のバンプが形成されたウェーハの加工方法であって、該ウェーハの表面側から赤外線撮像手段によって該封止材を透過して該デバイスウェーハの表面側を撮像してアライメントマークを検出し、該アライメントマークに基づいてレーザー加工すべき該分割予定ラインを検出するアライメント工程と、該アライメント工程を実施した後、該デバイスウェーハ及び該封止材に対して透過性を有する波長のレーザービームの集光点を該デバイスウェーハ又は該封止材の内部に位置付けて、該ウェーハの表面側から該分割予定ラインに沿ってレーザービームを照射して、該デバイスウェーハ及び該封止材の内部に改質層を形成する改質層形成工程と、該改質層形成工程を実施した後、該デバイスウェーハ及び該封止材に外力を付与して該改質層を分割起点として表面が該封止材によって封止された個々のデバイスチップに分割する分割工程と、を備え、該封止材は該赤外線撮像手段が受光する赤外線が透過するような透過性を有することを特徴とするウェーハの加工方法が提供される。 According to the present invention, the surface of a device wafer on which a device is formed in each chip region defined by a plurality of division lines formed crossing the surface is sealed with a sealing material, and the sealing material A method of processing a wafer in which a plurality of bumps are formed in each chip region, wherein an alignment mark is formed by imaging the surface side of the device wafer through the sealing material by infrared imaging means from the surface side of the wafer. An alignment step for detecting and detecting the division line to be laser processed based on the alignment mark, and a laser having a wavelength that is transparent to the device wafer and the sealing material after the alignment step is performed. A beam condensing point is positioned inside the device wafer or the sealing material, and the splitting line is formed from the surface side of the wafer. A modified layer forming step of forming a modified layer inside the device wafer and the sealing material by irradiating a laser beam along the device wafer, and after performing the modified layer forming step, the device wafer and the encapsulation A splitting step in which an external force is applied to the stopper and the modified layer is divided into individual device chips whose surfaces are sealed by the sealant using the modified layer as a starting point. There is provided a method for processing a wafer, which has a transparency that allows infrared rays received by the laser beam to pass therethrough.
好ましくは、アライメント工程で用いる赤外線撮像手段はInGaAs撮像素子を含む。 Preferably, the infrared imaging means used in the alignment step includes an InGaAs imaging device.
本発明のウェーハの加工方法によると、赤外線撮像手段が受光する赤外線が透過するような封止材でデバイスウェーハの表面を封止し、赤外線撮像手段によって封止材を透過してデバイスウェーハに形成されたアライメントマークを検出し、アライメントマークに基づいてアライメントを実施できるようにしたので、従来のようにウェーハの表面の外周部分の封止材を除去することなく、簡単にアライメント工程を実施できる。 According to the wafer processing method of the present invention, the surface of the device wafer is sealed with a sealing material that transmits infrared rays received by the infrared imaging means, and the sealing material is transmitted by the infrared imaging means to be formed on the device wafer. Since the detected alignment mark is detected and alignment can be performed based on the alignment mark, the alignment process can be easily performed without removing the sealing material on the outer peripheral portion of the wafer surface as in the prior art.
よって、デバイスウェーハ及び封止材に対して透過性を有する波長のレーザービームの集光点をデバイスウェーハ又は封止材の内部に位置付けて、ウェーハの表面側からレーザービームを照射して、デバイスウェーハ及び封止材の内部に改質層を形成し、該改質層を分割起点としてウェーハを表面が封止材によって封止された個々のデバイスチップに分割することができる。 Therefore, the condensing point of the laser beam having a wavelength that is transmissive to the device wafer and the sealing material is positioned inside the device wafer or the sealing material, and the laser beam is irradiated from the front surface side of the wafer to obtain the device wafer. Then, a modified layer is formed inside the encapsulant, and the wafer can be divided into individual device chips whose surfaces are encapsulated by the encapsulant using the modified layer as a division starting point.
以下、本発明の実施形態を図面を参照して詳細に説明する。図1(A)を参照すると、WL-CSPウェーハ27の分解斜視図が示されている。図1(B)はWL-CSPウェーハ27の斜視図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1A, an exploded perspective view of the WL-CSP wafer 27 is shown. FIG. 1B is a perspective view of the WL-CSP wafer 27.
図1(A)に示されているように、デバイスウェーハ11の表面11aには格子状に形成された複数の分割予定ライン(ストリート)13によって区画された各領域にLSI等のデバイス15が形成されている。 As shown in FIG. 1A, devices 15 such as LSIs are formed on the surface 11a of the device wafer 11 in each region partitioned by a plurality of planned division lines (streets) 13 formed in a lattice pattern. Has been.
デバイスウェーハ、(以下、単にウェーハと略称することがある)11は予め裏面11bが研削されて所定の厚さ(100〜200μm程度)に薄化された後、図2に示すように、デバイス15中の電極17に電気的に接続された複数の金属ポスト21を形成した後、ウェーハ11の表面11a側を金属ポスト21が埋設するように封止材23で封止する。 As shown in FIG. 2, the device wafer 11 (hereinafter simply referred to as “wafer”) 11 is preliminarily ground and thinned to a predetermined thickness (about 100 to 200 μm). After forming a plurality of metal posts 21 electrically connected to the inner electrode 17, the surface 11 a side of the wafer 11 is sealed with a sealing material 23 so that the metal posts 21 are embedded.
封止材23としては、質量%でエポキシ樹脂又はエポキシ樹脂+フェノール樹脂10.3%、シリカフィラー8.53%、カーボンブラック0.1〜0.2%、その他の成分4.2〜4.3%を含む組成とした。その他の成分としては、例えば、金属水酸化物、三酸化アンチモン、二酸化ケイ素等を含む。 As the sealing material 23, epoxy resin or epoxy resin + phenol resin 10.3%, silica filler 8.53%, carbon black 0.1-0.2%, other components 4.2-4. The composition contained 3%. Examples of other components include metal hydroxide, antimony trioxide, silicon dioxide, and the like.
このような組成の封止材23でウェーハ11の表面11aを被覆してウェーハ11の表面11aを封止すると、封止材23中にごく少量含まれているカーボンブラックにより封止材23が黒色となるため、封止材23を通してウェーハ11の表面11aを見ることは通常困難である。 When the surface 11a of the wafer 11 is covered with the sealing material 23 having such a composition and the surface 11a of the wafer 11 is sealed, the sealing material 23 is black due to the carbon black contained in the sealing material 23 in a very small amount. Therefore, it is usually difficult to see the surface 11 a of the wafer 11 through the sealing material 23.
ここで封止材23中にカーボンブラックを混入させるのは、主にデバイス15の静電破壊を防止するためであり、現在のところカーボンブラックを含有しない封止材は市販されていない。 The reason why carbon black is mixed in the encapsulant 23 is mainly to prevent electrostatic breakdown of the device 15, and at present no encapsulant containing carbon black is commercially available.
他の実施形態として、デバイスウェーハ11の表面11a上に再配線層を形成した後、再配線層上にデバイス15中の電極17に電気的に接続された金属ポスト21を形成するようにしても良い。 As another embodiment, after the rewiring layer is formed on the surface 11a of the device wafer 11, the metal post 21 electrically connected to the electrode 17 in the device 15 may be formed on the rewiring layer. good.
次いで、単結晶ダイアモンドからなるバイト切削工具を有する平面切削装置(サーフェスプレイナー)やグラインダーと呼ばれる研削装置を使用して封止材23を薄化する。封止材23を薄化した後、例えばプラズマエッチングにより金属ポスト21の端面を露出させる。 Next, the sealing material 23 is thinned using a plane cutting device (surface planar) having a cutting tool made of single crystal diamond or a grinding device called a grinder. After the sealing material 23 is thinned, the end face of the metal post 21 is exposed, for example, by plasma etching.
次いで、露出した金属ポスト21の端面によく知られた方法によりハンダ等の金属バンプ25を形成して、WL-CSPウェーハ27が完成する。本実施形態のWL-CSPウェーハ27では、封止材23の厚さは100μm程度である。 Next, a metal bump 25 such as solder is formed on the exposed end face of the metal post 21 by a well-known method, and the WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of the present embodiment, the thickness of the sealing material 23 is about 100 μm.
WL-CSPウェーハ27をレーザー加工装置で加工するのに当たり、図3に示すように、好ましくは、WL-CSPウェーハ27を外周部が環状フレームFに貼着された粘着テープとしてのダイシングテープTに貼着する。これにより、WL-CSPウェーハ27はダイシングテープTを介して環状フレームFに支持された状態となる。 When the WL-CSP wafer 27 is processed with a laser processing apparatus, as shown in FIG. 3, the WL-CSP wafer 27 is preferably applied to a dicing tape T as an adhesive tape having an outer peripheral portion attached to an annular frame F. Adhere. As a result, the WL-CSP wafer 27 is supported by the annular frame F via the dicing tape T.
しかし、WL-CSPウェーハ27をレーザー加工装置で加工するのに当たり、環状フレームFを使用せずに、WL-CSPウェーハ27の裏面に粘着テープを貼着する形態でもよい。 However, when processing the WL-CSP wafer 27 with a laser processing apparatus, an adhesive tape may be attached to the back surface of the WL-CSP wafer 27 without using the annular frame F.
本発明のウェーハの加工方法では、まず、WL-CSPウェーハ27の表面側から赤外線撮像手段によって封止材23を通してデバイスウェーハ11の表面11aを撮像し、デバイスウェーハ11の表面に形成されている少なくとも2つのターゲットパターン等のアライメントマークを検出し、これらのアライメントマークに基づいて切削すべき分割予定ライン13を検出するアライメント工程を実施する。 In the wafer processing method of the present invention, first, the surface 11a of the device wafer 11 is imaged from the surface side of the WL-CSP wafer 27 through the sealing material 23 by infrared imaging means, and at least formed on the surface of the device wafer 11. An alignment step is performed in which alignment marks such as two target patterns are detected, and a division line 13 to be cut is detected based on these alignment marks.
このアライメント工程について、図4を参照して詳細に説明する。アライメント工程では、図4に示すように、ダイシングテープTを介してレーザー加工装置のチャックテーブル10でWL-CSPウェーハ27を吸引保持し、デバイスウェーハ11の表面11aを封止している封止材23を上方に露出させる。そして、クランプ12で環状フレームFをクランプして固定する。 This alignment process will be described in detail with reference to FIG. In the alignment step, as shown in FIG. 4, the WL-CSP wafer 27 is sucked and held by the chuck table 10 of the laser processing apparatus through the dicing tape T, and the sealing material sealing the surface 11a of the device wafer 11 is sealed. 23 is exposed upward. Then, the annular frame F is clamped and fixed by the clamp 12.
次いで、図示しないレーザー加工装置の撮像ユニット14の赤外線撮像素子でWL-CSPウェーハ27の封止材23を通してデバイスウェーハ11の表面11aを撮像する。封止材23は、撮像ユニット14の赤外線撮像素子が受光する赤外線が透過する封止材から構成されているため、赤外線撮像素子によってデバイスウェーハ11の表面11aに形成された少なくとも2つのターゲットパターン等のアライメントマークを検出することができる。 Next, the surface 11 a of the device wafer 11 is imaged through the sealing material 23 of the WL-CSP wafer 27 with the infrared imaging element of the imaging unit 14 of the laser processing apparatus (not shown). Since the sealing material 23 is composed of a sealing material that transmits infrared rays received by the infrared imaging element of the imaging unit 14, at least two target patterns formed on the surface 11a of the device wafer 11 by the infrared imaging element, and the like. The alignment mark can be detected.
好ましくは、赤外線撮像素子としては感度の高いInGaAs撮像素子を採用する。好ましくは、撮像ユニット14は、露光時間等を調整できるエキスポジャーを備えている。 Preferably, a highly sensitive InGaAs image sensor is employed as the infrared image sensor. Preferably, the imaging unit 14 includes an exposure that can adjust the exposure time and the like.
次いで、これらのアライメントマークを結んだ直線が加工送り方向と平行となるようにチャックテーブル10をθ回転し、更にアライメントマークと分割予定ライン13の中心との距離だけレーザー加工装置のレーザーヘッドを加工送り方向と直交する方向に移動することにより、レーザー加工すべき分割予定ライン13を検出する。 Next, the chuck table 10 is rotated by θ so that the straight line connecting these alignment marks is parallel to the processing feed direction, and the laser head of the laser processing apparatus is further processed by the distance between the alignment mark and the center of the line 13 to be divided. By moving in a direction perpendicular to the feed direction, the division line 13 to be laser processed is detected.
アライメント工程を実施した後、図5(A)に示すように、WL-CSPウェーハ27の表面側から分割予定ライン13に沿ってレーザー加工装置のレーザーヘッド(集光器)16からデバイスウェーハ11及び封止材23に対して透過性を有する波長(例えば1064nm)のレーザービームLBをその集光点をデバイスウェーハ11の内部又は封止材23の内部に位置付けて、チャックテーブル10を矢印X1方向又は矢印X2方向に加工送りすることにより、デバイスウェーハの内部及び封止材23の内部に改質層29(29a,29b)を形成する改質層形成工程を実施する。 After performing the alignment step, as shown in FIG. 5A, the device wafer 11 and the laser beam (condenser) 16 of the laser processing apparatus are separated from the surface side of the WL-CSP wafer 27 along the scheduled division line 13. The condensing point of the laser beam LB having a wavelength (for example, 1064 nm) having transparency to the sealing material 23 is positioned inside the device wafer 11 or inside the sealing material 23, and the chuck table 10 is moved in the direction of the arrow X1 or By processing and feeding in the direction of the arrow X2, a modified layer forming step for forming modified layers 29 (29a, 29b) inside the device wafer and inside the sealing material 23 is performed.
改質層形成工程では、まず、図5(B)に示すように、レーザービームLBの集光点をデバイスウェーハ11の内部に位置付けてチャックテーブル10を矢印X1方向に加工送りすることにより、デバイスウェーハ11の内部に集光点29aを形成する。 In the modified layer forming step, first, as shown in FIG. 5B, the focusing point of the laser beam LB is positioned inside the device wafer 11, and the chuck table 10 is processed and fed in the direction of the arrow X1, thereby A condensing point 29 a is formed inside the wafer 11.
次いで、図5(C)に示すように、レーザービームLBの集光点を封止材23の内部に位置付けて、チャックテーブル10を矢印X2方向に加工送りすることにより、封止材23の内部に改質層29bを形成する。 Next, as shown in FIG. 5C, the condensing point of the laser beam LB is positioned inside the sealing material 23, and the chuck table 10 is processed and fed in the direction of the arrow X2, so that the inside of the sealing material 23 Then, the modified layer 29b is formed.
この改質層形成工程を第1の方向に伸長する分割予定ライン13に沿って往路及び復路で次々と実施した後、チャックテーブル10を90°回転し、第1の方向に直交する第2の方向に伸長する分割予定ライン13に沿って往路及び復路で次々と実施する。 After this reformed layer forming step is successively performed in the forward path and the backward path along the division line 13 extending in the first direction, the chuck table 10 is rotated by 90 ° and the second direction orthogonal to the first direction is formed. This is performed one after another on the forward path and the return path along the planned dividing line 13 extending in the direction.
改質層形成工程実施後、図6に示す分割装置50を使用してWL-CSPウェーハ27に外力を付与し、WL-CSPウェーハ27を個々のデバイスチップ31へと分割する分割工程を実施する。 After performing the modified layer forming step, the dividing step shown in FIG. 6 is used to apply an external force to the WL-CSP wafer 27 and to divide the WL-CSP wafer 27 into individual device chips 31. .
図7に示す分割装置50は、環状フレームFを保持するフレーム保持手段52と、フレーム保持手段52に保持された環状フレームFに装着されたダイシングテープTを拡張するテープ拡張手段54を具備している。 7 includes a frame holding unit 52 that holds the annular frame F, and a tape expansion unit 54 that extends the dicing tape T attached to the annular frame F held by the frame holding unit 52. Yes.
フレーム保持手段52は、環状のフレーム保持部材56と、フレーム保持部材56の外周に配設された固定手段としての複数のクランプ58から構成される。フレーム保持部材56の上面は環状フレームFを載置する載置面56aを形成しており、この載置面56a上に環状フレームFが載置される。 The frame holding means 52 includes an annular frame holding member 56 and a plurality of clamps 58 as fixing means arranged on the outer periphery of the frame holding member 56. An upper surface of the frame holding member 56 forms a mounting surface 56a on which the annular frame F is mounted, and the annular frame F is mounted on the mounting surface 56a.
そして、載置面56a上に載置された環状フレームFは、クランプ58によってフレーム保持手段56に固定される。このように構成されたフレーム保持手段52はテープ拡張手段54によって上下方向に移動可能に支持されている。 The annular frame F placed on the placement surface 56 a is fixed to the frame holding means 56 by a clamp 58. The frame holding means 52 configured as described above is supported by the tape extending means 54 so as to be movable in the vertical direction.
テープ拡張手段54は、環状のフレーム保持部材56の内側に配設された拡張ドラム60を具備している。拡張ドラム60の上端は蓋62で閉鎖されている。この拡張ドラム60は、環状フレームFの内径より小さく、環状フレームFに装着されたダイシングテープTに貼着されるWL-CSPウェーハ27の外径より大きい内径を有している。 The tape expansion means 54 includes an expansion drum 60 disposed inside an annular frame holding member 56. The upper end of the expansion drum 60 is closed with a lid 62. The expansion drum 60 has an inner diameter that is smaller than the inner diameter of the annular frame F and larger than the outer diameter of the WL-CSP wafer 27 attached to the dicing tape T attached to the annular frame F.
拡張ドラム60はその下端に一体的に形成された支持フランジ64を有している。テープ拡張手段54は更に、環状のフレーム保持部材56を上下方向に移動する駆動手段66を具備している。この駆動手段66は支持フランジ64上に配設された複数のエアシリンダ68から構成されており、そのピストンロッド70はフレーム保持部材56の下面に連結されている。 The expansion drum 60 has a support flange 64 integrally formed at the lower end thereof. The tape expanding means 54 further includes driving means 66 for moving the annular frame holding member 56 in the vertical direction. The driving means 66 includes a plurality of air cylinders 68 disposed on the support flange 64, and the piston rod 70 is connected to the lower surface of the frame holding member 56.
複数のエアシリンダ68から構成される駆動手段66は、環状のフレーム保持部材56を、その載置面56aが拡張ドラム60の上端である蓋62の表面と略同一高さとなる基準位置と、拡張ドラム60の上端より所定量下方の拡張位置との間で上下方向に移動する。 The driving means 66 composed of a plurality of air cylinders 68 includes an annular frame holding member 56, a reference position where the mounting surface 56a is substantially the same height as the surface of the lid 62 which is the upper end of the expansion drum 60, and an expansion. It moves in the vertical direction between the extended position below the upper end of the drum 60 by a predetermined amount.
以上のように構成された分割装置50を用いて実施するWL-CSPウェーハ27の分割工程について図7を参照して説明する。図7(A)に示すように、WL-CSPウェーハ27をダイシングテープTを介して支持した環状フレームFを、フレーム保持部材56の載置面56a上に載置し、クランプ58によってフレーム保持部材56に固定する。この時、フレーム保持部材56はその載置面56aが拡張ドラム60の上端と略同一高さとなる基準位置に位置付けられる。 A dividing process of the WL-CSP wafer 27 performed using the dividing apparatus 50 configured as described above will be described with reference to FIG. As shown in FIG. 7A, an annular frame F that supports a WL-CSP wafer 27 via a dicing tape T is placed on a placement surface 56 a of a frame holding member 56, and the frame holding member 56 is clamped by a clamp 58. 56. At this time, the frame holding member 56 is positioned at a reference position where the placement surface 56 a is substantially the same height as the upper end of the expansion drum 60.
次いで、エアシリンダ68を駆動してフレーム保持部材56を図7(B)に示す拡張位置に下降する。これにより、フレーム保持部材56の載置面56a上に固定されている環状フレームFを下降するため、環状フレームFに装着されたダイシングテープTは拡張ドラム60の上端縁に当接して主に半径方向に拡張される。 Next, the air cylinder 68 is driven to lower the frame holding member 56 to the extended position shown in FIG. As a result, the annular frame F fixed on the mounting surface 56a of the frame holding member 56 is lowered, so that the dicing tape T attached to the annular frame F abuts on the upper end edge of the expansion drum 60 and mainly has a radius. Expanded in the direction.
その結果、ダイシングテープTに貼着されているWL-CSPウェーハ27には放射状に引っ張り力が作用する。このようにWL-CSPウェーハ27に放射状に引っ張り力が作用すると、分割予定ライン13に沿ってデバイスウェーハ11中に形成された改質層29a及び封止材23中に形成された改質層29bが分割起点となってWL-CSPウェーハ27が分割予定ライン13に沿って図8の拡大断面図に示すように割断され、表面が封止材23によって封止された個々のデバイスチップ31に分割される。 As a result, a tensile force acts radially on the WL-CSP wafer 27 adhered to the dicing tape T. Thus, when a tensile force acts radially on the WL-CSP wafer 27, the modified layer 29 a formed in the device wafer 11 along the scheduled division line 13 and the modified layer 29 b formed in the sealing material 23. Is divided into individual device chips 31 whose surface is sealed by the sealing material 23, as shown in the enlarged sectional view of FIG. Is done.
11 デバイスウェーハ
13 分割予定ライン
14 撮像ユニット
15 デバイス
16 レーザーヘッド(集光器)
21 金属ポスト
23 封止材
25 バンプ
27 WL-CSPウェーハ
29,29a,29b 改質層
31 デバイスチップ
50 分割装置
11 Device wafer 13 Scheduled division line 14 Imaging unit 15 Device 16 Laser head (condenser)
21 Metal Post 23 Sealing Material 25 Bump 27 WL-CSP Wafer 29, 29a, 29b Modified Layer 31 Device Chip 50 Dividing Device
Claims (2)
該ウェーハの表面側から赤外線撮像手段によって該封止材を透過して該デバイスウェーハの表面側を撮像してアライメントマークを検出し、該アライメントマークに基づいてレーザー加工すべき該分割予定ラインを検出するアライメント工程と、
該アライメント工程を実施した後、該デバイスウェーハ及び該封止材に対して透過性を有する波長のレーザービームの集光点を該デバイスウェーハ又は該封止材の内部に位置付けて、該ウェーハの表面側から該分割予定ラインに沿ってレーザービームを照射して、該デバイスウェーハ及び該封止材の内部に改質層を形成する改質層形成工程と、
該改質層形成工程を実施した後、該デバイスウェーハ及び該封止材に外力を付与して該改質層を分割起点として表面が該封止材によって封止された個々のデバイスチップに分割する分割工程と、を備え、
該封止材は該赤外線撮像手段が受光する赤外線が透過するような透過性を有することを特徴とするウェーハの加工方法。 The surface of the device wafer on which the device is formed in the chip area partitioned by the plurality of division lines formed intersecting the surface is sealed with a sealing material, and a plurality of each in the chip area of the sealing material A method of processing a wafer on which a bump is formed,
An infrared imaging means transmits the sealing material from the surface side of the wafer, images the surface side of the device wafer, detects an alignment mark, and detects the division line to be laser processed based on the alignment mark Alignment step to perform,
After performing the alignment step, a condensing point of a laser beam having a wavelength transmissive to the device wafer and the encapsulant is positioned inside the device wafer or the encapsulant, and the surface of the wafer A modified layer forming step of forming a modified layer in the device wafer and the sealing material by irradiating a laser beam along the division line from the side,
After performing the modified layer forming step, an external force is applied to the device wafer and the sealing material, and the modified layer is divided into individual device chips whose surfaces are sealed by the sealing material using the modified layer as a starting point. A splitting process,
The method for processing a wafer, wherein the sealing material is transparent so that infrared rays received by the infrared imaging means are transmitted.
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SG10201807858QA SG10201807858QA (en) | 2017-09-19 | 2018-09-12 | Processing method for wafer |
CN201811069093.8A CN109524354A (en) | 2017-09-19 | 2018-09-13 | The processing method of chip |
TW107132237A TWI772519B (en) | 2017-09-19 | 2018-09-13 | Wafer Processing Method |
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