JP2019036784A - Electronic component and method of manufacturing the same - Google Patents

Abstract

To suppress foreign matter from entering a gap.SOLUTION: An electronic component includes: a substrate 10 which has a first area and a second area surrounding the first area in a plan view on a principal surface, and in which a step 54 is provided between the first area and the second area, the first area having a thickness greater than that of the second area; a device chip 11 mounted on the first area using a bump so as to face the substrate with a gap sandwiched therebetween; and a sealing portion 30 provided to surround the device chip and joined to the second area while not joined to the first area.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic component and a method for manufacturing the same, and more particularly to an electronic component in which a device chip faces a substrate with a gap interposed therebetween and a method for manufacturing the same.

  As a device chip packaging method, there is known a method in which a device chip is flip-chip mounted on a substrate and a sealing portion is provided so as to surround the device chip (for example, Patent Documents 1 to 3). The lower surface of the device chip provided with the functional element is opposed to the upper surface of the substrate with a gap interposed therebetween.

JP 2006-203149 A JP 2010-147348 A Japanese Patent Laid-Open No. 2006-201780

  However, the material of the sealing portion may enter the gap between the substrate and the device chip. If it is going to suppress the penetration | invasion of the material of a sealing part, the space | interval of a sealing part and a device chip will be expanded, and an electronic component will enlarge.

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress entry of foreign matter into the gap.

  The present invention has, on the main surface, a first region and a second region surrounding the first region in plan view, and a step is provided between the first region and the second region, The first region has a thickness larger than that of the second region, a device chip mounted using bumps so as to face each other with a gap on the first region, and a thickness surrounding the device chip. An electronic component including: a sealing portion that is bonded to the second region and is not bonded to the first region.

  The said structure WHEREIN: The metal film provided in the side surface of the said level | step difference can be comprised, and the said sealing part can be set as the structure which consists of solder and joins the said metal film.

  The said structure WHEREIN: The metal film provided on the side surface of the said level | step difference and the said 2nd area | region can be comprised, and the said sealing part can be set as the structure joined to the said metal film consisting of solder.

  The said structure WHEREIN: It can be set as the structure which comprises the lid provided on the said device chip and the said sealing part.

  The said structure WHEREIN: The said device chip can be set as the structure provided with the functional element which opposes the said 1st area | region on both sides of a space | gap.

  In the above configuration, the functional element may be an elastic wave element.

  The present invention has, on the main surface, a first region and a second region surrounding the first region in plan view, and a step is provided between the first region and the second region, Mounting a device chip using bumps on a substrate having a thickness in the first region larger than that in the second region so as to oppose the first region with a gap interposed therebetween, enclosing the device chip, Joining the two regions and forming a sealing portion so as not to join the first region.

  In the above configuration, the substrate includes a metal film provided on a side surface of the step and the second region, the sealing portion is made of solder, and the step of forming the sealing portion includes the sealing It can be set as the structure including the process of forming the said sealing part so that a part may join to the said metal film.

  According to the present invention, entry of foreign matter into the gap can be suppressed.

FIG. 1A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 1B is a plan view of the substrate. FIG. 2A is a plan view illustrating an example of a functional element in the first embodiment, and FIG. 2B is a cross-sectional view illustrating another example of the functional element. FIG. 3A to FIG. 3D are cross-sectional views (part 1) illustrating the method of manufacturing the electronic component according to the first embodiment. 4A to 4C are cross-sectional views (part 2) illustrating the method of manufacturing the electronic component according to the first embodiment. FIG. 5 is a cross-sectional view of an electronic component according to Comparative Example 1. FIG. 6A and FIG. 6B are enlarged views of cross sections of Comparative Example 1 and Example 1, respectively.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 1B is a plan view of the substrate 20. As shown in FIG. 1A, the device chip 11 is flip-chip mounted on the substrate 20. The substrate 20 has laminated insulating layers 20a and 20b. The insulating layers 20a and 20b are, for example, ceramic layers or resin layers. Wirings 22c and 24 are provided on the upper surfaces of the insulating layers 20a and 20b, respectively. Terminals 26 are provided on the lower surface of the insulating layer 20a. The terminal 26 is a hood pad for connecting the functional element 12 to the outside. Via wirings 22a and 22b penetrating the insulating layers 20a and 20b are provided. The via wirings 22a and 22b and the wiring 22c form an internal wiring 22. The internal wiring 22 electrically connects the wiring 24 and the terminal 26. The via wirings 22a and 22b, the wirings 22c and 24, and the terminal 26 are metal layers such as a copper layer, a gold layer, an aluminum layer, and / or a nickel layer, for example.

  The upper surface of the substrate 20 has regions 50 and 52. As shown in FIG. 1B, the region 50 is a central region of the substrate 20. The region 52 is provided in an annular shape so as to surround the region 50. A step 54 is formed between the regions 50 and 52. The thickness of the substrate 20 in the region 50 is larger than the thickness of the substrate 20 in the region 52. A metal film 28 is provided on the side surfaces of the region 52 and the step 54. The metal film 28 is, for example, a gold film and / or a nickel film.

  As shown in FIG. 1A, the functional element 12 and the wiring 14 are provided on the lower surface of the substrate 10. The device chip 11 includes a substrate 10, functional elements 12 and wirings 14. The wiring 14 is a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 10 is flip-chip mounted (face-down mounted) on a region 50 on the upper surface of the substrate 20 via bumps 36. The bump 36 is, for example, a gold bump, a solder bump, or a copper bump. The bump 36 is bonded to the wirings 14 and 24. The functional element 12 is opposed to the upper surface of the substrate 20 through the gap 38.

  A sealing portion 30 is provided so as to surround the device chip 11. The sealing part 30 is, for example, a metal such as solder or a resin. The sealing portion 30 is bonded to the metal film 28 formed in the region 52 and the step 54 on the upper surface of the substrate 20. A lid 32 is provided on the upper surfaces of the sealing unit 30 and the device chip 11. The lid 32 is, for example, a metal plate such as a Kovar plate or an insulating plate. A protective film 34 is provided so as to cover the lid 32 and the sealing portion 30. The protective film 34 is a metal film such as a nickel film or an insulating film. A sealing unit 30 may be provided on the device chip 11. The lid 32 may not be provided.

  The terminal 26 is electrically connected to the functional element 12 via the internal wiring 22, the wiring 24, the bump 36, and the wiring 14. The metal film 28 is electrically connected to the ground terminal of the terminals 26 via the internal wiring 22. Thereby, the sealing part 30 is grounded.

  FIG. 2A is a plan view illustrating an example of a functional element in the first embodiment, and FIG. 2B is a cross-sectional view illustrating another example of the functional element. 2A and 2B are examples in which the functional element 12 is a surface acoustic wave resonator and a piezoelectric thin film resonator, respectively.

  As shown in FIG. 2A, an IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 10. The IDT 40 has a pair of comb electrodes 40a facing each other. The comb-shaped electrode 40a includes a plurality of electrode fingers 40b and a bus bar 40c that connects the plurality of electrode fingers 40b. The reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites surface acoustic waves on the substrate 10. The substrate 10 is a piezoelectric substrate such as a lithium tantalate substrate or a lithium niobate substrate. The IDT 40 and the reflector 42 are made of, for example, an aluminum film or a copper film. The substrate 20 may be bonded to a support substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate. A protective film or a temperature compensation film that covers the IDT 40 and the reflector 42 may be provided. In this case, it functions as the functional element 12 including the protective film or the temperature compensation film.

  As shown in FIG. 2B, a piezoelectric film 46 is provided on the substrate 10. A lower electrode 44 and an upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 10. The lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. The lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film, for example. The piezoelectric film 46 is, for example, an aluminum nitride film. The substrate 10 is, for example, a silicon substrate or a semiconductor substrate such as gallium arsenide, or an insulating substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a glass substrate. As shown in FIGS. 2A and 2B, the functional element 12 includes an electrode for exciting an elastic wave. For this reason, the functional element 12 is covered with the air gap 38 so as not to limit the vibration of the elastic wave.

[Production Method of Example 1]
FIG. 3A to FIG. 4C are cross-sectional views illustrating the method for manufacturing the electronic component according to the first embodiment. As shown in FIG. 3A, a substrate 20 provided with an internal wiring 22, a wiring 24, and a terminal 26 is prepared.

  As shown in FIG. 3B, a groove 60 is formed on the upper surface of the substrate 20 so as to surround the region 50 where the device chip 11 is mounted. The bottom surface of the groove 60 becomes the region 52. The groove 60 is formed by, for example, half dicing using a dicing blade. The depth of the groove 60 may be larger or smaller than the thickness of the insulating layer 20b. The groove 60 may be formed using an etching method.

  As shown in FIG. 3C, the metal film 28 is formed on the bottom surface and side surfaces of the groove 60. The metal film 28 is, for example, a gold film, a nickel film, or a gold film from the substrate 20 side. The metal film 28 is formed using, for example, a plating method. When the metal film 28 is formed by a plating method, the plating layer may be formed after the seed layer is formed. The uppermost surface of the metal film 28 is preferably a gold film having good wettability with solder. It is preferable to provide a barrier layer such as a nickel film for suppressing mutual diffusion between the gold film and the internal wiring 22.

  As shown in FIG. 3D, the device chip 11 is flip-chip mounted on the substrate 20 using the bumps 36. A gap 38 is formed between the region 50 on the upper surface of the substrate 20 and the functional element 12 of the device chip 11.

  As shown in FIG. 4A, a lid 32 having a solder 31 provided on the lower surface is disposed above the device chip 11. The solder 31 is, for example, SnAg solder. The solder 31 is heated above the melting point of the solder 31. The upper surface of the lid 32 is pressed against the device chip 11 as indicated by an arrow 58.

  As shown in FIG. 4B, the solder 31 is melted and joined to the metal film 28 on the inner surface of the groove 60. The metal film 28 is not provided in the region 50 on the upper surface of the substrate 20. For this reason, the region 50 has poor wettability of the solder 31. Therefore, the solder 31 is not joined to the region 50. The sealing portion 30 is formed by the solder 31.

  As shown in FIG. 4C, the lid 32, the sealing portion 30, and the substrate 20 are cut using, for example, a dicing method like a cutting region 62. Thereafter, a protective film 34 is formed so as to cover the lid 32 and the sealing portion 30. The protective film 34 is formed using, for example, a plating method. Thus, the electronic component shown in FIG. 1A is completed.

[Comparative Example 1]
FIG. 5 is a cross-sectional view of an electronic component according to Comparative Example 1. As shown in FIG. 5, in Comparative Example 1, the upper surface of the substrate 20 is flat and no step 54 is provided. The metal film 28 is formed on the upper surface of the substrate 20 having the same height as the wiring 24. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  FIG. 6A and FIG. 6B are enlarged views of cross sections of Comparative Example 1 and Example 1, respectively. As shown in FIG. 6A, in Comparative Example 1, the metal film 28 is provided flat on the upper surface of the substrate 20. The angle formed between the side surface of the sealing unit 30 and the upper surface of the substrate 20 is θ1. The angle θ1 depends on the surface tension of the melted sealing portion 30 on the surface of the metal film 28 in FIGS. 4A and 4B. For example, when the sealing portion 30 is SnAg solder and the uppermost surface of the metal film 28 is a gold film, the angle θ1 is 30 ° to 60 °. When the angle θ1 is small, the distance between the side surface of the sealing portion 30 and the upper surface of the substrate 20 is narrowed. For this reason, the material (for example, solder) of the sealing part 30 easily enters the gap 38 as a foreign substance. In addition, the material of the sealing portion 30 easily enters the gap 38 during reflow or the like when mounting the electronic component. In order to prevent foreign matter from entering between the device chip 11 and the substrate 20, the distance L1 between the device chip 11 and the metal film 28 is increased. This increases the size of the electronic component.

  As shown in FIG. 6B, in Example 1, the metal film 28 is provided on the side surface of the step 54. For example, if the angle θ3 formed by the region 52 and the side surface of the step 54 is 90 °, the side surface of the sealing portion 30 should be provided as indicated by the broken line 64 from the surface tension of the sealing portion 30. However, since stress is applied inward to the sealing portion 30, the side surface of the sealing portion 30 is nearly perpendicular to the upper surface of the substrate 20. As an example, the angle θ2 formed by the upper surface of the substrate 20 is 40 ° to 70 °. Thus, the angle θ2 is larger than the angle θ1 of the comparative example 1. For this reason, it becomes difficult for the material of the sealing portion 30 to enter the gap 38. Thereby, the distance L2 between the device chip 11 and the metal film 28 can be reduced, and the electronic component can be miniaturized.

  When the substrate 20 is a multilayer substrate, the thickness of the insulating layer 20b is, for example, 50 μm to 70 μm. When the groove 60 is formed by half dicing, the depth D1 of the groove 60 may be larger or smaller than the thickness of the uppermost insulating layer 20b. If the depth of the groove 60 is small, the angle θ2 cannot be increased. Therefore, the depth D1 of the groove 60 is preferably 10 μm or more, preferably 20 μm or more, and more preferably 30 μm or more. If the depth of the groove is large, the number of processing steps increases. Therefore, the depth of the groove 60 is preferably 100 μm or less, and more preferably 70 μm or less. The thickness of the metal film 28 is, for example, 1 μm to 20 μm, which is sufficiently smaller than the depth D1. The distance between the upper surface of the substrate 20 and the lower surface of the device chip 11 is, for example, 10 μm to 20 μm.

  If the angle θ3 is too large, the angle θ2 becomes small. Therefore, the angle θ3 is preferably 135 ° or less, and more preferably 120 ° or less. When the groove 60 is formed by half dicing, θ3 becomes approximately 90 °. When the groove 60 is formed using an etching method, the angle θ3 becomes larger than 90 °. The distance L2 between the device chip 11 and the metal film 28 is preferably 100 μm or less from the viewpoint of miniaturization, and is preferably 5 μm or more so that foreign matter does not enter the gap 38.

  Although the case where the sealing part 30 is made of solder has been described as an example of FIGS. 6A and 6B, the sealing part 30 is bonded to the substrate 20 even when the sealing part 30 is made of resin. The resin easily enters the gap 38. Therefore, the sealing part 30 may be made of resin.

  According to the first embodiment, the upper surface (main surface) of the substrate 20 includes the region 50 (first region) and the region 52 (second region) surrounding the region 50 in plan view. A step 54 is provided between the region 50 and the region 52. The thickness of the substrate 20 in the region 50 is larger than the thickness of the substrate 20 in the region 52. The device chip 11 is mounted on the region 50 using the bumps 36 so as to face each other with the gap 38 interposed therebetween. The sealing unit 30 is provided so as to surround the device chip 11, is bonded to the region 52, and is not bonded to the region 50. Thereby, it can suppress that a foreign material penetrate | invades into the space | gap 38. FIG.

  The metal film 28 is provided on the side surface of the step 54. The sealing part 30 is made of solder and joined to the metal film 28. Thereby, it can suppress that the sealing part 30 wraps around the device chip 11 with the surface tension of solder. Therefore, it is possible to further suppress the entry of foreign matter into the gap 38. The metal film 28 may be provided on the region 52. Thereby, the sealing portion 30 is firmly bonded to the region 52.

  The lid 32 is provided on the device chip 11 and the sealing portion 30. Thereby, the gap 38 can be hermetically sealed by the sealing portion 30 and the lid 32.

  The device chip 11 includes a functional element 12 that faces the region 50 with the gap 38 interposed therebetween. Thereby, the functional element 12 can be sealed in the gap 38.

  The functional element 12 is an acoustic wave element. Since the acoustic wave element is surrounded by the gap 38, the vibration of the acoustic wave element is not limited.

  In the first embodiment, an acoustic wave element is described as an example of the functional element 12. However, the functional element 12 may be a passive element such as an inductor or a capacitor, an active element including a transistor, or a MEMS (Micro Electro Mechanical Systems) element. Each functional element 12 may form an elastic wave filter. The functional element 12 may form a multiplexer such as a duplexer, a triplexer, or a quadplexer.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10, 20 Board | substrate 12 Functional element 14, 24 Wiring 28 Metal film 30 Sealing part 32 Lid 34 Protective film

Claims (8)

The main surface has a first region and a second region surrounding the first region in plan view, and a step is provided between the first region and the second region. A substrate having a thickness greater than that in the second region;
A device chip mounted using bumps so as to face each other with a gap on the first region;
A sealing portion provided to surround the device chip, bonded to the second region, and not bonded to the first region;
An electronic component comprising: Comprising a metal film provided on the side surface of the step;
The electronic component according to claim 1, wherein the sealing portion is made of solder and is joined to the metal film. Comprising a metal film provided on the side surface of the step and the second region;
The electronic component according to claim 1, wherein the sealing portion is made of solder and is joined to the metal film.   The electronic component according to claim 1, further comprising a lid provided on the device chip and the sealing portion.   5. The electronic component according to claim 1, wherein the device chip includes a functional element facing the first region with a gap interposed therebetween.   The electronic component according to claim 5, wherein the functional element is an acoustic wave element. The main surface has a first region and a second region surrounding the first region in plan view, and a step is provided between the first region and the second region. A step of mounting a device chip using bumps so that the thickness is larger than the thickness in the second region, and the gap is opposed to the first region;
Forming a sealing portion so as to surround the device chip, to be bonded to the second region, and not to be bonded to the first region;
Of electronic parts including The substrate has a metal film provided on a side surface of the step and the second region,
The sealing portion is made of solder,
The method of manufacturing an electronic component according to claim 7, wherein the step of forming the sealing portion includes a step of forming the sealing portion so that the sealing portion is bonded to the metal film.

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