JP6942004B2 - Electronic components and their manufacturing methods - Google Patents

Description

The present invention relates to an electronic component and a method for manufacturing the same, and relates to an electronic component in which a device chip faces a substrate with a gap sandwiched between the electronic component and a method for manufacturing the electronic component.

As a method for packaging a device chip, there is known a method in which a device chip is flip-chip mounted on a substrate and a sealing portion is provided so as to surround the device chip (for example, Patent Documents 1 to 3). The lower surface of the device chip provided with the functional element faces the upper surface of the substrate with a gap in between.

Japanese Unexamined Patent Publication No. 2006-203149 Japanese Unexamined Patent Publication No. 2010-147348 Japanese Unexamined Patent Publication No. 2016-2017780

However, the material of the sealing portion may enter the gap between the substrate and the device chip. If an attempt is made to suppress the intrusion of the material in the sealing portion, the distance between the sealing portion and the device chip is widened, and the electronic component becomes large.

The present invention has been made in view of the above problems, and an object of the present invention is to suppress the invasion of foreign matter into the voids.

The present invention has a first region and a second region surrounding the first region in a plan view on a main surface, and a step is provided between the first region and the second region. A substrate whose thickness in the first region is larger than the thickness in the second region, a device chip mounted on the first region using bumps so as to sandwich a gap, and a metal provided on the side surface of the step. a membrane, made of solder, the provided so as to surround the device chip, joined to the second region and the metal film, anda sealing portion which is not joined to the first region, the sealing portion The side surface on the void side is an electronic component made of the solder and inclined toward the device chip side.

In the above configuration, the angle formed by the side surface of the sealing portion on the void side and the upper surface of the substrate in the first region can be 40 ° or more and 70 ° or less .

In the above configuration, the metal film may be configured being provided et the sides and the second region of the step.

In the above configuration, the lids provided on the device chip and the sealing portion can be provided.

In the above configuration, the device chip may include a functional element that faces the first region with a gap in between.

In the above configuration, the functional element may be an elastic wave element.

The present invention has a first region and a second region surrounding the first region in a plan view on a main surface, and a step is provided between the first region and the second region. A step of mounting a device chip using bumps on the first region of a substrate whose thickness in the first region is larger than the thickness in the second region so as to face each other with a gap sandwiched between them, and a step of surrounding the device chip and the first. bonded to the second region, wherein the first region viewed including a step of forming a seal to prevent bonding, the substrate has a metal film provided on a side surface of the step, the sealing The portion is made of solder, and the step of forming the sealing portion includes a step of forming the sealing portion so that the sealing portion is bonded to the metal film, and the side surface of the sealing portion on the void side. Is a method for manufacturing an electronic component made of the solder and inclined toward the device chip side.

In the above configuration, the metal film may be configured that provided on the side surface and the second region of the step.

According to the present invention, it is possible to suppress the invasion of foreign matter into the voids.

FIG. 1A is a cross-sectional view of an electronic component according to the first embodiment, and FIG. 1B is a plan view of a substrate. FIG. 2A is a plan view showing an example of the functional element in the first embodiment, and FIG. 2B is a cross-sectional view showing another example of the functional element. 3 (a) to 3 (d) are cross-sectional views (No. 1) showing a method of manufacturing an electronic component according to the first embodiment. 4 (a) to 4 (c) are cross-sectional views (No. 2) showing a method of manufacturing an electronic component according to the first embodiment. FIG. 5 is a cross-sectional view of the electronic component according to Comparative Example 1. 6 (a) and 6 (b) are enlarged views of cross sections of Comparative Example 1 and Example 1, respectively.

Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 1B is a plan view of the substrate 20. As shown in FIG. 1A, the device chip 11 is flip-chip mounted on the substrate 20. The substrate 20 has laminated insulating layers 20a and 20b. The insulating layers 20a and 20b are, for example, a ceramic layer or a resin layer. Wiring 22c and 24 are provided on the upper surfaces of the insulating layers 20a and 20b, respectively. The terminal 26 is provided on the lower surface of the insulating layer 20a. The terminal 26 is a hood pad for connecting the functional element 12 to the outside. Via wirings 22a and 22b that penetrate the insulating layers 20a and 20b are provided. The via wirings 22a and 22b and the wiring 22c form the internal wiring 22. The internal wiring 22 electrically connects the wiring 24 and the terminal 26. The via wires 22a, 22b, wires 22c, 24 and terminal 26 are metal layers such as, for example, a copper layer, a gold layer, an aluminum layer and / or a nickel layer.

The upper surface of the substrate 20 has regions 50 and 52. As shown in FIG. 1B, the region 50 is the central region of the substrate 20. The region 52 is provided in a ring shape so as to surround the region 50. A step 54 is formed between the regions 50 and 52. The thickness of the substrate 20 in the region 50 is larger than the thickness of the substrate 20 in the region 52. A metal film 28 is provided on the side surfaces of the region 52 and the step 54. The metal film 28 is, for example, a gold film and / or a nickel film.

As shown in FIG. 1A, the functional element 12 and the wiring 14 are provided on the lower surface of the substrate 10. The device chip 11 includes a substrate 10, a functional element 12, and wiring 14. The wiring 14 is a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 10 is flip-chip mounted (face-down mounted) in the region 50 on the upper surface of the substrate 20 via the bump 36. The bump 36 is, for example, a gold bump, a solder bump or a copper bump. The bump 36 joins the wires 14 and 24. The functional element 12 faces the upper surface of the substrate 20 via the gap 38.

A sealing portion 30 is provided so as to surround the device chip 11. The sealing portion 30 is, for example, a metal or resin such as solder. The sealing portion 30 is joined to the metal film 28 formed in the region 52 on the upper surface of the substrate 20 and the step 54. A lid 32 is provided on the upper surfaces of the sealing portion 30 and the device chip 11. The lid 32 is a metal plate such as a Kovar plate or an insulating plate. A protective film 34 is provided so as to cover the lid 32 and the sealing portion 30. The protective film 34 is a metal film such as a nickel film or an insulating film. The sealing portion 30 may be provided on the device chip 11. The lid 32 may not be provided.

The terminal 26 is electrically connected to the functional element 12 via the internal wiring 22, the wiring 24, the bump 36, and the wiring 14. The metal film 28 is electrically connected to the ground terminal of the terminals 26 via the internal wiring 22. As a result, the sealing portion 30 is grounded.

FIG. 2A is a plan view showing an example of the functional element in the first embodiment, and FIG. 2B is a cross-sectional view showing another example of the functional element. 2 (a) and 2 (b) are examples in which the functional element 12 is a surface acoustic wave resonator and a piezoelectric thin film resonator, respectively.

As shown in FIG. 2A, an IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 10. The IDT 40 has a pair of comb-shaped electrodes 40a facing each other. The comb-shaped electrode 40a has a plurality of electrode fingers 40b and a bus bar 40c for connecting the plurality of electrode fingers 40b. Reflectors 42 are provided on both sides of the IDT 40. IDT40 excites surface acoustic waves on the substrate 10. The substrate 10 is a piezoelectric substrate such as a lithium tantalate substrate or a lithium niobate substrate. The IDT 40 and the reflector 42 are formed of, for example, an aluminum film or a copper film. The substrate 20 may be bonded to a support substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate. A protective film or a temperature compensation film may be provided to cover the IDT 40 and the reflector 42. In this case, it functions as a functional element 12 including a protective film or a temperature compensation film.

As shown in FIG. 2B, the piezoelectric film 46 is provided on the substrate 10. The lower electrode 44 and the upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 10. The lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. The lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film. The piezoelectric film 46 is, for example, an aluminum nitride film. The substrate 10 is, for example, a silicon substrate, a semiconductor substrate such as gallium arsenide, or an insulating substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a glass substrate. As shown in FIGS. 2A and 2B, the functional element 12 includes an electrode that excites an elastic wave. Therefore, the functional element 12 is covered with a gap 38 so as not to limit the vibration of the elastic wave.

[Manufacturing method of Example 1]
3 (a) to 4 (c) are cross-sectional views showing a method of manufacturing an electronic component according to the first embodiment. As shown in FIG. 3A, the substrate 20 provided with the internal wiring 22, the wiring 24, and the terminal 26 is prepared.

As shown in FIG. 3B, a groove 60 is formed on the upper surface of the substrate 20 so as to surround the region 50 on which the device chip 11 is mounted. The bottom surface of the groove 60 becomes the region 52. The groove 60 is formed by, for example, half dicing using a dicing blade. The depth of the groove 60 may be larger or smaller than the thickness of the insulating layer 20b. The groove 60 may be formed by using an etching method.

As shown in FIG. 3C, a metal film 28 is formed on the bottom surface and the side surface of the groove 60. The metal film 28 is, for example, a gold film, a nickel film, and a gold film from the substrate 20 side. The metal film 28 is formed by, for example, a plating method. When the metal film 28 is formed by the plating method, the plating layer may be formed after the seed layer is formed. The uppermost surface of the metal film 28 is preferably a gold film or the like having good wettability with solder. It is preferable to provide a barrier layer such as a nickel film between the gold film and the internal wiring 22 to suppress mutual diffusion.

As shown in FIG. 3D, the device chip 11 is flip-chip mounted on the substrate 20 using the bump 36. A gap 38 is formed between the region 50 on the upper surface of the substrate 20 and the functional element 12 of the device chip 11.

As shown in FIG. 4A, a lid 32 provided with a solder 31 on the lower surface is arranged above the device chip 11. The solder 31 is, for example, SnAg solder. The solder 31 is heated to a temperature equal to or higher than the melting point of the solder 31. The upper surface of the lid 32 is pressed against the device chip 11 as shown by the arrow 58.

As shown in FIG. 4B, the solder 31 is melted and joined to the metal film 28 on the inner surface of the groove 60. The metal film 28 is not provided in the region 50 on the upper surface of the substrate 20. Therefore, the region 50 has poor wettability of the solder 31. Therefore, the solder 31 is not bonded to the region 50. The sealing portion 30 is formed by the solder 31.

As shown in FIG. 4C, the lid 32, the sealing portion 30, and the substrate 20 are cut as shown in the cutting region 62 by using, for example, a dicing method. After that, the protective film 34 is formed so as to cover the lid 32 and the sealing portion 30. The protective film 34 is formed by, for example, a plating method. As a result, the electronic component shown in FIG. 1A is completed.

[Comparative Example 1]
FIG. 5 is a cross-sectional view of the electronic component according to Comparative Example 1. As shown in FIG. 5, in Comparative Example 1, the upper surface of the substrate 20 is flat and no step 54 is provided. The metal film 28 is formed on the upper surface of the substrate 20 at the same height as the wiring 24. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

6 (a) and 6 (b) are enlarged views of cross sections of Comparative Example 1 and Example 1, respectively. As shown in FIG. 6A, in Comparative Example 1, the metal film 28 is provided flat on the upper surface of the substrate 20. The angle formed by the side surface of the sealing portion 30 and the upper surface of the substrate 20 is θ1. The angle θ1 depends on the surface tension of the molten sealing portion 30 on the surface of the metal film 28 in FIGS. 4 (a) and 4 (b). For example, when the sealing portion 30 is SnAg solder and the uppermost surface of the metal film 28 is a gold film, the angle θ1 is 30 ° to 60 °. When the angle θ1 is small, the distance between the side surface of the sealing portion 30 and the upper surface of the substrate 20 becomes narrow. Therefore, the material (for example, solder) of the sealing portion 30 easily enters the void 38 as a foreign substance. In addition, the material of the sealing portion 30 easily penetrates into the gap 38 during reflow or the like when mounting an electronic component. If foreign matter is prevented from entering between the device chip 11 and the substrate 20, the distance L1 between the device chip 11 and the metal film 28 will be increased. As a result, the size of the electronic component becomes large.

As shown in FIG. 6B, in the first embodiment, the metal film 28 is provided on the side surface of the step 54. For example, assuming that the angle θ3 formed by the region 52 and the side surface of the step 54 is 90 °, the side surface of the sealing portion 30 should be provided as shown by the broken line 64 from the surface tension of the sealing portion 30. However, since stress is applied inward to the sealing portion 30, the side surface of the sealing portion 30 is close to perpendicular to the upper surface of the substrate 20. As an example, the angle θ2 formed by the upper surface of the substrate 20 is 40 ° to 70 °. In this way, the angle θ2 is larger than the angle θ1 of Comparative Example 1. Therefore, the material of the sealing portion 30 is less likely to enter the void 38. As a result, the distance L2 between the device chip 11 and the metal film 28 can be reduced, and the electronic components can be miniaturized.

When the substrate 20 is a multilayer substrate, the thickness of the insulating layer 20b is, for example, 50 μm to 70 μm. When the groove 60 is formed by half dicing, the depth D1 of the groove 60 may be larger or smaller than the thickness of the uppermost insulating layer 20b. If the depth of the groove 60 is small, the angle θ2 cannot be increased. Therefore, the depth D1 of the groove 60 is preferably 10 μm or more, preferably 20 μm or more, and even more preferably 30 μm or more. If the groove depth is large, the processing man-hours will increase. Therefore, the depth of the groove 60 is preferably 100 μm or less, more preferably 70 μm or less. The film thickness of the metal film 28 is, for example, 1 μm to 20 μm, which is sufficiently smaller than the depth D1. The distance between the upper surface of the substrate 20 and the lower surface of the device chip 11 is, for example, 10 μm to 20 μm.

If the angle θ3 is too large, the angle θ2 becomes small. Therefore, the angle θ3 is preferably 135 ° or less, more preferably 120 ° or less. When the groove 60 is formed by half dicing, θ3 becomes approximately 90 °. When the groove 60 is formed by the etching method, the angle θ3 becomes larger than 90 °. The distance L2 between the device chip 11 and the metal film 28 is preferably 100 μm or less from the viewpoint of miniaturization, and is preferably 5 μm or more so that foreign matter does not enter the gap 38.

Although the case where the sealing portion 30 is made of solder has been described as an example of FIGS. 6A and 6B, when the sealing portion 30 is bonded to the substrate 20 even when the sealing portion 30 is made of resin. The resin easily penetrates into the void 38. Therefore, the sealing portion 30 may be made of resin.

According to the first embodiment, the upper surface (main surface) of the substrate 20 has a region 50 (first region) and a region 52 (second region) surrounding the region 50 in a plan view. A step 54 is provided between the area 50 and the area 52. The thickness of the substrate 20 in the region 50 is larger than the thickness of the substrate 20 in the region 52. The device chip 11 is mounted on the region 50 by using bumps 36 so as to sandwich the gap 38 and face each other. The sealing portion 30 is provided so as to surround the device chip 11 and is bonded to the region 52 and not to the region 50. As a result, it is possible to prevent foreign matter from entering the gap 38.

The metal film 28 is provided on the side surface of the step 54. The sealing portion 30 is made of solder and is joined to the metal film 28. As a result, it is possible to prevent the sealing portion 30 from wrapping around to the device chip 11 due to the surface tension of the solder. Therefore, the invasion of foreign matter into the void 38 can be further suppressed. The metal film 28 may be provided on the region 52. As a result, the sealing portion 30 is firmly joined to the region 52.

The lid 32 is provided on the device chip 11 and on the sealing portion 30. As a result, the void 38 can be hermetically sealed by the sealing portion 30 and the lid 32.

The device chip 11 includes a functional element 12 that faces the region 50 with the gap 38 interposed therebetween. As a result, the functional element 12 can be sealed in the gap 38.

The functional element 12 is an elastic wave element. Since the elastic wave element is surrounded by the void 38, the vibration of the elastic wave element is not limited.

In the first embodiment, an elastic wave element has been described as an example of the functional element 12, but the functional element 12 may be a passive element such as an inductor or a capacitor, an active element including a transistor, or a MEMS (Micro Electro Mechanical Systems) element. Each functional element 12 may form an elastic wave filter. The functional element 12 may form a multiplexer such as a duplexer, a triplexer, or a quadplexer.

Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10, 20 Substrate 12 Functional element 14, 24 Wiring 28 Metal film 30 Sealing part 32 Lid 34 Protective film

Claims (8)

The main surface has a first region and a second region surrounding the first region in a plan view, and a step is provided between the first region and the second region in the first region. With a substrate whose thickness is larger than the thickness in the second region,
A device chip mounted on the first region using bumps so as to sandwich a gap and face each other.
A metal film provided on the side surface of the step and
A sealing portion made of solder, provided so as to surround the device chip, bonded to the second region and the metal film, and not bonded to the first region.
Equipped with
An electronic component whose side surface on the void side of the sealing portion is made of the solder and is inclined toward the device chip side. The electronic component according to claim 1 , wherein the angle formed by the side surface of the sealing portion on the void side and the upper surface of the substrate in the first region is 40 ° or more and 70 ° or less. The metal film, electronic component according to claim 1 or 2 wherein is provided et the sides and the second region of the step. The electronic component according to any one of claims 1 to 3, further comprising a lid provided on the device chip and the sealing portion. The electronic component according to any one of claims 1 to 4, wherein the device chip includes a functional element that faces the first region with a gap interposed therebetween. The electronic component according to claim 5, wherein the functional element is an elastic wave element. The main surface has a first region and a second region surrounding the first region in a plan view, and a step is provided between the first region and the second region in the first region. A step of mounting a device chip on a substrate having a thickness larger than the thickness in the second region by using bumps on the first region so as to sandwich a gap and face each other.
A step of surrounding the device chip, joining the second region, and forming a sealing portion so as not to join the first region.
Only including,
The substrate has a metal film provided on the side surface of the step.
The sealing part is made of solder.
The step of forming the sealing portion includes a step of forming the sealing portion so that the sealing portion is bonded to the metal film.
A method for manufacturing an electronic component in which the side surface of the sealing portion on the void side is made of the solder and is inclined toward the device chip side. The metal film is a side and the method of manufacturing the second electronic component according to claim 7, wherein that provided on the region of the step.

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