JP7406341B2 - Electronic components, filters and multiplexers - Google Patents

Description

The present invention relates to electronic components, filters, and multiplexers, and for example, to electronic components, filters, and multiplexers that have a sealing part.

A sealing device in which a second substrate having a functional element such as an acoustic wave device on the bottom surface is mounted on a first substrate such as a ceramic substrate, and is bonded to a metal layer provided on the first substrate surrounding the second substrate. A structure in which a functional element is sealed by a portion is known (for example, Patent Documents 1 and 2).

Japanese Patent Application Publication No. 2017-204544 Japanese Patent Application Publication No. 2019-036784

When stress such as thermal stress is applied between the first substrate and the metal layer surrounding the second substrate, the metal layer may peel off from the first substrate. For example, the adhesion between an LTCC (Low Temperature Co-fired Ceramics) substrate and a copper layer is poor, and the copper layer may peel off from the LTCC substrate. Furthermore, if the adhesion between the sealing part and the metal layer is poor, the sealing part may peel off from the metal layer. When the sealing part and/or the metal layer peels off, the airtightness of the gap sealed by the sealing part deteriorates.

The present invention has been made in view of the above problems, and an object of the present invention is to suppress deterioration of airtightness.

The present invention includes a first substrate, a second substrate disposed on the first substrate so as to face each other with a gap therebetween, and a first substrate surrounding the second substrate when the first substrate is viewed from above. a first metal layer provided on a substrate; a second metal layer provided on the first substrate surrounding the second substrate and the first metal layer and spaced from the first metal layer; An element provided on a surface of the second substrate on the first substrate side and surrounding the second substrate to seal the element and cover between the first metal layer and the second metal layer. a sealing portion provided on the first metal layer and the second metal layer; and a sealing portion provided on the first metal layer and the second metal layer from above at least one of the first metal layer and the second metal layer. The electronic component includes an insulating layer formed of a material different from that of the first substrate and provided over the surface of the first substrate in a region between the layers .

In the above structure, the first metal layer and the second metal layer may be embedded in the first substrate.

In the above structure, the first metal layer and the second metal layer may be provided on a surface of the first substrate facing the second substrate.

In the above configuration, the sealing portion may be made of solder.

In the above configuration, the first substrate may be an LTCC (Low Temperature Co-fired Ceramics) substrate, and the first metal layer and the second metal layer may have copper as a main component.

The present invention includes a first substrate, a second substrate disposed on the first substrate so as to face each other with a gap therebetween, and a first substrate surrounding the second substrate when the first substrate is viewed from above. a first metal layer provided on a substrate; a second metal layer provided on the first substrate surrounding the second substrate and the first metal layer and spaced from the first metal layer; An element provided on a surface of the second substrate on the first substrate side and surrounding the second substrate to seal the element and cover between the first metal layer and the second metal layer. a sealing portion provided on the first metal layer and the second metal layer, the first substrate including a support substrate and a piezoelectric substrate provided on a surface of the support substrate on the second substrate side. and the piezoelectric substrate has two openings surrounding the second substrate when the piezoelectric substrate is viewed from above, and the first metal layer and the second metal layer are arranged in the two openings, respectively. It is an electronic component provided.

In the above configuration, the element may be an acoustic wave element.

The present invention is a filter including the electronic component described above.

The present invention is a multiplexer including the above filter.

According to the present invention, deterioration of airtightness can be suppressed.

FIG. 1(a) is a cross-sectional view of the electronic component according to Example 1, FIG. 1(b) is an enlarged view of the vicinity of the metal layer, and FIG. 1(c) is a plan view. 2(a) and 2(b) are a plan view and a cross-sectional view showing an example of the acoustic wave element 22 in Example 1. FIG. FIGS. 3(a) to 3(c) are cross-sectional views (part 1) showing the method for manufacturing the electronic component according to the first embodiment. FIGS. 4(a) and 4(b) are cross-sectional views (part 2) showing the method for manufacturing the electronic component according to the first embodiment. FIGS. 5(a) to 5(c) are cross-sectional views of electronic components in the simulation. FIGS. 6(a) and 6(b) are a plan view and a cross-sectional view showing the structure used in the simulation. FIGS. 7(a) to 7(c) are diagrams showing distortions with respect to position Y in simulation. FIG. 8 is a cross-sectional view of an electronic component according to Modification 1 of Example 1. FIG. 9 is a sectional view of an electronic component according to a second modification of the first embodiment. 10(a) and 10(b) are cross-sectional views of electronic components according to modified examples 3 and 4 of Example 1, respectively, and FIG. 10(c) is a plan view. FIG. 11A is a circuit diagram of a filter according to a second embodiment, and FIG. 11B is a circuit diagram of a duplexer according to a first modification of the second embodiment.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a cross-sectional view of the electronic component according to Example 1, FIG. 1(b) is an enlarged view of the vicinity of the metal layer, and FIG. 1(c) is a plan view. FIG. 1(c) illustrates the substrate 10 and metal layers 32a and 32b.

As shown in FIGS. 1(a) to 1(c), insulating layers 10a and 10b are provided. The insulating layers 10a and 10b are, for example, ceramic layers such as LTCC (Low Temperature Co-fired Ceramics) or HTCC (High Temperature Co-fired Ceramics), or resin layers such as glass epoxy resin. A terminal 18 is provided on the lower surface of the insulating layer 10a. A metal layer 12a is provided between insulating layers 10a and 10b. Metal layers 12b, 32a and 32b are embedded in the upper surface of insulating layer 10b. The upper surface of substrate 10 and the upper surfaces of metal layers 12b, 32a and 32b are substantially flat. Via interconnections 16a and 16b are provided that penetrate through insulating layers 10a and 10b. The metal layers 12a, 12b, 32a, 32b, the via wiring 16a, 16b, and the terminal 18 are, for example, metal layers such as a copper layer, an aluminum layer, or a gold layer.

Metal layers 32a and 32b are provided at the periphery of substrate 10. The metal layer 32a is provided so as to surround the substrate 20, and the metal layer 32b is provided so as to surround the metal layer 32a. A region 31 (a gap between the metal layers 32a and 32b) in which no metal layer is embedded is provided between the metal layers 32a and 32b. When the substrate 10 is an LTCC substrate, the metal layers 32a and 32b are, for example, a copper layer containing copper as a main component or a silver layer containing silver as a main component. When the substrate 10 is an HTCC substrate, the metal layers 32a and 32b are, for example, tungsten layers containing tungsten as a main component.

Metal layers 34a and 34b are provided on metal layers 32a and 32b, respectively. When the metal layers 32a and 32b are copper layers and the sealing part 30 is a solder layer, the metal layers 34a and 34b are, for example, a nickel layer 33a and a gold layer 33b from the metal layers 32a and 32b side. The nickel layer 33a is a barrier layer that suppresses mutual diffusion between the sealing part 30 and the metal layers 32a and 32b. The gold layer 33b is a layer that has good wettability with the sealing part 30, and joins the sealing part 30 to the metal layers 34a and 34b. The gold layer 33b forms an alloy layer with the sealing portion 30. When the metal layers 32a and 32b have good wettability with the sealing part 30, the metal layers 34a and 34b may not be provided.

A substrate 20 is mounted on the substrate 10. An acoustic wave element 22 and wiring 24 are provided on the lower surface of the substrate 20. The wiring 24 is, for example, a metal layer such as a copper layer, an aluminum layer, or a gold layer. The board 20 is flip-chip mounted (face-down mounted) on the board 10 via bumps 28. Bump 28 is bonded to metal layer 12b and wiring 24. Bumps 28 are, for example, gold bumps, solder bumps, or copper bumps.

A sealing section 30 is provided on the substrate 10 so as to surround the substrate 20. The sealing portion 30 is, for example, a solder or resin layer containing tin. The sealing portion 30 is bonded to the upper surfaces of the metal layers 34a and 34b, and is not bonded to the substrate 10 in the region 31. A gap 31a is formed between the substrate 10 and the sealing part 30 in the region 31. In the region 31, the lower surface of the sealing part 30 has a recess 30a.

A flat lid 36 is provided on the upper surface of the substrate 20 and the upper surface of the sealing section 30. The lid 36 is, for example, a metal plate such as a Kovar plate or an insulating plate. A protective film 38 is provided to cover the lid 36 and the sealing part 30. The protective film 38 is a metal film such as a nickel film or an insulating film.

The acoustic wave element 22 faces the substrate 10 with a gap 26 in between. The acoustic wave element 22 is sealed by the sealing part 30, the substrate 10, the substrate 20, and the lid 36. Bump 28 is surrounded by void 26. The terminal 18 is electrically connected to the acoustic wave element 22 via the via wiring 16a, the metal layer 12a, the via wiring 16b, the metal layer 12b, the bump 28, and the wiring 24.

2(a) and 2(b) are a plan view and a cross-sectional view showing an example of the acoustic wave element 22 in Example 1. FIG. As shown in FIG. 2(a), the acoustic wave element 22 is a surface acoustic wave resonator. The substrate 20 is a piezoelectric substrate, and an IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 20. The IDT 40 has a pair of comb-shaped electrodes 40a facing each other. The comb-shaped electrode 40a has a plurality of electrode fingers 40b and a bus bar 40c connecting the plurality of electrode fingers 40b. Reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites surface acoustic waves in the substrate 20, which is a piezoelectric substrate. The wavelength of the elastic wave is approximately equal to the pitch of the electrode fingers 40b of one of the pair of comb-shaped electrodes 40a. That is, the wavelength of the elastic wave is approximately equal to twice the pitch of the electrode fingers 40b of the pair of comb-shaped electrodes 40a. The IDT 40 and the reflector 42 are formed of, for example, an aluminum film or a copper film. A protective film or a temperature compensation film may be provided on the substrate 20 so as to cover the IDT 40 and the reflector 42. The substrate 20 may be bonded directly or indirectly onto a supporting substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, a quartz substrate, or a silicon substrate.

As shown in FIG. 2(b), the acoustic wave element 22 is a piezoelectric thin film resonator. A piezoelectric film 46 is provided on the substrate 20. A lower electrode 44 and an upper electrode 48 are provided so as to sandwich the piezoelectric film 46 therebetween. A gap 45 is formed between the lower electrode 44 and the substrate 20. A region where the lower electrode 44 and the upper electrode 48 face each other with at least a portion of the piezoelectric film 46 in between is a resonance region 47 . In the resonance region 47, the lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode within the piezoelectric film 46. The substrate 20 is, for example, a sapphire substrate, a spinel substrate, an alumina substrate, a glass substrate, a crystal substrate, or a silicon substrate. The lower electrode 44 and the upper electrode 48 are, for example, metal films such as ruthenium films. The piezoelectric film 46 is, for example, an aluminum nitride film. Instead of the void 45, an acoustic reflection film that reflects elastic waves may be provided.

The elastic wave element 22 includes an electrode that excites elastic waves. Therefore, the elastic wave element 22 is covered with a void 26 so as not to limit the elastic waves.

[Production method of Example 1]
FIGS. 3A to 4B are cross-sectional views showing a method for manufacturing an electronic component according to the first embodiment. As shown in FIG. 3(a), the substrate 10 has a plurality of stacked insulating layers 10a to 10c. Metal layers 12b, 32a and 32b are provided between the uppermost insulating layers 10c and 10b.

As shown in FIG. 3(b), the upper surface of the insulating layer 10c is polished. As a result, the upper surfaces of metal layers 12b, 32a, and 32b are exposed from insulating layer 10c. Hereinafter, the insulating layer 10c will be explained as part of the insulating layer 10b. As shown in FIG. 3(c), metal layers 34a and 34b are formed on metal layers 32a and 32b, respectively.

As shown in FIG. 4A, the substrate 20 is flip-chip mounted onto the substrate 10 via bumps 28. Thereby, the substrate 10 and the acoustic wave element 22 face each other with the gap 26 in between. As shown in FIG. 4(b), a lid 36 having a solder plate made of, for example, tin and silver formed on its lower surface is placed on the substrate 20. The solder is heated and melted, and the lid 36 is pressed toward the substrate 20. As a result, since the upper surfaces of the metal layers 34a and 34b have good wettability with the solder, the molten solder is bonded to the upper surfaces of the metal layers 34a and 34b. Since the solder has poor wettability with the substrate 10, the solder does not bond to the substrate 10. Thereby, a sealing portion 30 is formed that surrounds the substrate 20 and is bonded to the metal layers 34a and 34b. The lid 36, sealing part 30, and substrate 10 are cut. Thereby, the electronic component is separated into individual pieces. A protective film 38 surrounding the sealing part 30 and the lid 36 is formed. As a result, the electronic components shown in FIGS. 1(a) to 1(c) are manufactured.

[simulation]
The strain applied to the metal layer 32 was simulated. FIGS. 5(a) to 5(c) are cross-sectional views of electronic components in the simulation. 5(a) corresponds to Comparative Example 1, FIG. 5(b) corresponds to Comparative Example 2, and FIG. 5(c) corresponds to Example 1. As shown in FIG. 5A, in Comparative Example 1, there is only one metal layer 32, which is not embedded in the substrate 10. A point on the lower surface of the metal layer 32 on the substrate 20 side (the right side in FIG. 5(a)) is designated as A1.

As shown in FIG. 5B, in Comparative Example 2, there is only one metal layer 32, which is embedded in the substrate 10. The upper surface of substrate 10 and the upper surface of metal layer 32 are substantially flat. Points on the upper and lower surfaces of the metal layer 32 on the substrate 20 side are designated A2 and A3, respectively.

As shown in FIG. 5C, in Example 1, two metal layers 32a and 32b are provided and embedded in the substrate 10. The upper surface of substrate 10 and the upper surfaces of metal layers 32a and 32b are substantially flat. Points on the upper and lower surfaces of the metal layer 32a on the substrate 20 side are designated A4 and A5, respectively. Points on the upper and lower surfaces of the metal layer 32b on the substrate 20 side are designated A6 and A7, respectively.

FIGS. 6(a) and 6(b) are a plan view and a cross-sectional view showing the structure used in the simulation. In FIGS. 6A and 6B, Comparative Example 1 will be described as an example, but Comparative Example 2 is the same except that the metal layers 32 and 12b are embedded in the substrate 10. Example 1 is similar except that metal layers 32a and 32b are provided and embedded in the substrate. The normal direction of the substrate 10 is the Z direction, and the side directions of the substrate 10 are the X direction and the Y direction.

As shown in FIGS. 6(a) and 6(b), the simulation was performed using a 1/4 symmetrical model of the substrate 10. That is, the metal layer 32 and the protective film 38 were not provided on the +X side surface and the −Y side surface of the substrate 10, and the boundary condition of these surfaces was set as a mirror surface condition. Let the lengths of the substrate 10 in the Y direction and the X direction be D1 and D2. Let the lengths of the substrate 20 in the X direction and the Y direction be D4 and D5. The width of the metal layer 32 is assumed to be D3. The diameter of the bump 28 is assumed to be D6. Let the thickness of the substrate 10 be T1. Let the thickness of the metal layer 32 and the bump 28 be T2. The thickness of the substrate 20 and the sealing part 30 is assumed to be T3. Let the thickness of the lid 36 be T4. The thickness of the protective film 38 is assumed to be T5.

The simulation conditions are as follows.
Substrate 10: LTCC substrate Metal layers 12a, 32, 32a and 32b: Copper (Cu)
Bump 28: Gold (Au)
Substrate 20: Sapphire Sealing portion 30: Tin silver (SnAg)
Lid 36: Kovar Protective film 38: Nickel (Ni)

D1=1.26mm, D2=1.1mm, D3=0.1mm, D4=0.8mm, D5=1.05mm, D6=75μm
T1=330μm, T2=15μm, T3=350μm, T4=25μm, T5=10μm
Width of metal layers 32a and 32b in Example 1: 0.04 mm
Width of region 31: 20 μm

Table 1 is a table showing the Young's modulus, linear expansion coefficient, and Poisson's ratio of each material used in the simulation.

5(a) to 5(a) to 5(a) when the sealing part 30 is assembled at 221° C. and then heated to 25° C., −40° C. and 125° C., with the −Y end in FIG. The distortion from positions A1 to A7 in (c) was simulated.

FIGS. 7(a) to 7(c) are diagrams showing distortions with respect to position Y in simulation. Figures 7(a) to 7(c) show the strains at 25°C, -40°C, and 120°C, respectively. For the position Y, the −Y end in FIG. 6(a) is set as 0, and the +Y direction is set as positive.

As shown in FIGS. 7(a) to 7(c), as the position Y increases, the distortion decreases. Among the same positions, the distortion at position A1 is the largest. The distortions at positions A2 and A4 are of the same degree and the next largest. The distortions at positions A3 and A5 are of the same degree and the next largest. The distortion at position A6 is the next largest, and the distortion at position A7 is the smallest.

In Comparative Example 1, the distortion at position A1 is large. As a result, if the adhesion between the metal layer 32 and the substrate 10 is poor, the metal layer 32 may be peeled off from the substrate 10. Further, if the adhesion between the sealing part 30 and the metal layer 32 is poor, the sealing part 30 may be peeled off from the metal layer 32.

The distortions at position A2 in Comparative Example 2 and at position A4 in Example 1 are comparable. As a result, in both Comparative Example 2 and Example 1, the metal layers 32 and 32a may be peeled off from the substrate 10. Furthermore, there is a possibility that the sealing part 30 will peel off from the metal layers 32 and 32a. In Comparative Example 2, when the metal layer 32 starts to peel off from the substrate 10 (or the sealing part 30 from the metal layer 32), the metal layer 32 easily peels off from the substrate 10 (or the sealing part 30 from the metal layer 32). Therefore, a gap is formed between the metal layer 32 and the substrate 10 (or between the sealing part 30 and the metal layer 32). As a result, airtightness deteriorates, such as moisture entering the void 26.

In Example 1, the metal layer 32a starts to peel off from the substrate 10 (or the sealing part 30 from the metal layer 32a), and the gap between the metal layer 32a and the substrate 10 (or between the sealing part 30 and the metal layer 32a) Even if a gap is formed, the metal layer 32b is in close contact with the substrate 10 (or the metal layer 32b of the sealing part 30). It is thought that when the metal layer 32a (or the sealing part 30) is peeled off, the strain at positions A6 and A7 of the metal layer 32b will be comparable to the strain at positions A4 and A5 before the metal layer 32a (or the sealing part 30) is peeled off. It will be done. However, it takes time for the metal layer 32b to peel off from the substrate 10 (or for the sealing part 30 to peel off from the metal layer 32b). If the metal layer 32b does not peel off from the substrate 10 (or the sealing part 30 from the metal layer 32b), the airtightness of the gap 26 is ensured by the metal layer 32b. Therefore, in Example 1, peeling of the metal layer 32b (or sealing portion 30) can be suppressed compared to Comparative Example 2, and the airtightness of the gap 26 can be further ensured.

[Modification 1 of Example 1]
FIG. 8 is a cross-sectional view of an electronic component according to Modification 1 of Example 1. As shown in FIG. 8, metal layers 12b, 32a and 32b are not embedded in substrate 10, but are provided on the flat top surface of substrate 10. In the first modification of the first embodiment, unlike the first embodiment, the metal layers 32a and 32b do not need to be buried in the substrate 10, so that the manufacturing process is easier than in the first embodiment. Furthermore, even if the metal layer 32a is peeled off from the substrate 10, it takes time for the metal layer 32b to peel off. Therefore, compared to Comparative Example 1, deterioration of airtightness can be suppressed. The other configurations are the same as those in Example 1, and their explanation will be omitted.

[Modification 2 of Example 1]
FIG. 9 is a sectional view of an electronic component according to a second modification of the first embodiment. As shown in FIG. 9, the substrate 10 includes a support substrate 11a and a piezoelectric substrate 11b. The support substrate 11a is, for example, a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate. The piezoelectric substrate 11b is, for example, a lithium tantalate substrate or a lithium niobate substrate. The piezoelectric substrate 11b is bonded to the upper surface of the support substrate 11a. The linear expansion coefficient of the support substrate 11a is smaller than that of the piezoelectric substrate 11b. An insulating layer such as silicon oxide or aluminum nitride may be provided between the piezoelectric substrate 11b and the support substrate 11a. In this way, the piezoelectric substrate 11b is directly or indirectly bonded onto the support substrate 11a.

An acoustic wave element 12 and wiring 14 are provided on the upper surface of the substrate 10. The acoustic wave element 12 is a surface acoustic wave resonator shown in FIG. 2(a). Piezoelectric substrate 11b is removed and metal layers 12b, 32a and 32b are provided on support substrate 11a. A via wiring 16 is provided that penetrates the support substrate 11a. The via wiring 16 electrically connects the terminal 18 and the wiring 14. The other configurations are the same as those in Example 1, and their explanation will be omitted. As in the second modification of the first embodiment, the substrate 10 may include a support substrate 11a and a piezoelectric substrate 11b, and the metal layers 32a and 32b may be embedded in the piezoelectric substrate 11b.

[Modifications 3 and 4 of Example 1]
10(a) and 10(b) are cross-sectional views of electronic components according to modified examples 3 and 4 of Example 1, respectively, and FIG. 10(c) is a plan view. FIG. 10(a) shows substrates 10 and 20, metal layers 32a and 32b, and insulating layers 35a and 35b.

As shown in FIGS. 10(a) to 10(c), in Modifications 3 and 4 of Example 1, insulating layers 35a and 35b are provided inside (substrate 20 side) above metal layers 34a and 34b. There is. The insulating layers 35a and 35b are, for example, glass, resin such as silicone resin, or ceramics such as LTCC or HTCC. The sealing portion 30 is not bonded to the insulating layers 35a and 35b. Thereby, the sealing part 30 is bonded to the outer upper surfaces of the metal layers 34a and 34b, but not to the inner upper surfaces. Therefore, the strain at the inner end portions of the metal layers 32a and 32b (positions A4 to A7 in FIG. 5(c)) is reduced. This makes it difficult for the metal layers 32a and 32b to peel off from the substrate 10. The other configurations are the same as those of the first embodiment and the first modification thereof, and a description thereof will be omitted.

According to the first embodiment and its modifications, the substrate 20 (second substrate) is placed on the substrate 10 (first substrate) so as to face each other with the gap 26 interposed therebetween. The metal layer 32a (first metal layer) is provided on the substrate 10 to surround the substrate 20 when the substrate 10 is viewed from above, and the metal layer 32b (second metal layer) is provided on the substrate 10 to surround the substrate 20 and the metal layer. It surrounds the layer 32a and is provided at a distance (region 31) from the metal layer 32a. The acoustic wave element 22 (element) is provided on the surface of the substrate 20 on the substrate 10 side. The sealing part 30 surrounds the substrate 20, seals the acoustic wave element 22, and is provided on the metal layers 32a and 32b so as to cover between the metal layers 32a and 32b. The sealing portion 30 is bonded to the metal layers 32a and 32b, but not to the region between the metal layers 32a and 32b.

As a result, even if the metal layer 32a peels off from the substrate 10 (or the sealing part 30 from the metal layer 32a), it takes time for the metal layer 32b to peel off from the substrate 10 (or the sealing part 30 from the metal layer 32b). It takes. The metal layer 32b can suppress deterioration of the airtightness of the void 26.

As in Variations 2 and 3 of Example 1, metal layers 32a and 32b are embedded in substrate 10. Thereby, the distortion of the metal layers 32a and 32b is small, and peeling of the metal layers 32a and 32b from the substrate 10 (or from the metal layers 32a and 32b of the sealing part 30) can be further suppressed.

As in Modifications 1 and 4 of Example 1, the upper surface of the substrate 10 on the substrate 20 side is a substantially flat surface, and the metal layers 32a and 32b are provided on the upper surface of the substrate 10. Thereby, metal layers 32a and 32b can be easily manufactured.

As in Modifications 3 and 4 of Example 1, insulation of a material different from that of the substrate 10 is applied from above at least one of the metal layers 32a and 32b to the surface of the substrate 10 in the region between the metal layers 32a and 32b. Layers 35a and 35b are provided. As a result, when the inner ends of the metal layers 32a and 32b and the inner ends where the sealing part 30 is joined to the metal layers 34a and 34b substantially coincide with each other, as in the first embodiment and the first modification thereof, In comparison, the strain in metal layers 32a and 32b is reduced. Therefore, peeling of the metal layers 32a and 32b from the substrate 10 can be further suppressed.

As shown in Table 1, the solder layer has a large coefficient of linear expansion. In particular, solder containing tin has a large coefficient of linear expansion. Therefore, if the sealing part 30 is made of solder, thermal stress is likely to be applied to the metal layers 32a and 32b to which the sealing part 30 is bonded. Therefore, it is preferable to provide metal layers 32a and 32b.

In Example 1 and Modifications 1, 3, and 4 thereof, when the substrate 10 is an LTCC substrate and the metal layers 32a and 32b mainly contain copper, the adhesion between the metal layers 32a and 32b and the substrate 10 is poor. . Therefore, it is preferable to provide a plurality of metal layers 32a and 32b.

According to the second modification of the first embodiment, the substrate 10 includes a support substrate 11a and a piezoelectric substrate 11b provided on the surface of the support substrate 11a on the substrate 20 side. The piezoelectric substrate 11b has two openings surrounding the substrate 20 when viewed from above. Metal layers 32a and 32b are provided in two openings, respectively. Also in such a configuration, by providing the metal layers 32a and 32b, peeling of the metal layers 32a and 32b (or the sealing portion 30) can be suppressed.

In the first embodiment and its modifications, an example of the acoustic wave element 22 (piezoelectric thin film resonator or surface acoustic wave resonator) was explained as the element (for example, functional element), but the element may be a passive element such as an inductor or a capacitor, An active element including a transistor or a MEMS (Micro Electro Mechanical Systems) element may be used.

FIG. 11(a) is a circuit diagram of a filter according to the second embodiment. As shown in FIG. 11(a), one or more series resonators S1 to S4 are connected in series between the input terminal Tin and the output terminal Tout. One or more parallel resonators P1 to P4 are connected in parallel between the input terminal Tin and the output terminal Tout. The filter of Example 2 may be formed of the elastic wave element 22. The number of series resonators and parallel resonators can be set as appropriate. Although the filter has been described using a ladder filter as an example, the filter may be a multimode filter.

FIG. 11(b) is a circuit diagram of a duplexer according to a first modification of the second embodiment. As shown in FIG. 11(b), a transmission filter 50 is connected between the common terminal Ant and the transmission terminal Tx. A reception filter 52 is connected between the common terminal Ant and the reception terminal Rx. The transmission filter 50 passes a signal in the transmission band among the high frequency signals inputted from the transmission terminal Tx to the common terminal Ant as a transmission signal, and suppresses signals of other frequencies. The reception filter 52 passes a signal in the reception band among the high-frequency signals inputted from the common terminal Ant to the reception terminal Rx as a reception signal, and suppresses signals at other frequencies. At least one of the transmission filter 50 and the reception filter 52 can be the filter of the second embodiment. Furthermore, in the second modification of the first embodiment, the transmission filter 50 may be formed of the elastic wave element 12 and the reception filter 52 may be formed of the elastic wave element 22.

Although a duplexer has been described as an example of a multiplexer, a triplexer or a quadplexer may also be used.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and variations can be made within the scope of the gist of the present invention as described in the claims. Changes are possible.

10, 20 Substrate 10a-10c Insulating layer 11a Support substrate 11b Piezoelectric substrate 12, 22 Acoustic wave element 12a, 12b, 32a, 32b, 34a, 34b Metal layer 14, 24 Wiring 16, 16a, 16b Via wiring 18 Terminal 26 Gap 28 Bump 30 Sealing portion 35a, 35b Insulating layer 36 Lid 50 Transmission filter 52 Reception filter

Claims (9)

a first substrate;
a second substrate disposed on the first substrate so as to face each other with a gap therebetween;
A first metal layer provided on the first substrate surrounding the second substrate when the first substrate is viewed from above;
a second metal layer provided on the first substrate surrounding the second substrate and the first metal layer and spaced apart from the first metal layer;
an element provided on a surface of the second substrate on the first substrate side;
a sealing part that surrounds the second substrate, seals the element, covers between the first metal layer and the second metal layer, and is provided on the first metal layer and the second metal layer; and,
Provided from above at least one of the first metal layer and the second metal layer to the surface of the first substrate in a region between the first metal layer and the second metal layer, is an insulating layer of different materials,
Electronic components with. The electronic component according to claim 1, wherein the first metal layer and the second metal layer are embedded in the first substrate. The electronic component according to claim 1, wherein the first metal layer and the second metal layer are provided on a surface of the first substrate that faces the second substrate. The electronic component according to any one of claims 1 to 3 , wherein the sealing portion is solder. 5. The electronic device according to claim 1, wherein the first substrate is an LTCC (Low Temperature Co-fired Ceramics) substrate, and the first metal layer and the second metal layer contain copper as a main component. parts. a first substrate;
a second substrate disposed on the first substrate so as to face each other with a gap therebetween;
A first metal layer provided on the first substrate surrounding the second substrate when the first substrate is viewed from above;
a second metal layer provided on the first substrate surrounding the second substrate and the first metal layer and spaced apart from the first metal layer;
an element provided on a surface of the second substrate on the first substrate side;
a sealing part that surrounds the second substrate, seals the element, covers between the first metal layer and the second metal layer, and is provided on the first metal layer and the second metal layer; and,
The first substrate includes a support substrate and a piezoelectric substrate provided on a surface of the support substrate on the second substrate side,
The piezoelectric substrate has two openings surrounding the second substrate when the piezoelectric substrate is viewed from above,
The first metal layer and the second metal layer are provided in the two openings, respectively. The electronic component according to any one of claims 1 to 6 , wherein the element is an acoustic wave element. A filter comprising the electronic component according to any one of claims 1 to 7 . A multiplexer comprising a filter according to claim 8 .

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