JP2021068975A - Electronic component, filter, and multiplexer - Google Patents

Abstract

To suppress degradation in airtightness.SOLUTION: An electronic component comprises: a first substrate 10; a second substrate 20 which is disposed above the first substrate in a manner facing the first substrate across a gap 26; a first metal layer 32a which is provided on the first substrate in a manner surrounding the second substrate in plan view of the first substrate; a second metal layer 32b which is provided on the first substrate in a manner surrounding the second substrate and the first metal layer, while being spaced apart from the first metal layer; an element provided on a surface on the first substrate side of the second substrate; and a sealing part 30 which surrounds the second substrate and seals the element, and which is provided above the first metal layer and the second metal layer while covering a portion between the first metal layer and the second metal layer.SELECTED DRAWING: Figure 1

Description

The present invention relates to electronic components, filters and multiplexers, for example, electronic components, filters and multiplexers having a sealing portion.

A second substrate having a functional element such as an elastic wave element provided on the lower surface of the first substrate such as a ceramic substrate is mounted, and the second substrate is surrounded and sealed with a metal layer provided on the first substrate. A structure is known in which a functional element is sealed by a portion (for example, Patent Documents 1 and 2).

JP-A-2017-204544 Japanese Unexamined Patent Publication No. 2019-036784

When a stress such as thermal stress is applied between the metal layer surrounding the second substrate and the first substrate, the metal layer may be peeled off from the first substrate. For example, the adhesion between the LTCC (Low Temperature Co-fired Ceramics) substrate and the copper layer is poor, and the copper layer may peel off from the LTCC substrate. Further, if the adhesion between the sealing portion and the metal layer is poor, the sealing portion may be peeled off from the metal layer. When the sealing portion and / or the metal layer is peeled off, the airtightness of the void sealed by the sealing portion deteriorates.

The present invention has been made in view of the above problems, and an object of the present invention is to suppress deterioration of airtightness.

In the present invention, the first substrate, the second substrate arranged on the first substrate so as to face each other through a gap, and the first substrate are viewed in a plan view, and the first substrate is surrounded by the first substrate. A first metal layer provided on the substrate, and a second metal layer provided on the first substrate so as to surround the second substrate and the first metal layer at intervals from the first metal layer. The element provided on the surface of the second substrate on the first substrate side and the second substrate are surrounded, the element is sealed, and the space between the first metal layer and the second metal layer is covered. It is an electronic component including the first metal layer and a sealing portion provided on the second metal layer.

In the above configuration, the first metal layer and the second metal layer may be embedded in the first substrate.

In the above configuration, the first metal layer and the second metal layer may be provided on the surface of the first substrate facing the second substrate.

In the above configuration, it is provided from above at least one metal layer of the first metal layer and the second metal layer to the surface of the first substrate in the region between the first metal layer and the second metal layer. It can be configured to include an insulating layer made of a material different from that of the first substrate.

In the above configuration, the sealing portion may be made of solder.

In the above configuration, the first substrate is an LTCC (Low Temperature Co-fired Ceramics) substrate, and the first metal layer and the second metal layer can be configured to contain copper as a main component.

In the above configuration, the first substrate includes a support substrate and a piezoelectric substrate provided on the surface of the support substrate on the second substrate side, and the piezoelectric substrate has the second piezoelectric substrate in a plan view. It has two openings surrounding the substrate, and the first metal layer and the second metal layer may be provided in the two openings, respectively.

In the above configuration, the element may be an elastic wave element.

The present invention is a filter including the above electronic components.

The present invention is a multiplexer including the above filter.

According to the present invention, deterioration of airtightness can be suppressed.

1 (a) is a cross-sectional view of an electronic component according to the first embodiment, FIG. 1 (b) is an enlarged view of the vicinity of a metal layer, and FIG. 1 (c) is a plan view. 2 (a) and 2 (b) are a plan view and a cross-sectional view showing an example of the elastic wave element 22 in the first embodiment. 3 (a) to 3 (c) are cross-sectional views (No. 1) showing a method of manufacturing an electronic component according to the first embodiment. 4 (a) and 4 (b) are cross-sectional views (No. 2) showing a method of manufacturing an electronic component according to the first embodiment. 5 (a) to 5 (c) are cross-sectional views of electronic components in the simulation. 6 (a) and 6 (b) are a plan view and a cross-sectional view showing the structure used in the simulation. 7 (a) to 7 (c) are diagrams showing the distortion with respect to the position Y in the simulation. FIG. 8 is a cross-sectional view of the electronic component according to the first modification of the first embodiment. FIG. 9 is a cross-sectional view of the electronic component according to the second modification of the first embodiment. 10 (a) and 10 (b) are cross-sectional views of electronic components according to modifications 3 and 4, respectively, and FIG. 10 (c) is a plan view. FIG. 11A is a circuit diagram of the filter according to the second embodiment, and FIG. 11B is a circuit diagram of the duplexer according to the first modification of the second embodiment.

Hereinafter, examples of the present invention will be described with reference to the drawings.

1 (a) is a cross-sectional view of an electronic component according to the first embodiment, FIG. 1 (b) is an enlarged view of the vicinity of a metal layer, and FIG. 1 (c) is a plan view. FIG. 1 (c) illustrates the substrate 10, the metal layers 32a and 32b.

As shown in FIGS. 1 (a) to 1 (c), the insulating layers 10a and 10b are provided. The insulating layers 10a and 10b are, for example, a ceramic layer such as LTCC (Low Temperature Co-fired Ceramics) or HTCC (High Temperature Co-fired Ceramics) or a resin layer such as a glass epoxy resin. A terminal 18 is provided on the lower surface of the insulating layer 10a. A metal layer 12a is provided between the insulating layers 10a and 10b. Metal layers 12b, 32a and 32b are embedded in the upper surface of the insulating layer 10b. The upper surface of the substrate 10 and the upper surfaces of the metal layers 12b, 32a and 32b are substantially flat. Via wirings 16a and 16b that penetrate the insulating layers 10a and 10b are provided. The metal layers 12a, 12b, 32a, 32b, via wirings 16a, 16b and terminals 18 are metal layers such as, for example, a copper layer, an aluminum layer or a gold layer.

The metal layers 32a and 32b are provided on the peripheral edge of the substrate 10. The metal layer 32a is provided so as to surround the substrate 20, and the metal layer 32b is provided so as to surround the metal layer 32a. A region 31 (distance between the metal layers 32a and 32b) in which the metal layer is not embedded is provided between the metal layers 32a and 32b. When the substrate 10 is an LTCC substrate, the metal layers 32a and 32b are, for example, a copper layer containing copper as a main component or a silver layer containing silver as a main component. When the substrate 10 is an HTCC substrate, the metal layers 32a and 32b are, for example, tungsten layers containing tungsten as a main component.

Metal layers 34a and 34b are provided on the metal layers 32a and 32b, respectively. When the metal layers 32a and 32b are copper layers and the sealing portion 30 is a solder layer, the metal layers 34a and 34b are, for example, nickel layers 33a and gold layers 33b from the metal layers 32a and 32b side. The nickel layer 33a is a barrier layer that suppresses mutual diffusion between the sealing portion 30 and the metal layers 32a and 32b. The gold layer 33b is a layer having good wettability with the sealing portion 30, and the sealing portion 30 is joined to the metal layers 34a and 34b. The gold layer 33b forms an alloy layer with the sealing portion 30. If the metal layers 32a and 32b have good wettability with the sealing portion 30, the metal layers 34a and 34b may not be provided.

The substrate 20 is mounted on the substrate 10. An elastic wave element 22 and a wiring 24 are provided on the lower surface of the substrate 20. The wiring 24 is, for example, a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 20 is flip-chip mounted (face-down mounted) on the substrate 10 via bumps 28. The bump 28 is joined to the metal layer 12b and the wiring 24. The bump 28 is, for example, a gold bump, a solder bump or a copper bump.

A sealing portion 30 is provided on the substrate 10 so as to surround the substrate 20. The sealing portion 30 is, for example, a solder or resin layer containing tin. The sealing portion 30 is bonded to the upper surfaces of the metal layers 34a and 34b, and is not bonded to the substrate 10 of the region 31. There is a gap 31a between the substrate 10 and the sealing portion 30 in the region 31. In the region 31, the lower surface of the sealing portion 30 has a recess 30a.

A flat lid 36 is provided on the upper surface of the substrate 20 and the upper surface of the sealing portion 30. The lid 36 is a metal plate such as a Kovar plate or an insulating plate. A protective film 38 is provided so as to cover the lid 36 and the sealing portion 30. The protective film 38 is a metal film such as a nickel film or an insulating film.

The elastic wave element 22 faces the substrate 10 through the gap 26. The elastic wave element 22 is sealed by the sealing portion 30, the substrate 10, the substrate 20, and the lid 36. The bump 28 is surrounded by the void 26. The terminal 18 is electrically connected to the elastic wave element 22 via the via wiring 16a, the metal layer 12a, the via wiring 16b, the metal layer 12b, the bump 28, and the wiring 24.

2 (a) and 2 (b) are a plan view and a cross-sectional view showing an example of the elastic wave element 22 in the first embodiment. As shown in FIG. 2A, the surface acoustic wave element 22 is a surface acoustic wave resonator. The substrate 20 is a piezoelectric substrate, and an IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 20. The IDT 40 has a pair of comb-shaped electrodes 40a facing each other. The comb-shaped electrode 40a has a plurality of electrode fingers 40b and a bus bar 40c for connecting the plurality of electrode fingers 40b. Reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites a surface acoustic wave on the substrate 20 which is a piezoelectric substrate. The wavelength of the elastic wave is substantially equal to the pitch of the electrode fingers 40b of one comb-shaped electrode 40a of the pair of comb-shaped electrodes 40a. That is, the wavelength of the elastic wave is substantially equal to twice the pitch of the electrode fingers 40b of the pair of comb-shaped electrodes 40a. The IDT 40 and the reflector 42 are formed of, for example, an aluminum film or a copper film. A protective film or a temperature compensation film may be provided on the substrate 20 so as to cover the IDT 40 and the reflector 42. The substrate 20 may be directly or indirectly bonded to a support substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate.

As shown in FIG. 2B, the elastic wave element 22 is a piezoelectric thin film resonator. A piezoelectric film 46 is provided on the substrate 20. The lower electrode 44 and the upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 20. The region where the lower electrode 44 and the upper electrode 48 face each other with at least a part of the piezoelectric film 46 sandwiched is the resonance region 47. In the resonance region 47, the lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. The substrate 20 is, for example, a sapphire substrate, a spinel substrate, an alumina substrate, a glass substrate, a crystal substrate, or a silicon substrate. The lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film. The piezoelectric film 46 is, for example, an aluminum nitride film. An acoustic reflection film that reflects elastic waves may be provided instead of the gap 45.

The elastic wave element 22 includes an electrode that excites an elastic wave. Therefore, the elastic wave element 22 is covered with a gap 26 so as not to limit the elastic wave.

[Manufacturing method of Example 1]
3 (a) to 4 (b) are cross-sectional views showing a method of manufacturing an electronic component according to the first embodiment. As shown in FIG. 3A, the substrate 10 has a plurality of laminated insulating layers 10a to 10c. Metal layers 12b, 32a and 32b are provided between the topmost insulating layers 10c and 10b.

As shown in FIG. 3B, the upper surface of the insulating layer 10c is polished. As a result, the upper surfaces of the metal layers 12b, 32a and 32b are exposed from the insulating layer 10c. Hereinafter, the insulating layer 10c will be described as a part of the insulating layer 10b. As shown in FIG. 3C, the metal layers 34a and 34b are formed on the metal layers 32a and 32b, respectively.

As shown in FIG. 4A, the substrate 20 is flip-chip mounted on the substrate 10 via bumps 28. As a result, the substrate 10 and the elastic wave element 22 face each other with the gap 26 interposed therebetween. As shown in FIG. 4B, a lid 36 having a solder plate made of, for example, tin and silver formed on the lower surface thereof is arranged on the substrate 20. The solder is heated and melted, and the lid 36 is pressed in the direction of the substrate 20. As a result, the upper surfaces of the metal layers 34a and 34b have good wettability with respect to the solder, so that the molten solder is joined to the upper surfaces of the metal layers 34a and 34b. Since the solder has poor wettability with the substrate 10, the solder does not join with the substrate 10. As a result, a sealing portion 30 that surrounds the substrate 20 and joins the metal layers 34a and 34b is formed. The lid 36, the sealing portion 30, and the substrate 10 are cut. As a result, the electronic components are separated into individual pieces. A protective film 38 surrounding the sealing portion 30 and the lid 36 is formed. As a result, the electronic components shown in FIGS. 1 (a) to 1 (c) are manufactured.

[simulation]
The strain applied to the metal layer 32 was simulated. 5 (a) to 5 (c) are cross-sectional views of electronic components in the simulation. FIG. 5A corresponds to Comparative Example 1, FIG. 5B corresponds to Comparative Example 2, and FIG. 5C corresponds to Example 1. As shown in FIG. 5A, in Comparative Example 1, there is only one metal layer 32, and it is not embedded in the substrate 10. The point on the substrate 20 side (right side in FIG. 5A) of the lower surface of the metal layer 32 is designated as A1.

As shown in FIG. 5B, in Comparative Example 2, there is only one metal layer 32, which is embedded in the substrate 10. The upper surface of the substrate 10 and the upper surface of the metal layer 32 are substantially flat. The points on the substrate 20 side of the upper surface and the lower surface of the metal layer 32 are designated as A2 and A3, respectively.

As shown in FIG. 5 (c), in the first embodiment, two metal layers 32a and 32b are provided and embedded in the substrate 10. The upper surface of the substrate 10 and the upper surfaces of the metal layers 32a and 32b are substantially flat. The points on the upper surface and the lower surface of the metal layer 32a on the substrate 20 side are designated as A4 and A5, respectively. The points on the substrate 20 side of the upper surface and the lower surface of the metal layer 32b are designated as A6 and A7, respectively.

6 (a) and 6 (b) are a plan view and a cross-sectional view showing the structure used in the simulation. Although Comparative Example 1 is described as an example in FIGS. 6A and 6B, Comparative Example 2 is the same except that the metal layers 32 and 12b are embedded in the substrate 10. The first embodiment is the same except that the metal layers 32a and 32b are provided and embedded in the substrate. The normal direction of the substrate 10 is the Z direction, and the side directions of the substrate 10 are the X direction and the Y direction.

As shown in FIGS. 6 (a) and 6 (b), the simulation was performed using a 1/4 symmetric model of the substrate 10. That is, the metal layer 32 and the protective film 38 are not provided on the + X side surface and the −Y side surface of the substrate 10, and the boundary condition between these surfaces is set as the mirror surface condition. Let the lengths of the substrate 10 in the Y direction and the X direction be D1 and D2. Let the lengths of the substrate 20 in the X and Y directions be D4 and D5. Let the width of the metal layer 32 be D3. Let the diameter of the bump 28 be D6. Let T1 be the thickness of the substrate 10. Let T2 be the thickness of the metal layer 32 and the bump 28. The thickness of the substrate 20 and the sealing portion 30 is T3. Let the thickness of the lid 36 be T4. The thickness of the protective film 38 is T5.

The simulation conditions are as follows.
Substrate 10: LTCC substrate Metal layers 12a, 32, 32a and 32b: Copper (Cu)
Bump 28: Gold (Au)
Substrate 20: Sapphire sealing part 30: Tin silver (SnAg)
Lid 36: Kovar protective film 38: Nickel (Ni)

D1 = 1.26 mm, D2 = 1.1 mm, D3 = 0.1 mm, D4 = 0.8 mm, D5 = 1.05 mm, D6 = 75 μm
T1 = 330 μm, T2 = 15 μm, T3 = 350 μm, T4 = 25 μm, T5 = 10 μm
Width of metal layers 32a and 32b in Example 1: 0.04 mm
Region 31 width: 20 μm

Table 1 is a table showing Young's modulus, coefficient of linear expansion and Poisson's ratio of each material used in the simulation.

FIGS. 5 (a) to 5 (a) to FIG. 5 (a) show that the positions in the Y direction with the −Y end as 0 in FIG. The distortion of positions A1 to A7 in (c) was simulated.

7 (a) to 7 (c) are diagrams showing the distortion with respect to the position Y in the simulation. 7 (a) to 7 (c) are strains at 25 ° C., −40 ° C. and 120 ° C., respectively. For the position Y, the −Y end in FIG. 6A was set to 0, and the + Y direction was set to positive.

As shown in FIGS. 7 (a) to 7 (c), the distortion becomes smaller as the position Y becomes larger. At the same position, the distortion at position A1 is the largest. The distortions at positions A2 and A4 are about the same and the next largest. The distortions at positions A3 and A5 are about the same and the next largest. The distortion at position A6 is the next largest, and the distortion at position A7 is the smallest.

In Comparative Example 1, the distortion at the position A1 is large. As a result, if the adhesion between the metal layer 32 and the substrate 10 is poor, the metal layer 32 may be peeled off from the substrate 10. Further, if the adhesion between the sealing portion 30 and the metal layer 32 is poor, the sealing portion 30 may be peeled off from the metal layer 32.

The distortion at the position A2 of Comparative Example 2 and the position A4 of Example 1 is about the same. As a result, the metal layers 32 and 32a may be peeled off from the substrate 10 in both Comparative Example 2 and Example 1. Further, the sealing portion 30 may be peeled off from the metal layers 32 and 32a. In Comparative Example 2, when the metal layer 32 starts to peel off from the substrate 10 (or the sealing portion 30 starts to peel off from the metal layer 32), the metal layer 32 tends to peel off from the substrate 10 (or the sealing portion 30 from the metal layer 32). Therefore, a gap is formed between the metal layer 32 and the substrate 10 (or between the sealing portion 30 and the metal layer 32). As a result, the airtightness deteriorates, such as moisture entering the voids 26.

In Example 1, the metal layer 32a begins to peel off from the substrate 10 (or the sealing portion 30 from the metal layer 32a) and is between the metal layer 32a and the substrate 10 (or between the sealing portion 30 and the metal layer 32a). Even if a gap is formed in the metal layer 32b, the metal layer 32b is in close contact with the substrate 10 (or the sealing portion 30 is in close contact with the metal layer 32b). It is considered that when the metal layer 32a (or the sealing portion 30) is peeled off, the strain of the positions A6 and A7 of the metal layer 32b becomes the same as the strain of the positions A4 and A5 before the metal layer 32a (or the sealing portion 30) is peeled off. Be done. However, it takes time for the metal layer 32b to peel off from the substrate 10 (or the sealing portion 30 from the metal layer 32b). If the metal layer 32b is not peeled off from the substrate 10 (or the sealing portion 30 is removed from the metal layer 32b), the metal layer 32b ensures the airtightness of the gap 26. Therefore, in Example 1, peeling of the metal layer 32b (or the sealing portion 30) can be suppressed as compared with Comparative Example 2, and the airtightness of the void 26 can be further ensured.

[Modification 1 of Example 1]
FIG. 8 is a cross-sectional view of the electronic component according to the first modification of the first embodiment. As shown in FIG. 8, the metal layers 12b, 32a and 32b are not embedded in the substrate 10 but are provided on the flat upper surface of the substrate 10. In the first modification of the first embodiment, unlike the first embodiment, the metal layers 32a and 32b do not have to be embedded in the substrate 10, so that the manufacturing process becomes easier than in the first embodiment. Further, even if the metal layer 32a is peeled off from the substrate 10, it takes time for the metal layer 32b to be peeled off. Therefore, deterioration of airtightness can be suppressed as compared with Comparative Example 1. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

[Modification 2 of Example 1]
FIG. 9 is a cross-sectional view of the electronic component according to the second modification of the first embodiment. As shown in FIG. 9, the substrate 10 has a support substrate 11a and a piezoelectric substrate 11b. The support substrate 11a is, for example, a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate. The piezoelectric substrate 11b is, for example, a lithium tantalate substrate or a lithium niobate substrate. The piezoelectric substrate 11b is joined to the upper surface of the support substrate 11a. The coefficient of linear expansion of the support substrate 11a is smaller than that of the piezoelectric substrate 11b. An insulator layer such as silicon oxide or aluminum nitride may be provided between the piezoelectric substrate 11b and the support substrate 11a. In this way, the piezoelectric substrate 11b is directly or indirectly bonded to the support substrate 11a.

An elastic wave element 12 and a wiring 14 are provided on the upper surface of the substrate 10. The surface acoustic wave element 12 is an elastic surface wave resonator shown in FIG. 2 (a). The piezoelectric substrate 11b has been removed, and metal layers 12b, 32a and 32b are provided on the support substrate 11a. A via wiring 16 that penetrates the support substrate 11a is provided. The via wiring 16 electrically connects the terminal 18 and the wiring 14. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted. As in the second modification of the first embodiment, the substrate 10 may have a support substrate 11a and a piezoelectric substrate 11b, and the metal layers 32a and 32b may be embedded in the piezoelectric substrate 11b.

[Modified Examples 3 and 4 of Example 1]
10 (a) and 10 (b) are cross-sectional views of electronic components according to modifications 3 and 4, respectively, and FIG. 10 (c) is a plan view. FIG. 10A shows the substrates 10, 20, the metal layers 32a and 32b, and the insulating layers 35a and 35b.

As shown in FIGS. 10 (a) to 10 (c), in the modified examples 3 and 4 of the first embodiment, the insulating layers 35a and 35b are provided on the inner side (the substrate 20 side) on the metal layers 34a and 34b. There is. The insulating layers 35a and 35b are resins such as glass and silicone resin, or ceramics such as LTCC or HTCC. The sealing portion 30 is not bonded to the insulating layers 35a and 35b. As a result, the sealing portion 30 is bonded to the outer upper surface of the metal layers 34a and 34b and not to the inner upper surface. Therefore, the distortion of the inner end portions (positions A4 to A7 in FIG. 5C) of the metal layers 32a and 32b is reduced. As a result, the metal layers 32a and 32b are less likely to be peeled off from the substrate 10. Other configurations are the same as those of the first embodiment and the first modification thereof, and the description thereof will be omitted.

According to the first embodiment and its modifications, the substrate 20 (second substrate) is arranged on the substrate 10 (first substrate) so as to face each other through the gap 26. The metal layer 32a (first metal layer) is provided on the substrate 10 so as to surround the substrate 20 in a plan view of the substrate 10, and the metal layer 32b (second metal layer) is provided on the substrate 10 with the substrate 20 and metal. The layer 32a is surrounded by a space (region 31) from the metal layer 32a. The elastic wave element 22 (element) is provided on the surface of the substrate 20 on the substrate 10 side. The sealing portion 30 surrounds the substrate 20 to seal the elastic wave element 22, covers between the metal layers 32a and 32b, and is provided on the metal layers 32a and 32b. The sealing portion 30 is bonded to the metal layers 32a and 32b, and is not bonded to the region between the metal layers 32a and 32b.

As a result, even if the metal layer 32a is peeled off from the substrate 10 (or the sealing portion 30 is peeled off from the metal layer 32a), it takes time for the metal layer 32b to be peeled off from the substrate 10 (or the sealing portion 30 is peeled off from the metal layer 32b). It takes. The metal layer 32b can suppress the deterioration of the airtightness of the void 26.

The metal layers 32a and 32b are embedded in the substrate 10 as in the modifications 2 and 3 of the first embodiment. As a result, the strain of the metal layers 32a and 32b is small, and the peeling of the metal layers 32a and 32b from the substrate 10 (or from the metal layers 32a and 32b of the sealing portion 30) can be further suppressed.

As in the first and fourth modifications of the first embodiment, the upper surface of the substrate 10 on the substrate 20 side is a substantially flat surface, and the metal layers 32a and 32b are provided on the upper surface of the substrate 10. Thereby, the metal layers 32a and 32b can be easily manufactured.

Insulation of a material different from the substrate 10 from above at least one of the metal layers 32a and 32b to the surface of the substrate 10 in the region between the metal layers 32a and 32b as in the modifications 3 and 4 of the first embodiment. Layers 35a and 35b are provided. As a result, as in Example 1 and its modification 1, the inner end of the metal layers 32a and 32b and the inner end of the sealing portion 30 joining the metal layers 34a and 34b substantially coincide with each other. In comparison, the strain of the metal layers 32a and 32b becomes smaller. Therefore, peeling of the metal layers 32a and 32b from the substrate 10 can be further suppressed.

As shown in Table 1, the solder layer has a large coefficient of linear expansion. In particular, solder containing tin has a large coefficient of linear expansion. Therefore, when the sealing portion 30 is soldered, thermal stress is likely to be applied to the metal layers 32a and 32b to which the sealing portion 30 is bonded. Therefore, it is preferable to provide the metal layers 32a and 32b.

In Example 1 and its modifications 1, 3 and 4, when the substrate 10 is an LTCC substrate and the metal layers 32a and 32b contain copper as a main component, the adhesion between the metal layers 32a and 32b and the substrate 10 is poor. .. Therefore, it is preferable to provide a plurality of metal layers 32a and 32b.

According to the second modification of the first embodiment, the substrate 10 includes a support substrate 11a and a piezoelectric substrate 11b provided on the surface of the support substrate 11a on the substrate 20 side. The piezoelectric substrate 11b has two openings surrounding the substrate 20 in a plan view of the piezoelectric substrate 11b. The metal layers 32a and 32b are provided in the two openings, respectively. Even in such a configuration, by providing the metal layers 32a and 32b, peeling of the metal layers 32a and 32b (or the sealing portion 30) can be suppressed.

In Example 1 and its modifications, an example of an elastic wave element 22 (piezoelectric thin film resonator or elastic surface wave resonator) was described as an element (for example, a functional element), but the element is a passive element such as an inductor or a capacitor. An active element including a transistor or a MEMS (Micro Electro Mechanical Systems) element may be used.

FIG. 11A is a circuit diagram of the filter according to the second embodiment. As shown in FIG. 11A, one or more series resonators S1 to S4 are connected in series between the input terminal Tin and the output terminal Tout. One or more parallel resonators P1 to P4 are connected in parallel between the input terminal Tin and the output terminal Tout. The filter of the second embodiment may be formed by the elastic wave element 22. The number of series resonators and parallel resonators can be set as appropriate. Although the ladder type filter has been described as an example of the filter, the filter may be a multiple mode type filter.

FIG. 11B is a circuit diagram of the duplexer according to the first modification of the second embodiment. As shown in FIG. 11B, a transmission filter 50 is connected between the common terminal Ant and the transmission terminal Tx. A reception filter 52 is connected between the common terminal Ant and the reception terminal Rx. The transmission filter 50 passes a signal in the transmission band among the high-frequency signals input from the transmission terminal Tx to the common terminal Ant as a transmission signal, and suppresses signals of other frequencies. The reception filter 52 passes a signal in the reception band among the high frequency signals input from the common terminal Ant to the reception terminal Rx as a reception signal, and suppresses signals of other frequencies. At least one of the transmission filter 50 and the reception filter 52 can be the filter of the second embodiment. Further, in the second modification of the first embodiment, the transmission filter 50 may be formed by the elastic wave element 12, and the reception filter 52 may be formed by the elastic wave element 22.

Although the duplexer has been described as an example as the multiplexer, a triplexer or a quadplexer may be used.

Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10, 20 Substrate 10a-10c Insulation layer 11a Support substrate 11b Hydraulic substrate 12, 22 Elastic wave element 12a, 12b, 32a, 32b, 34a, 34b Metal layer 14, 24 Wiring 16, 16a, 16b Via wiring 18 Terminal 26 Void 28 Bump 30 Sealing part 35a, 35b Insulation layer 36 Lid 50 Transmission filter 52 Reception filter

Claims (10)

1st board and
A second substrate arranged on the first substrate so as to face each other through a gap,
With the first substrate viewed in a plan view, a first metal layer provided on the first substrate surrounding the second substrate and
A second metal layer provided on the first substrate so as to surround the second substrate and the first metal layer at a distance from the first metal layer.
An element provided on the surface of the second substrate on the first substrate side, and
A sealing portion that surrounds the second substrate, seals the element, covers between the first metal layer and the second metal layer, and is provided on the first metal layer and the second metal layer. When,
Electronic components equipped with. The electronic component according to claim 1, wherein the first metal layer and the second metal layer are embedded in the first substrate. The electronic component according to claim 1, wherein the first metal layer and the second metal layer are provided on a surface of the first substrate facing the second substrate. It is provided from on at least one metal layer of the first metal layer and the second metal layer to the surface of the first substrate in the region between the first metal layer and the second metal layer, and is provided with the first substrate. The electronic component according to any one of claims 1 to 3, further comprising an insulating layer made of a different material. The electronic component according to any one of claims 1 to 4, wherein the sealing portion is solder. The electron according to any one of claims 1 to 5, wherein the first substrate is an LTCC (Low Temperature Co-fired Ceramics) substrate, and the first metal layer and the second metal layer contain copper as a main component. parts. The first substrate includes a support substrate and a piezoelectric substrate provided on the surface of the support substrate on the second substrate side.
The piezoelectric substrate has two openings surrounding the second substrate in a plan view of the piezoelectric substrate.
The electronic component according to any one of claims 1 to 5, wherein the first metal layer and the second metal layer are provided in the two openings, respectively. The electronic component according to any one of claims 1 to 7, wherein the element is an elastic wave element. A filter including the electronic component according to any one of claims 1 to 8. A multiplexer containing the filter according to claim 9.

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