JP2018074051A - Electronic component and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure low profile.SOLUTION: An electronic component includes a board 10, a device chip 20 where a functional part 22 is provided on the lower surface, a first metal film 26 is provided on the lateral face, the first metal film is not provided on the upper surface, and the device chip is mounted on the upper surface of the board so that the functional part and the upper surface of the board face via a cavity 38, a metal sealing part 30 composed of a brazing material surrounding the device chip, and provided to be bonded to the first metal film and the upper surface of the board thus sealing the cavity, and a second metal film 34 provided on the lateral face and the upper surface of the metal sealing part, and is not provided in at least an area of the upper surface of the device chip overlapping the functional part, in the plan view.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic component and a manufacturing method thereof, for example, an electronic component in which a device chip is sealed with a metal sealing portion and a manufacturing method thereof.

  It is known that a device chip is mounted on a substrate, a resin sealing portion is provided around the device chip in a plan view, and the device chip is sealed using the resin sealing portion (for example, Patent Documents 1 and 2). . It is known to use a metal sealing portion such as solder as the sealing portion (for example, Patent Documents 3 and 4).

JP 2001-332654 A JP 2012-186761 A Japanese Patent Laying-Open No. 2015-204531 JP 2010-74418 A

  When a functional part such as an acoustic wave element is formed on the lower surface of the device chip, the functional part is exposed in the gap. In order to suppress the deterioration of the functional part, it is important to increase the airtightness of the air gap. By using a metal sealing portion as the sealing portion and providing a lid on the device chip and the metal sealing portion, the gap can be sealed between the lid and the metal sealing portion, and airtightness can be improved. . However, when the metal sealing portion and the lid are cut, burrs are formed on the periphery of the lid. It is difficult to reduce the height of electronic components due to burrs. In addition, if a lid is provided, the electronic parts are high and it is difficult to reduce the height.

  The present invention has been made in view of the above problems, and an object thereof is to reduce the height.

  In the present invention, the functional part is provided on the lower surface, the first metal film is provided on the side surface, the first metal film is not provided on the upper surface, and the functional part and the upper surface of the substrate are spaced from each other. A device chip mounted on the upper surface of the substrate so as to face each other, and a brazing material that surrounds the device chip, is bonded to the upper surface of the first metal film and the substrate, and seals the gap And a second metal film that is provided on a side surface and an upper surface of the metal sealing portion, and is not provided in a region that overlaps the functional portion in at least a plan view of the upper surface of the device chip. This is an electronic component.

  The said structure WHEREIN: It can be set as the structure by which the lid is not provided in the upper surface of the said device chip.

  The said structure WHEREIN: It can be set as the structure which comprises the lid provided in the upper surface of the said device chip, and the upper surface of the said 2nd metal film provided in the upper surface of the said metal sealing part.

  The said structure WHEREIN: It can be set as the structure by which the space | gap is formed between the said device chip and the said lid.

  The said structure WHEREIN: It can be set as the structure which comprises the cyclic | annular metal film which is provided in the upper surface of the said board | substrate and encloses the said device chip in planar view and joins with the said metal sealing part.

  The said structure WHEREIN: The said 2nd metal film can be set as the structure which is not provided in the upper surface whole surface of the said device chip.

  In the above configuration, the functional unit may be an elastic wave element.

  The present invention provides a device chip in which a functional portion is provided on the lower surface, a first metal film is provided on the side surface, and the first metal film is not provided on the upper surface, and the functional portion and the upper surface of the substrate are interposed via a gap. Mounting on the upper surface of the substrate so as to face each other, and brazing material on the upper surface of the substrate so as to surround the device chip, to be bonded to the upper surface of the first metal film and the substrate and to seal the gap Cutting the metal sealing portion and the substrate using a dicing blade in a state where a lid is not provided on the metal sealing portion and the upper surface of the substrate. An electronic component manufacturing method including a step of singulating.

  In the above configuration, after the step of dividing into pieces, a barrel plating method is used, and is provided on a side surface and an upper surface of the metal sealing portion, and at least overlaps the functional portion in a plan view among the upper surfaces of the device chip. It can be set as the structure including the process of forming the 2nd metal film which is not provided.

  The said structure WHEREIN: After the process of forming the said metal sealing part, it can be set as the structure including the process of planarizing the upper surface of the said device chip and the said metal sealing part before the said process of separating into pieces. .

  According to the present invention, the height can be reduced.

FIG. 1A and FIG. 1B are a cross-sectional view and a plan view of an electronic component according to the first embodiment. FIG. 2A is a plan view showing an example in which the functional unit is a surface acoustic wave resonator in Example 1, and FIG. 2B is a cross-sectional view showing an example in which the functional unit is a piezoelectric thin film resonator. FIG. 3A to FIG. 3C are cross-sectional views (part 1) illustrating the method of manufacturing the electronic component according to the first embodiment. 4A to 4C are cross-sectional views (part 2) illustrating the method of manufacturing the electronic component according to the first embodiment. 5A to 5C are cross-sectional views (part 3) illustrating the method of manufacturing the electronic component according to the first embodiment. 6A to 6C are cross-sectional views (part 4) illustrating the method of manufacturing the electronic component according to the first embodiment. FIG. 7 is a cross-sectional view of an electronic component according to Comparative Example 1. FIG. 8 is a cross-sectional view of the electronic component according to the second embodiment. FIG. 9 is a cross-sectional view of the electronic component according to the third embodiment. FIG. 10 is a cross-sectional view of an electronic component according to Modification 1 of Embodiment 3. FIG. 11 is a cross-sectional view of the electronic component according to the fourth embodiment. FIG. 12 illustrates an electronic component according to Modification 1 of Embodiment 4.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A and FIG. 1B are a cross-sectional view and a plan view of an electronic component according to the first embodiment. FIG. 1B illustrates a device chip, an annular electrode, and a metal film. As shown in FIG. 1A, the electronic component 100 according to the first embodiment has a device chip 20 mounted on the upper surface of a substrate 10. The substrate 10 is an insulating substrate, for example, a ceramic substrate such as HTCC (High Temperature Co-fired Ceramic) or LTCC (Low Temperature Co-fired Ceramic) or a resin substrate. The substrate 10 has a plurality of stacked insulating layers 10a and 10b. Terminals 12a and wirings 12b are formed on the top surfaces of the insulating layers 10a and 10b, respectively. Terminals 12c are formed on the lower surface of the insulating layer 10b. Via wirings 14a and 14b penetrating the insulating layers 10a and 10b are formed. The via wiring 14a electrically connects the terminal 12a and the wiring 12b, and the via wiring 14b electrically connects the wiring 12b and the terminal 12c.

  The upper surface of the substrate 10 is flat, for example, and the terminal 12a and the annular electrode 16 are provided on the upper surface. The terminal 12a is a pad to which the bump 36 is bonded, for example. The annular electrode 16 is provided on the outer edge of the upper surface of the substrate 10 so as to surround the terminal 12a. Terminals 12 c are provided on the lower surface of the substrate 10. The terminal 12c is an external terminal for electrically connecting to the outside, and is a foot pad, for example. The terminals 12a and 12c, the wiring 12b, and the via wirings 14a and 14b are metal layers such as a tungsten layer, a copper layer, a gold layer, or an aluminum layer. The annular electrode 16 is a metal layer such as a tungsten layer, a nickel layer, or a copper layer.

  A functional unit 22 and a pad 24 are provided on the lower surface of the device chip 20. The functional unit 22 is, for example, an electrode that excites an elastic wave. The pad 24 is bonded to the bump 36. A metal film 26 is provided on the side surface of the device chip 20. The metal film 26 is not provided on the upper and lower surfaces of the device chip 20. The metal film 26 is a material having good solder wettability such as a gold film or a copper film.

  The device chip 20 is mounted on the substrate 10 via bumps 36. The functional unit 22 faces the substrate 10 with a gap 38 therebetween. Since the functional unit 22 is exposed in the gap 38, vibration of the functional unit 22 is not suppressed. The bump 36 is, for example, a copper bump, a gold bump, or a solder bump.

  A metal sealing portion 30 is provided on the upper surface of the substrate 10 so as to surround the device chip 20. The metal sealing part 30 is joined to the metal film 26 and the annular electrode 16. The metal sealing portion 30 is made of a brazing material such as SnAg solder or AuSn solder. A metal film 34 is provided on the side surface and the upper surface of the metal sealing portion 30. The metal film 34 is, for example, a nickel film, and the melting point of the metal film 34 is higher than the melting point of the metal sealing portion 30. The metal film 34 is a film that protects the metal sealing portion 30 from being deformed by reflow or the like when an electronic component is mounted on a printed circuit board or the like.

  As shown in FIG. 1B, the annular electrode 16 and the metal film 26 completely surround the device chip 20 in plan view. By this. The metal sealing portion 30 completely surrounds the device chip 20 in plan view. The device chip 20 is completely surrounded by the substrate 10, the device chip 20 and the metal sealing portion 30. Thereby, the functional part 22 is hermetically sealed.

  FIG. 2A is a plan view showing an example in which the functional unit is a surface acoustic wave resonator in Example 1, and FIG. 2B is a cross-sectional view showing an example in which the functional unit is a piezoelectric thin film resonator. As shown in FIG. 2A, an IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the piezoelectric substrate 21. The IDT 40 has a pair of comb electrodes 40a facing each other. The comb-shaped electrode 40a includes a plurality of electrode fingers 40b and a bus bar 40c that connects the plurality of electrode fingers 40b. The reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites a surface acoustic wave on the piezoelectric substrate 21. The piezoelectric substrate 21 is, for example, a lithium tantalate substrate or a lithium niobate substrate. The IDT 40 and the reflector 42 are made of, for example, an aluminum film or a copper film. The piezoelectric substrate 21 may be bonded to the lower surface of a support substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a silicon substrate. A protective film or a temperature compensation film that covers the IDT 40 and the reflector 42 may be provided. In this case, it functions as the functional unit 22 including the protective film or the temperature compensation film.

  As shown in FIG. 2B, a piezoelectric film 46 is provided on the substrate 21. A lower electrode 44 and an upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 21. The lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. As described above, the lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film, for example. The piezoelectric film 46 is, for example, an aluminum nitride film. The substrate 21 is, for example, a semiconductor substrate such as a silicon substrate or gallium arsenide, or an insulating substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a glass substrate. As shown in FIGS. 2A and 2B, the functional unit 22 includes an electrode that excites an elastic wave. For this reason, the function part 22 is covered with the space | gap 38 so that an elastic wave may not be regulated.

[Production Method of Example 1]

  FIG. 3A to FIG. 6C are cross-sectional views illustrating the method for manufacturing the electronic component according to the first embodiment. As shown in FIG. 3A, the functional unit 22 and the pad 24 are formed on the piezoelectric substrate 21. As shown in FIG. 3B, a protective film 50 is formed on the piezoelectric substrate 21 so as to cover the functional unit 22 and the pad 24. The protective film 50 is, for example, a photoresist. As shown in FIG. 3C, the groove 52 is formed so as to reach the middle of the piezoelectric substrate 21. The groove 52 is formed using a dicing blade, for example.

  As shown in FIG. 4A, the metal film 26 is formed on the upper surface of the protective film 50 and the inner surface of the groove 52. The metal film 26 is formed using, for example, a sputtering method. The metal film 26 is a laminated film in which a gold layer is provided on a titanium layer having a thickness of 0.3 μm, for example. The metal film 26 preferably contains gold in order to obtain solder wettability. As shown in FIG. 4B, the protective film 50 is peeled off. Thereby, the metal film 26 formed on the upper surface and the side surface of the protective film 50 is removed. As shown in FIG. 4C, bumps 36 are formed on the pads 24. The bump 36 is, for example, a gold stud bump. The piezoelectric substrate 21 is cut so as to overlap the groove 52. The piezoelectric substrate 21 is cut using, for example, a dicing blade. Thereby, the device chip 20 is separated into individual pieces.

  As shown in FIG. 5A, the device chip 20 singulated on the substrate 10 is flip-chip mounted by bonding the bumps 36 to the terminals 12a. In the terminal 12 a, a gap 38 is widened between the functional unit 22 of the device chip 20 and the substrate 10. The height of the gap 38 is, for example, 10 μm to 20 μm. The device chips 20 are arranged on the substrate 10 in a matrix. As shown in FIG. 5B, a plate-like member 31 is disposed on the upper surface of the device chip 20. The plate member 31 is, for example, SnAg solder.

  As shown in FIG. 5C, the plate member 31 is melted at a temperature equal to or higher than the melting point of the plate member 31. For example, the melting point of SnAg solder is about 220 ° C., and the temperature is 230 ° C. or higher. The molten solder of the plate-like member 31 is filled between the device chips 20. The filled solder reaches the side surface of the metal film 26 and the upper surface of the annular electrode 16. Since the metal film 26 and the annular electrode 16 have good solder wettability, the molten solder wets and spreads on the side surface of the metal film 26 and the upper surface of the annular electrode 16. In this state, the temperature of the substrate 10 is set to be equal to or lower than the melting point of the metal sealing portion 30. Thereby, the metal sealing part 30 is formed from the solder which the plate-shaped member 31 fuse | melted. The metal sealing part 30 is joined to the metal film 26 and the annular electrode 16. Thereby, the functional unit 22 is hermetically sealed in the gap 38 formed by the device chip 20, the substrate 10 and the metal sealing unit 30. The distance between the upper surface of the substrate 10 and the lower surface of the device chip 20 is, for example, 10 μm to 20 μm.

  As shown in FIG. 6A, the upper surfaces of the piezoelectric substrate 21 and the metal sealing portion 30 are planarized. For the planarization, for example, a polishing device 56 or the like is used. By setting the thickness of the piezoelectric substrate 21 to 100 μm or less, for example, the height of the electronic component can be reduced. Stress applied to the device chip 20 during polishing is dispersed by the metal sealing portion 30. Thereby, the crack etc. of the device chip 20 can be suppressed. For the planarization, a grinding apparatus or the like may be used.

  As shown in FIG. 6B, a protective film 62 is formed on the lower surface of the substrate 10. The protective film 62 is, for example, a photoresist. The substrate 10 is attached to the dicing tape 64 through the protective film 62. The metal sealing part 30, the substrate 10 and the protective film 62 are cut using a dicing blade 58. As a result, the electronic component 100 is separated into a plurality of pieces.

  As shown in FIG. 6C, the plurality of electronic components 100 are peeled off from the dicing tape 64, put into a barrel (not shown), and the barrel is put into the plating tank 66. The metal film 34 which is a plating film is formed using a barrel plating method. The metal film 34 is, for example, a nickel film having a thickness of 10 μm. The metal film 34 is mainly formed on the surface of a metal material. Therefore, although the metal film 34 is formed on the surface of the metal sealing portion 30, it is not formed on the upper surface of the device chip 20, the side surface of the substrate 10, and the lower surface of the protective film 62.

  After the formation of the metal film 34, the protective film 62 is peeled off. The metal film 34 is formed on the side surface and the upper surface of the metal sealing portion 30 and is not formed on the upper surface of the device chip 20. Thereby, the electronic component 100 of FIG. 1A and FIG. 1B is completed.

[Comparative Example 1]
FIG. 7 is a cross-sectional view of an electronic component according to Comparative Example 1. As shown in FIG. 7, a lid 32 is provided on the upper surfaces of the device chip 20 and the metal sealing portion 30. A metal film 34 is provided on the lid 32. A burr 33 is formed on the periphery of the lid 32. The metal film is not provided on the side surface of the device chip 20, and the side surface of the device chip 20 is not joined to the metal sealing portion 30. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  In Comparative Example 1, the device chip 20 and the metal sealing portion 30 are not joined. For this reason, the functional part 22 is hermetically sealed in the gap 38 by the device chip 20, the substrate 10, the metal sealing part 30, and the lid 32 by bonding the lid 32 and the metal sealing part 30.

  However, as shown in FIG. 6B, if the lid 32 is provided on the device chip 20 and the metal sealing portion 30 when singulated, the burr 32 is cut when the lid 32 is cut using the dicing blade 58. 33 is formed. When the burr 33 is formed, the electronic component becomes higher by the burr 33, so that it is difficult to reduce the height. If the lid 32 is provided, it is difficult to reduce the height of the lid 32 by the thickness. Further, when the lid 32 is a conductor, a stray capacitance Cf is formed between the functional unit 22 and the lid 32.

  According to Example 1, as shown in FIG. 5A, the functional unit 22 is provided on the lower surface, the metal film 26 (first metal film) is provided on the side surface, and the metal film 26 is not provided on the upper surface. The device chip 20 is mounted on the upper surface of the substrate 10 so that the functional unit 22 and the upper surface of the substrate 10 face each other with the gap 38 therebetween. As shown in FIG. 5C, a metal sealing portion 30 made of a brazing material is formed on the upper surface of the substrate 10 so as to surround the device chip 20 and to be bonded to the upper surface of the metal film 26 and the substrate 10 and seal the gap 38. Form. As shown in FIG. 6B, the lid is not provided, and the metal sealing portion 30 and the substrate 10 are cut into pieces by cutting with a dicing blade. As described above, the lid is not provided on the metal sealing portion 30 when singulated. Since the metal sealing portion 30 made of the brazing material is soft, the formation of the burr 33 is suppressed. As a result, the height of the electronic component can be reduced.

  Further, as shown in FIG. 6C, after singulation, barrel plating is used to provide the side surface and the upper surface of the metal sealing portion 30, and at least the functional portion 22 in the plan view of the upper surface of the device chip 20. A metal film 34 (second metal film) that is not provided in the overlapping region is formed. In the barrel plating method, the electronic components 100 are in contact with each other. Thereby, the burr 33 made of a soft brazing material is crushed and lowered. Therefore, it is possible to reduce the height of the electronic component.

  Further, as shown in FIG. 6A, the upper surfaces of the device chip 20 and the metal sealing portion 30 are flattened after the metal sealing portion 30 is formed and before being separated into individual pieces. Thereby, the electronic component 100 can be reduced in height.

  In the first embodiment, the lid 32 is not provided on the upper surface of the device chip 20. Thereby, it becomes possible to reduce the height. In Comparative Example 1, the lid 32 is hermetically sealed by bonding to the upper surface of the metal sealing portion 30. In the second embodiment, the metal film 26 on the side surface of the device chip 20 and the metal sealing portion 30 are joined, so that even if the lid 32 is not provided, hermetic sealing is possible. Further, since the lid 32 is not provided, the stray capacitance Cf between the functional unit 22 and the lid 32 as shown in FIG. 7 can be suppressed.

  The metal film 34 is not provided in a region of the upper surface of the device chip 20 that overlaps the functional unit 22 at least in plan view. Thereby, the stray capacitance Cf can be suppressed. It is preferable that the metal film 34 is not provided on the entire upper surface of the device chip 20. Thereby, the stray capacitance Cf can be further suppressed.

  The annular electrode 16 is provided on the upper surface of the substrate 10 and surrounds the device chip 20 in a plan view and is joined to the metal sealing portion 30. Thereby, airtight sealing becomes possible.

  FIG. 8 is a cross-sectional view of the electronic component according to the second embodiment. As shown in FIG. 8, in Example 2, a lid 32 is provided on the device chip 20 and the metal sealing portion 30. The lid 32 is a metal plate such as Kovar or an insulating plate. The film thickness of the lid 32 is, for example, 10 μm to 30 μm. The lid 32 is provided on the device chip 20 and the metal sealing portion 30 after the metal film 34 is formed. Thus, the lid 32 is provided on the upper surface of the device chip 20 and the upper surface of the metal film 34 provided on the upper surface of the metal sealing portion 30. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  Thus, the lid 32 may be provided after the metal film 34 is formed. Thereby, the burr 33 can be suppressed and the height can be reduced. Further, since the gap 39 is formed between the device chip 20 and the lid 32, the stray capacitance Cf between the functional unit 22 and the lid 32 can be suppressed even if the lid 32 is a conductor. It is preferable that the gap 39 is provided so as to overlap the functional unit 22 in a plan view. In order to suppress the stray capacitance Cf, the lid 32 is preferably an insulator. By providing the lid 32, the device chip 20 can be protected against an impact from the upper surface. For example, the device chip 20 can be prevented from being damaged by an impact when the device chip 20 is mounted on a printed board or the like.

  The lid 32 is preferably smaller than the metal sealing portion 30 in plan view. Thereby, when the lid 32 is provided on the separated electronic component 100, an alignment margin can be secured.

  FIG. 9 is a cross-sectional view of the electronic component according to the third embodiment. As shown in FIG. 9, a plurality of device chips 20 may be mounted on the substrate 10. The plurality of device chips 20 are, for example, a transmission filter and a reception filter, respectively. Thereby, a multiplexer such as a duplexer can be mounted on one substrate. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  FIG. 10 is a cross-sectional view of an electronic component according to Modification 1 of Embodiment 3. As shown in FIG. 10, a lid 32 is provided on the device chip 20 and the metal film 34. Other configurations are the same as those of the second and third embodiments, and the description thereof is omitted.

  FIG. 11 is a cross-sectional view of the electronic component according to the fourth embodiment. As shown in FIG. 11, the substrate 10 includes a support substrate 10d and a piezoelectric substrate 10c. The support substrate 10d and the piezoelectric substrate 10c are joined. A functional unit 11 is provided on the upper surface of the piezoelectric substrate 10c. The functional unit 11 is opposed to the functional unit 22 via the gap 38. The functional unit 11 is, for example, the same surface acoustic wave element as the functional unit 22 in FIG. Via wirings 14 penetrating the piezoelectric substrate 10c and the support substrate 10d are provided. The via wiring 14 electrically connects the terminals 12a and 12c. The piezoelectric substrate 10c at the periphery of the support substrate 10d is removed, and an annular electrode 16 is provided. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  As in the fourth embodiment, the functional unit 11 may be provided on the upper surface of the substrate 10, and the functional units 11 and 22 may be opposed to each other through the gap 38. The support substrate 10d may not be provided. The functional unit 11 may be the same piezoelectric thin film resonator as that shown in FIG.

  FIG. 12 illustrates an electronic component according to Modification 1 of Embodiment 4. As shown in FIG. 12, the upper surface and the side surface of the metal sealing portion 30 are inclined to form an integral plane. Other configurations are the same as those of the fourth embodiment, and the description thereof is omitted. As in the first modification of the fourth embodiment, at least one of the upper surface and the side surface of the metal sealing portion 30 may be inclined.

  In the fourth embodiment and its modification, the function unit 22 is a transmission filter and the function unit 11 is a reception filter, whereby a multiplexer such as a duplexer can be obtained.

  In the first to fourth embodiments and the modifications thereof, the functional units 22 and 11 may be other than the surface acoustic wave device or the acoustic wave device such as the piezoelectric thin film resonator. For example, the functional unit may be an active element such as an amplifier and / or a switch. The functional unit may be a passive element such as an inductor and / or a capacitor.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Board | substrate 16 Ring electrode 20 Device chip 22 Functional part 26 Metal film 30 Metal sealing part 32 Lid 34 Metal film 36 Bump

Claims (10)

A substrate,
A functional part is provided on the lower surface, a first metal film is provided on the side surface, the first metal film is not provided on the upper surface, and the functional part and the upper surface of the substrate are opposed to each other through a gap. A device chip mounted on the upper surface of the substrate;
A metal sealing portion made of a brazing material that surrounds the device chip and is bonded to the first metal film and the upper surface of the substrate and seals the gap;
A second metal film that is provided on a side surface and an upper surface of the metal sealing portion, and is not provided in a region overlapping at least the functional portion in a plan view of the upper surface of the device chip;
An electronic component comprising:   The electronic component according to claim 1, wherein a lid is not provided on the upper surface of the device chip.   The electronic component according to claim 1, further comprising a lid provided on an upper surface of the device chip and an upper surface of the second metal film provided on an upper surface of the metal sealing portion.   The electronic component according to claim 3, wherein a gap is formed between the device chip and the lid.   5. The electronic component according to claim 1, further comprising an annular metal film that is provided on an upper surface of the substrate and surrounds the device chip in a plan view and is bonded to the metal sealing portion.   The electronic component according to claim 1, wherein the second metal film is not provided on the entire upper surface of the device chip.   The electronic component according to claim 1, wherein the functional unit is an acoustic wave element. A functional chip is provided on the lower surface, a first metal film is provided on the side surface, and a device chip not provided with the first metal film is provided on the upper surface so that the functional part and the upper surface of the substrate face each other with a gap. Mounting on the upper surface of the substrate;
Forming a metal sealing portion made of a brazing material on the upper surface of the substrate so as to surround the device chip and to be bonded to the upper surface of the first metal film and the substrate and seal the gap;
Cutting the metal sealing portion and the substrate using a dicing blade in a state where a lid is not provided on the metal sealing portion and the upper surface of the substrate,
Of electronic parts including   After the step of dividing into individual pieces, a barrel plating method is used, provided on the side surface and the upper surface of the metal sealing portion, and not provided in a region overlapping at least the functional portion in a plan view among the upper surface of the device chip. The manufacturing method of the electronic component of Claim 8 including the process of forming 2 metal films. 10. The electronic component according to claim 8, further comprising a step of planarizing an upper surface of the device chip and the metal sealing portion after the step of forming the metal sealing portion and before the step of dividing into pieces. Production method.

Images