JP6810599B2 - Electronic components and their manufacturing methods - Google Patents

Description

The present invention relates to an electronic component and a manufacturing method thereof, for example, an electronic component in which a second substrate is mounted on a first substrate and a manufacturing method thereof.

A technique is known in which a piezoelectric substrate is bonded onto a support substrate such as a sapphire substrate to form an elastic wave element on the upper surface of the piezoelectric substrate (for example, Patent Document 1). It is known that two substrates having elastic wave elements formed on their surfaces are joined via an intermediate layer so that the elastic wave elements face each other through a gap (for example, Patent Document 2).

Japanese Unexamined Patent Publication No. 2004-186868 Japanese Patent Publication No. 2008-546207

When a composite substrate in which a piezoelectric substrate is bonded and another substrate are laminated on a support substrate, chipping and / or cracks occur in the substrate when an attempt is made to cut the composite substrate and the other substrate together.

The present invention has been made in view of the above problems, and an object of the present invention is to suppress the occurrence of chipping and / or cracks.

The present invention is a step of irradiating a region to be cut of a first substrate having a support substrate and a piezoelectric substrate joined to the upper surface of the support substrate and having a functional portion on the upper surface to form a groove in the support substrate. After the step of mounting the structure including the second substrate on the first substrate and the step of mounting the structure so that the lower surfaces of the second substrate face each other with a gap in the functional portion. A step of cutting the structure in the region to be cut using a dicing method, a step of cutting the structure, and then a step of cutting the support substrate in the region to be cut starting from the groove. It is a manufacturing method of an electronic component including.

In the above configuration, the step of mounting the structure includes a step of surrounding the second substrate in a plan view, joining the second substrate to the first substrate, and forming a sealing portion overlapping the region to be cut. The cutting step can include a step of cutting the sealing portion in the region to be cut.

In the above configuration, the step of forming the groove on the support substrate includes a step of forming the groove on the upper surface of the support substrate before the step of mounting the structure, and is a step of cutting the structure. At least a part of the groove may remain on the support substrate.

In the above configuration, the sealing portion may be a metal sealing portion.

In the above configuration, the step of mounting the structure includes the step of mounting the structure so that the second substrate overlaps the region to be cut, and the step of cutting the structure should be cut. The configuration may include a step of cutting the second substrate in the region.

In the above configuration, the step of cutting the structure may include a step of cutting the piezoelectric substrate in the region to be cut.

In the above configuration, the groove may be provided on the lower surface of the support substrate.

In the above configuration, the lower surface of the second substrate may be provided with a second functional portion facing the functional portion via a gap.

In the above configuration, the piezoelectric substrate may be a lithium tantalate substrate or a lithium niobate substrate, and the support substrate may be a sapphire substrate, an alumina substrate, or a spinel substrate.

The present invention includes a first side surface provided on the upper surface side and having a curved surface that bends outward as it goes down, a second side surface provided below the first side surface and having a polycrystallized surface, and the first side surface. A first support substrate comprising a third side surface provided from the side surface to the lower surface side and having a substantially vertical flat surface, and a piezoelectric substrate joined to the upper surface of the support substrate and having a functional portion on the upper surface. It is an electronic component including a substrate and a second substrate mounted on the first substrate so that the lower surfaces of the second substrate face each other with a gap in the functional portion.

According to the present invention, the occurrence of chipping and / or cracking can be suppressed.

1 (a) and 1 (b) are a cross-sectional view and a plan view of the electronic component according to the first embodiment. FIG. 2A is a plan view of the functional unit, and FIG. 2B is a cross-sectional view of the functional unit. 3 (a) to 3 (d) are cross-sectional views (No. 1) showing a method of manufacturing an electronic component according to the first embodiment. 4 (a) to 4 (d) are cross-sectional views (No. 2) showing a method of manufacturing an electronic component according to the first embodiment. 5 (a) to 5 (c) are cross-sectional views (No. 3) showing a method of manufacturing an electronic component according to the first embodiment. 6 (a) and 6 (b) are cross-sectional views (No. 4) showing a method of manufacturing an electronic component according to the first embodiment. FIG. 7 is a cross-sectional view showing the vicinity of the end face of the substrate in the first embodiment. 8 (a) and 8 (b) are cross-sectional views showing a method of manufacturing an electronic component according to Comparative Example 1. 9 (a) and 9 (b) are cross-sectional views showing a method of manufacturing an electronic component according to a modification 1 of the first embodiment. 10 (a) and 10 (b) are cross-sectional views showing a method of manufacturing an electronic component according to a modification 2 of the first embodiment. 11 (a) to 11 (c) are cross-sectional views showing a method of manufacturing an electronic component according to a second embodiment. 12 (a) to 12 (c) are cross-sectional views (No. 1) showing a method of manufacturing an electronic component according to a third embodiment. 13 (a) to 13 (c) are cross-sectional views (No. 2) showing a method of manufacturing an electronic component according to the third embodiment. FIG. 14 is a circuit diagram of the duplexer according to the fourth embodiment.

Hereinafter, examples of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a cross-sectional view and a plan view of the electronic component according to the first embodiment. FIG. 1B illustrates the device chip 21 and the annular metal layer 37. As shown in FIG. 1A, the substrate 10 has a support substrate 10a and a piezoelectric substrate 10b. The support substrate 10a is, for example, a sapphire substrate, a spinel substrate, an alumina substrate, or a silicon substrate. The piezoelectric substrate 10b is, for example, a lithium tantalate substrate or a lithium niobate substrate. The piezoelectric substrate 10b is joined to the upper surface of the support substrate 10a. The joint surface between the piezoelectric substrate 10b and the support substrate 10a is flat and flat.

A terminal 14 is provided on the lower surface of the substrate 10. The terminal 14 is a foot pad for connecting the functional units 12 and 22 to the outside. The functional unit 12 and the wiring 18 are provided on the upper surface of the substrate 10. A via wiring 16 penetrating the substrate 10 is provided. The terminal 14, the via wiring 16, and the wiring 18 are metal layers such as a copper layer, an aluminum layer, or a gold layer. The via wiring 16 electrically connects the wiring 18 and the terminal 14. The piezoelectric substrate 10b on the outer edge of the substrate 10 is removed, and an annular metal layer 37 is provided on the support substrate 10a instead. The annular metal layer 37 may be provided on the piezoelectric substrate 10b. An annular electrode 36 is provided on the annular metal layer 37. The annular electrode 36 and the annular metal layer 37 are metal layers such as a copper layer, a nickel layer, a titanium layer, a gold layer, an aluminum layer and a silver layer, or a laminated film thereof.

The device chip 21 has a substrate 20 and a functional unit 22. A functional unit 22 and a wiring 28 are provided on the lower surface of the substrate 20. The substrate 20 is an insulating substrate such as a sapphire substrate, a spinel substrate, an alumina substrate, or a silicon substrate, or a semiconductor substrate. The wiring 28 is a metal layer such as a copper layer, an aluminum layer or a gold layer. The substrate 20 is flip-chip mounted (face-down mounted) on the substrate 10 via bumps 38. The bump 38 is, for example, a gold bump, a solder bump or a copper bump. The bump 38 joins the wires 28 and 18.

A sealing portion 30 is provided on the substrate 10 so as to surround the device chip 21 in a plan view. The sealing portion 30 is a metal material such as solder. The sealing portion 30 is joined to the upper surface of the annular electrode 36. A flat plate-shaped lid 32 is provided on the upper surface of the substrate 20 and the upper surface of the sealing portion 30. The lid 32 is, for example, a metal plate such as Kovar or an insulating plate. A protective film 34 is provided so as to cover the lid 32 and the sealing portion 30. The protective film 34 is a metal film such as a nickel film.

The functional parts 12 and 22 face each other through the gap 25. The void 25 is sealed by the sealing portion 30, the substrate 10, the substrate 20, and the lid 32. The bump 38 is surrounded by the void 25.

The terminal 14 is electrically connected to the functional unit 12 via the via wiring 16 and the wiring 18. Further, the terminal 14 is electrically connected to the functional unit 22 via the via wiring 16, the wiring 18, the bump 38, and the wiring 28. The sealing portion 30 is grounded.

As shown in FIG. 1B, the annular metal layer 37 is provided on the peripheral edge of the substrate 10 and surrounds the device chip 21. The outer circumference of the support substrate 10a is located outside the outer circumference of the annular metal layer 37.

FIG. 2A is a plan view of the functional unit 12, and FIG. 2B is a cross-sectional view of the functional unit 22. As shown in FIG. 2A, the functional unit 12 is a surface acoustic wave resonator. An IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 10. The IDT 40 has a pair of comb-shaped electrodes 40a facing each other. The comb-shaped electrode 40a has a plurality of electrode fingers 40b and a bus bar 40c for connecting the plurality of electrode fingers 40b. Reflectors 42 are provided on both sides of the IDT 40. IDT40 excites surface acoustic waves on the piezoelectric substrate 10b. The IDT 40 and the reflector 42 are formed of, for example, an aluminum film or a copper film. A protective film or a temperature compensation film may be provided to cover the IDT 40 and the reflector 42. In this case, it functions as the functional unit 12 including the protective film or the temperature compensation film.

As shown in FIG. 2B, the functional unit 22 is a piezoelectric thin film resonator. A piezoelectric film 46 is provided on the substrate 20. The lower electrode 44 and the upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 20. The lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. The lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film. The piezoelectric film 46 is, for example, an aluminum nitride film.

Functional parts 12 and 22 include electrodes that excite elastic waves. Therefore, the functional portions 12 and 22 are covered with voids 25 so as not to regulate elastic waves.

Hereinafter, each material and dimensions of Example 1 will be illustrated. The support substrate 10a is a sapphire substrate having a film thickness of 100 μm. The piezoelectric substrate 10b is a lithium tantalate substrate having a film thickness of 10 μm to 20 μm. When the coefficient of linear thermal expansion of the support substrate 10a is smaller than that of the piezoelectric substrate 10b, the frequency temperature dependence of the elastic wave element of the functional unit 12 becomes small. The terminal 14 is a copper layer having a film thickness of 2 μm, a nickel layer having a film thickness of 5 μm, and a gold layer having a film thickness of 0.5 μm from the support substrate 10a side. The via wiring is a copper via wiring. The bump 38 is a gold bump. The substrate 20 is a silicon substrate. The sealing portion 30 is SnAg solder. The lid 32 is a Coval plate having a film thickness of 15 μm. The protective film 34 is a nickel layer having a film thickness of 10 μm.

[Manufacturing method of Example 1]
3 (a) to 6 (b) are cross-sectional views showing a method of manufacturing an electronic component according to the first embodiment. As shown in FIG. 3A, the lower surface of the piezoelectric substrate 10b is joined to the upper surface of the support substrate 10a. This bonding is performed in a wafer state. Examples of the joining method include a method of activating the upper surface of the support substrate 10a and the lower surface of the piezoelectric substrate 10b to join at room temperature, a method of joining with an adhesive, and the like. The cutting region 80 is a region where the substrate 10 should be cut.

As shown in FIG. 3B, a desired opening 50 is formed in the piezoelectric substrate 10b. The opening 50 is formed, for example, by performing a blasting method on a patterned photoresist as a mask. In addition to the blast method, an ion milling method or a wet etching method may be used.

As shown in FIG. 3C, via holes are formed in the piezoelectric substrate 10b and the support substrate 10a. The via hole is formed by, for example, irradiating a laser beam. A seed layer (not shown) is formed in the via hole and in the opening 50. An electric current is supplied to the seed layer, and a via wire 16 is formed in the via hole and an annular metal layer 37 is formed in the opening 50 by using an electrolytic plating method. When the via wiring 16 and the annular metal layer 37 are copper layers, the seed layer can be, for example, a titanium film having a film thickness of 100 μm and a copper layer having a film thickness of 200 μm from the substrate 10 side. Unnecessary plating layer is removed by using CMP (Chemical Mechanical Polishing) method or the like.

As shown in FIG. 3D, the functional portion 12 and the wiring 18 are formed on the upper surface of the piezoelectric substrate 10b. The functional unit 12 is, for example, a titanium film and an aluminum film from the substrate 10 side. The wiring 18 is, for example, a titanium film and a gold film from the substrate 10 side.

As shown in FIG. 4A, the annular electrode 36 is formed on the annular metal layer 37. The annular electrode 36 is, for example, a titanium film and a nickel film from the substrate 10 side, and is formed by a vapor deposition method and a lift-off method. As shown in FIG. 4B, the substrate 10 in the cutting region 80 is irradiated with the laser beam 70 from the upper surface. As a result, the groove 60 is formed on the upper surface of the support substrate 10a and the piezoelectric substrate 10b. The depth of the groove 60 in the support substrate 10a is, for example, 30 μm. The laser light 70 is, for example, a YGA laser light or a carbon dioxide gas laser light. A laser ablation device is used as the laser device.

As shown in FIG. 4C, the lower surface of the substrate 10 is polished or ground. As a result, the via wiring 16 is exposed from the lower surface of the substrate 10. As shown in FIG. 4D, the terminal 14 is formed so as to come into contact with the via wiring 16. For example, a seed layer is formed on the lower surface of the substrate 10. A photoresist with an opening is formed under the seed layer. An electric current is supplied to the seed layer to form a plating layer in the opening by using an electrolytic plating method. After that, the seed layer other than the plating layer is removed. The seed layer can be, for example, a titanium film and a copper film from the substrate 10 side. The plating layer can be, for example, a copper layer, a nickel layer, and a gold layer from the substrate 10 side.

As shown in FIG. 5A, the substrate 20 is flip-chip mounted on the substrate 10. The substrate 20 is a device chip 21 after being individualized, and gold stud bumps are formed as bumps 38 on the lower surface of the substrate 20.

As shown in FIG. 5B, a solder plate is arranged on the substrate 10 so as to cover the substrate 20. The lid 32 is arranged on the solder plate. The solder plate is pressed against the substrate 10 by the lid 32 and heated above the melting point of the solder plate. For example, the melting point of SnAg solder is about 220 ° C., which is 230 ° C. or higher. As a result, the solder plate is melted and the sealing portion 30 is formed. The sealing portion 30 forms an alloy with the annular electrode 36. As a result, the sealing portion 30 is joined to the annular electrode 36. Since the lid 32 has good solder wettability, the sealing portion 30 is joined to the lid 32. The lid 32 contacts the upper surface of the substrate 20 but does not join. Since the inner surface of the groove 60 has poor wettability, the sealing portion 30 is not joined. As described above, the structure 82 is formed from the device chip 21, the sealing portion 30, and the lid 32.

As shown in FIG. 5C, the lower surface of the substrate 10 is protected by a protective film 52 such as a photoresist. A resin tape 54 is attached under the protective film 52. The lid 32, the sealing portion 30, and the piezoelectric substrate 10b in the cutting region 80 are cut using the dicing blade 72. As a result, a groove 62 is formed in the lid 32, the sealing portion 30, and the piezoelectric substrate 10b. The groove 60 in the support substrate 10a remains. The groove 60 in the support substrate 10a is left at a depth of at least 30 μm or more.

As shown in FIG. 6A, the tape 54 is peeled off, and the resin tape 56 is attached onto the lid 32. The break blade 74 is pressed from the lower surface so as to overlap the groove 60. As a result, the support substrate 10a is cut from the groove 60 as a starting point. The blade 74 may be pressed from the upper surface of the tape 56. As a result, cracks 64 are formed in the support substrate 10a and are separated into the electronic component 100.

As shown in FIG. 6B, the electronic component 100 is peeled off from the tape 56. A plurality of electronic components 100 are put into a barrel (not shown), and the barrel is put into the plating tank 58. The protective film 34 is formed by using the barrel plating method. The protective film 34 is, for example, a nickel film having a film thickness of 10 μm. The protective film 34 is mainly formed on the surface of a metal material. Therefore, the protective film 34 is formed on the upper surface of the lid 32, the side surface of the sealing portion 30, and the side surface of the annular metal layer 37, but is not formed on the side surface of the substrate 10 and the lower surface of the protective film 52. After the protective film 34 is formed, the protective film 52 is peeled off. As a result, the electronic components shown in FIGS. 1A and 1B are completed.

FIG. 7 is a cross-sectional view showing the vicinity of the end face of the substrate 10 in the first embodiment. The support substrate 10a has three types of end faces 11a to 11c. The end face 11a is an end face formed by blade dicing, and is a curved surface that curves as it goes down. The end face 11b is an end face formed by the laser beam 70, and has a tapered shape located outward as it goes down. The surface of the end face 11b is melted by the heat of the laser beam 70. As a result, the polycrystalline layer 61 is formed on the end face 11b. The end face 11c is a cut end face and is formed substantially vertically. The height H1 of the end face 11a is, for example, 10 μm to 20 μm, and the width W1 is, for example, 30 μm to 35 μm. The height H2 of the end face 11b is, for example, 10 μm to 20 μm, and the width W2 is, for example, 5 μm to 10 μm. The height H3 of the end face 11c is, for example, 65 μm to 70 μm.

[Manufacturing method of Comparative Example 1]
8 (a) and 8 (b) are cross-sectional views showing a method of manufacturing an electronic component according to Comparative Example 1. As shown in FIG. 8 (a), in any of the steps of FIGS. 3 (a) to 4 (a) of Example 1, a groove 68 is formed on the upper surface of the piezoelectric substrate 10b in the cutting region 80. As shown in FIG. 4 (b), the gap 25 is sealed by the sealing portion 30 and the lid 32 in the same manner as in FIG. 5 (b) of the first embodiment. When the sealing portion 30 is formed, air may remain between the sealing portion 30 and the substrate 10 to form voids. Since the air escapes from the groove 68, it is possible to prevent the formation of voids between the sealing portion 30 and the substrate 10. As shown in FIG. 8B, it is attached to the tape 54, and the lid 32, the sealing portion 30, and the substrate 10 are cut using a dicing blade. After that, the protective film 34 is formed in the same manner as in FIG. 6 (b).

In Comparative Example 1, chipping and / or cracks occur at 77 near the interface between the support substrate 10a and the piezoelectric substrate 10b and 78 near the lower surface of the support substrate 10a. This is because the support substrate 10a is hard. In this way, when the structure 82 including the substrate 20 is mounted on the substrate 10 of the support substrate 10a and the piezoelectric substrate 10b and an attempt is made to cut the structure 82 and the substrate 10, chipping and / or cracks occur in the support substrate 10a. appear. When the support substrate 10a is cut starting from the groove, the occurrence of chipping and cracks is suppressed. However, since the structure 82 is mounted on the support substrate 10a, it is difficult to divide the structure 82 from the groove as a starting point.

According to the first embodiment, as shown in FIG. 4B, the cutting region 80 to be cut of the substrate 10 (first substrate) is irradiated with the laser beam 70 to form a groove 60 in the support substrate 10a. As shown in FIG. 5B, the structure 82 including the substrate 20 is mounted on the substrate 10 so that the lower surface of the substrate 20 (second substrate) faces the functional portion 12 with the gap 25 interposed therebetween. After that, as shown in FIG. 5C, the structure 82 is cut in the cutting region 80 by using the dicing method. As shown in FIG. 6A, the support substrate 10a is cut from the groove 60 in the cutting region 80.

In this way, the groove 60 is formed in the support substrate 10a in advance, the structure 82 is cut, and then the support substrate 10a is cut from the groove 60 as a starting point to chip and / or crack the substrate 10 and the structure 82. Can be cut while suppressing.

As shown in FIG. 5B, in the step of mounting the structure 82, the substrate 20 is joined to the surrounding substrate 10 in a plan view to form a sealing portion 30 that overlaps the cutting region 80. As shown in FIG. 5C, in the step of cutting the structure 82, a step of cutting the sealing portion 30 in the cutting region 80 is included. Thereby, when the structure 82 includes the substrate 20 and the sealing portion 30, the structure 82 and the substrate 10 can be cut while suppressing chipping and / or cracking.

As shown in FIG. 4B, the step of forming the groove 60 on the support substrate 10a is a step of forming the groove 60 on the upper surface of the support substrate 10a before the step of mounting the structure 82 of FIG. 5B. including. In the step of cutting the structure 82 of FIG. 5C, at least a part of the groove 60 is left in the support substrate 10a. As a result, the support substrate 10a can be divided from the groove 60 as the starting point in FIG. 6A. Further, when the sealing portion 30 is formed, air is released through the groove 60, so that the formation of voids can be suppressed.

A functional unit 22 (second functional unit) facing the functional unit 12 via the gap 25 is provided on the lower surface of the substrate 20. As a result, the substrates 10 and 20 having the functional portions 12 and 22 can be laminated.

As shown in FIG. 7, the electronic component manufactured by the method of the first embodiment has an end surface 11a (first side surface) provided on the upper surface side and has a curved surface that bends outward as it goes down. The end face 11b (second side surface) is provided below the end face 11a and its surface is polycrystalline. The end face 11c is provided on the lower surface side from the end face 11b and has a substantially vertical plane.

9 (a) and 9 (b) are cross-sectional views showing a method of manufacturing an electronic component according to a modification 1 of the first embodiment. As shown in FIG. 9 (a), the piezoelectric substrate 10b in the cutting region 80 is removed in any of the steps of FIGS. 3 (a) to 4 (a) of Example 1. At this time, all the piezoelectric substrates 10b between the annular metal layers 37 are removed. As shown in FIG. 9B, the groove 60 is formed in the support substrate 10a by irradiating the laser beam 70. Subsequent steps are the same as in the first embodiment, and the description thereof will be omitted.

10 (a) and 10 (b) are cross-sectional views showing a method of manufacturing an electronic component according to a modification 2 of the first embodiment. As shown in FIG. 9 (a), the piezoelectric substrate 10b in the cutting region 80 is removed in any of the steps of FIGS. 3 (a) to 4 (a) of Example 1. At this time, the piezoelectric substrate 10b in the center of the cutting region 80 is removed, and the piezoelectric substrates 10b on both sides remain. As shown in FIG. 9B, the groove 60 is formed in the support substrate 10a by irradiating the laser beam 70. Subsequent steps are the same as in the first embodiment, and the description thereof will be omitted.

As in the first and second modifications of the first embodiment, at least a part of the piezoelectric substrate 10b in the cutting region 80 is removed before the groove 60 is formed in the support substrate 10a. As a result, when the groove 60 is formed, the support substrate 10a can be directly irradiated with the laser beam 70. As a result, a sharp groove 60 can be formed, and chipping and / or cracking at the time of cutting can be further suppressed.

11 (a) to 11 (c) are cross-sectional views showing a method of manufacturing an electronic component according to a second embodiment. As shown in FIG. 11A, a groove 68 is formed on the upper surface of the piezoelectric substrate 10b in the cutting region 80. The groove 68 suppresses the formation of voids in the sealing portion 30. The groove 68 may penetrate the piezoelectric substrate 10b, or may be formed only on the upper portion of the piezoelectric substrate 10b. The support substrate 10a in the cutting region 80 is irradiated with the laser beam 70 from the lower surface. As a result, a groove 60 is formed on the lower surface of the support substrate 10a. The depth of the groove 60 is, for example, 30 μm.

As shown in FIG. 11B, the dicing blade 72 is used to cut the lid 32, the sealing portion 30, and the piezoelectric substrate 10b in the same manner as in FIG. 5C of the first embodiment. As shown in FIG. 11 (c), the blade 74 is pressed against the lower surface of the support substrate 10a in the cutting region 80 in the same manner as in FIG. 6 (a) of the first embodiment. As a result, the support substrate 10a is cut. Other steps are the same as in the first embodiment, and the description thereof will be omitted.

As in the second embodiment, the groove 60 may be provided on the lower surface of the support substrate 10a.

12 (a) to 13 (c) are cross-sectional views showing a method of manufacturing an electronic component according to a third embodiment. As shown in FIG. 12A, the functional unit 12, the terminal 14, the via wiring 16 and the wiring 18 are formed on the substrate 10 as in the first embodiment. A groove 60 is formed in the support substrate 10a by irradiating the substrate 10 in the cutting region 80 with the laser beam 70 from the upper surface. As shown in FIG. 12B, bumps 38 are formed on the wiring 18 on the substrate 10. An annular metal layer 35 is formed on the substrate 10 so as to surround the functional portion 12 and the wiring 18. The bump 38 and the annular metal layer 35 are, for example, a copper layer, a gold layer or a solder layer.

As shown in FIG. 12 (c), the substrate 20 is mounted on the substrate 10. The functional portion 22 and the wiring 28 are formed on the lower surface of the substrate 20. The bump 38 is joined to the wiring 28. The functional unit 22 and the wiring 28 are surrounded by the annular metal layer 35. The annular metal layer 35 seals the functional portions 12 and 22 in the voids 25. The substrates 10 and 20 are in a wafer state, and the substrate 20 is not cut in the cutting region 80.

As shown in FIG. 13A, the lower surface of the substrate 10 is attached to the tape 54. The substrate 20 is cut by the dicing blade 72 in the cutting region 80. The dicing blade 72 may cut the piezoelectric substrate 10b.

As shown in FIG. 13B, the upper surface of the substrate 20 is attached to the tape 56. The blade 74 is pressed against the substrate 10 from the lower surface in the cutting region 80. As a result, the support substrate 10a is cut. As shown in FIG. 13 (c), the tapes 54 and 56 are peeled off. As a result, the electronic component according to the third embodiment is formed.

According to the third embodiment, as shown in FIG. 12C, the substrate 20 is mounted on the substrate 10 so that the substrate 20 overlaps the cutting region 80. As shown in FIG. 13A, after the substrate 20 is mounted on the substrate 10, the substrate 20 in the cutting region 80 is cut. As described above, the structure may be the substrate 20.

Example 4 is an example of a multiplexer such as a duplexer. FIG. 14 is a circuit diagram of the duplexer according to the fourth embodiment. As shown in FIG. 14, a transmission filter 90 is connected between the common terminal Ant and the transmission terminal Tx. A reception filter 92 is connected between the common terminal Ant and the reception terminal Rx. The transmission filter 90 passes a signal in the transmission band among the high frequency signals input from the transmission terminal Tx through the common terminal Ant and suppresses other signals. The reception filter 92 passes a signal in the reception band among the high frequency signals input to the common terminal Ant and suppresses other signals.

The transmission filter 90 is formed by the functional units 22 of Examples 1 to 3, and the reception filter 92 is formed by the functional units 12 of Examples 1 to 3. As a result, the electronic components of Examples 1 to 3 function as a duplexer. Although the example of a duplexer has been described as a multiplexer, a triplexer or a quadplexer may be used.

In Examples 1 to 3 and modifications thereof, both the functional parts 12 and 22 may be surface acoustic wave elements. The functional unit 22 may be other than the elastic wave element. For example, the functional unit 22 may be an active element such as an amplifier and / or a switch. Further, the functional unit 22 may be a passive element such as an inductor and / or a capacitor.

Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10, 20 Substrate 10a Support substrate 10b Piezoelectric substrate 12, 22 Functional part 21 Device chip 30 Encapsulation part 32 Lid 38 Bump 60, 62, 68 Grooves

Claims (10)

A step of irradiating a region to be cut of a first substrate provided with a support substrate and a piezoelectric substrate joined to the upper surface of the support substrate and having a functional portion on the upper surface to form a groove in the support substrate.
A step of mounting a structure including the second substrate on the first substrate so that the lower surfaces of the second substrate face each other with a gap in the functional portion.
After the step of mounting the structure, a step of cutting the structure in the region to be cut by using a dicing method and a step of cutting the structure.
After the step of cutting the structure, a step of cutting the support substrate starting from the groove in the region to be cut, and a step of cutting the support substrate.
Manufacturing methods for electronic components, including. The step of mounting the structure includes a step of surrounding the second substrate in a plan view, joining the second substrate to the first substrate, and forming a sealing portion overlapping the region to be cut.
The method for manufacturing an electronic component according to claim 1, wherein the step of cutting the structure includes a step of cutting the sealing portion in the region to be cut. The step of forming the groove on the support substrate includes a step of forming the groove on the upper surface of the support substrate before the step of mounting the structure.
The method for manufacturing an electronic component according to claim 2, wherein at least a part of the groove remains on the support substrate in the step of cutting the structure. The method for manufacturing an electronic component according to claim 2 or 3, wherein the sealing portion is a metal sealing portion. The step of mounting the structure includes a step of mounting the structure so that the second substrate overlaps the region to be cut.
The method for manufacturing an electronic component according to claim 1, wherein the step of cutting the structure includes a step of cutting the second substrate in the region to be cut. The method for manufacturing an electronic component according to any one of claims 1 to 5, wherein the step of cutting the structure includes a step of cutting the piezoelectric substrate in the region to be cut. The method for manufacturing an electronic component according to any one of claims 1 to 6, wherein the groove is provided on the lower surface of the support substrate. The method for manufacturing an electronic component according to any one of claims 1 to 7, wherein a second functional portion facing the functional portion via a gap is provided on the lower surface of the second substrate. The method for manufacturing an electronic component according to any one of claims 1 to 8, wherein the piezoelectric substrate is a lithium tantalate substrate or a lithium niobate substrate, and the support substrate is a sapphire substrate, an alumina substrate, or a spinel substrate. From the first side surface provided on the upper surface side and having a curved surface that bends outward as it goes down, the second side surface provided below the first side surface and having a polycrystalline surface, and the second side surface. A support substrate provided with a third side surface provided on the lower surface side and having a substantially vertical plane, and a first substrate provided with a piezoelectric substrate joined to the upper surface of the support substrate and having a functional portion on the upper surface.
The second substrate mounted on the first substrate and the second substrate so that the lower surfaces of the second substrate face each other with a gap in the functional portion.
Electronic components equipped with.

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