JP2019021998A - Electronic component - Google Patents

Abstract

To suppress a pressure applied to a piezoelectric substrate.SOLUTION: An electronic component includes a support substrate 10a having a first through hole 15a in which a first through electrode 16a is embedded, a piezoelectric substrate 10b having an opening 15c for exposing the first through hole, and bonded onto the support substrate, a first bump 28a overlapping the first through hole in the plan view, and connected with the first through electrode in the opening, and a device chip 11 mounted on the piezoelectric substrate via the first bump, so as to face the piezoelectric substrate via a cavity 26.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic component, and relates to an electronic component having a piezoelectric substrate.

  An acoustic wave device having improved frequency temperature characteristics by using a bonded substrate in which a piezoelectric substrate is bonded to the upper surface of a support substrate is known (for example, Patent Document 1). Further, in a configuration in which the piezoelectric substrate is bonded to a part of the upper surface of the support substrate and the wiring extends on the piezoelectric substrate from the region of the upper surface of the support substrate where the piezoelectric substrate is not bonded, the side surface of the piezoelectric substrate is defined as an inclined surface. By doing so, it is known to suppress disconnection of wiring (for example, Patent Document 2).

JP 2004-343359 A JP 2013-21387 A

  Stress is applied to the piezoelectric substrate when the bonding substrate having the piezoelectric substrate connected to the support substrate and another substrate are mounted using bumps. For this reason, the piezoelectric substrate may be damaged, such as a crack being introduced into the piezoelectric substrate.

  This invention is made | formed in view of the said subject, and it aims at suppressing the pressure added to a piezoelectric substrate.

  The present invention relates to a support substrate having a first through hole in which a first through electrode is embedded, a piezoelectric substrate having an opening through which the first through hole is exposed, and bonded to the support substrate. Mounted on the piezoelectric substrate through the first bump so as to be opposed to the piezoelectric substrate through a gap and a first bump that overlaps the first through hole and is connected to the first through electrode in the opening. An electronic component comprising the device chip.

  The said structure WHEREIN: The said 1st bump can be set as the structure which does not contact the said piezoelectric substrate.

  In the above configuration, a bonding area between the first through electrode and the first bump is farther from the device chip than a bonding area between the support substrate and the piezoelectric substrate, and a part of the first bump is the first bump. It can be set as the structure embedded in the through-hole.

  In the above configuration, the device chip includes a functional element that is provided on the device chip so as to face the piezoelectric substrate through the gap and is electrically connected to the first through electrode through the first bump. Can do.

  In the above configuration, the support substrate and the piezoelectric substrate have a second through hole in which a second through electrode is embedded, and the electronic component is a wiring provided in the piezoelectric substrate and connected to the second through hole And a second bump that overlaps the wiring and is connected to the wiring without overlapping the second through hole in plan view, and the device chip is disposed on the piezoelectric substrate via the first bump and the second bump. It can be set as the structure mounted in.

  The said structure WHEREIN: It can be set as the structure which comprises the acoustic wave element provided in the said piezoelectric substrate so as to oppose the said device chip via the said space | gap, and was electrically connected with the said 2nd penetration electrode.

  In the above configuration, the piezoelectric substrate may be a lithium tantalate substrate or a lithium niobate substrate.

  According to the present invention, the distortion of the substrate can be suppressed and the heat dissipation can be enhanced.

FIG. 1A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIG. 2A is a plan view of the functional element 12, and FIG. 2B is a cross-sectional view of the functional element 22. FIG. 3 is an enlarged view of the vicinity of the through electrode 16a and the bump 28a in the first embodiment. FIG. 4A to FIG. 4D are cross-sectional views (part 1) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 5A to FIG. 5C are cross-sectional views (part 2) illustrating the method of manufacturing the electronic component according to the first embodiment. FIG. 6A to FIG. 6C are cross-sectional views (part 3) illustrating the method of manufacturing the electronic component according to the first embodiment. FIG. 7 is a cross-sectional view of an electronic component according to Comparative Example 1. FIG. 8 is a cross-sectional view of the electronic component according to the first modification of the first embodiment. FIG. 9 is a cross-sectional view of the electronic component according to the second modification of the first embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A is a cross-sectional view of the electronic component according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. The surface direction of the substrate 10 is defined as the X direction and the Y direction, and the thickness direction of the substrate 20 is defined as the Z direction. As shown in FIGS. 1A and 1B, the substrate 10 includes a support substrate 10a and a piezoelectric substrate 10b. The support substrate 10a is, for example, a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate. The piezoelectric substrate 10b is, for example, a tantalum lithium substrate or a lithium niobate substrate. The piezoelectric substrate 10b is bonded to the upper surface of the support substrate 10a. The linear thermal expansion coefficient of the support substrate 10a is smaller than that of the piezoelectric substrate 10b.

  A functional element 12 and a metal layer 14 b are provided on the upper surface of the substrate 10. The metal layer 14 b is a wiring that connects the through electrode 16 a, the bump 28 b, and the functional element 12. Terminals 18 a and 18 b are provided on the lower surface of the substrate 10. Terminals 18a and 18b are foot pads for connecting functional elements 12 and 22 to the outside. A through hole 15a penetrating the support substrate 10a and an opening 15c penetrating the piezoelectric substrate 10b are formed. The through hole 15a overlaps the opening 15c, and the through hole 15a is smaller than the opening 15c.

  The right through electrode 16a is embedded in a part of the through hole 15a. A metal layer 14a is provided on the side surface of the opening 15c, the upper surface of the support substrate 10a exposed from the opening 15c, the upper side surface of the through hole 15a, and the upper surface of the through electrode 16a exposed from the through hole 15a. The metal layer 14a is a pad to which the through electrode 16a and the bump 28a are connected. The through electrode 16a electrically connects the metal layer 14a and the terminal 18a.

  The left through electrode 16b is embedded in a through hole 15b formed by the through hole 15a and the opening 15c. The upper surface of the through electrode 16b and the upper surface of the piezoelectric substrate 10b are flat. The upper surface of the through electrode 16b is in contact with the metal layer 14b. The through electrode 16b electrically connects the metal layer 14b and the terminal 18b.

  The piezoelectric substrate 10b is removed at the outer edge of the substrate 10, and an annular metal layer 32 is provided on the support substrate 10a. The metal layers 14a and 14b, the through electrodes 16a and 16b, the terminals 18a and 18b, and the annular metal layer 32 are metal layers such as a copper layer, an aluminum layer, or a gold layer, for example. An annular electrode 34 is provided on the annular metal layer 32. The annular electrode 34 is a metal layer such as a nickel layer, a copper layer, an aluminum layer, or a gold layer.

  A functional element 22 and a metal layer 24 are provided on the lower surface of the substrate 20. The metal layer 24 is a wiring and a pad. The substrate 20 is an insulating substrate or a semiconductor substrate such as a silicon substrate, a glass substrate, a sapphire substrate, an alumina substrate, a spinel substrate, or a quartz substrate. The metal layer 24 is a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 20 is flip-chip mounted (face-down mounted) on the substrate 10 via bumps 28a and 28b. The bumps 28a and 28b are, for example, gold bumps, solder bumps, or copper bumps. The bump 28a is embedded in the upper portion of the through hole 15a and connected to the through electrode 16a through the metal layer 14a. The bump 28b is joined to the metal layer 14b in a region that does not overlap the through electrode 16b in plan view.

  A sealing portion 30 is provided on the substrate 10 so as to surround the substrate 20. The sealing part 30 is a metal such as solder or a resin. The sealing part 30 is joined to the annular electrode 34. If the bonding property between the annular metal layer 32 and the sealing portion 30 is good, the annular electrode 34 may be omitted. A flat lid 36 is provided on the upper surface of the substrate 20 and the upper surface of the sealing portion 30. The lid 36 is a metal plate such as a Kovar plate or an insulating plate, for example. A protective film 38 is provided so as to cover the lid 36 and the sealing portion 30. The protective film 38 is a metal film such as a nickel film or an insulating film. The upper surface of the substrate 10 may be covered with the sealing portion 30. The lid 36 may not be provided.

  The functional element 12 faces the substrate 20 with a gap 26 interposed therebetween. The functional element 22 faces the piezoelectric substrate 10b with a gap 26 interposed therebetween. The functional elements 12 and 22 are sealed by the sealing portion 30, the substrate 10, the substrate 20, and the lid 36. The bumps 28 a and 28 b are surrounded by the gap 26.

  The terminal 18a is electrically connected to the functional element 12 through the through electrode 16a, the metal layer 14a, the bump 28a, and the metal layer 24. The terminal 18b is electrically connected to the functional element 12 via the through electrode 16b and the metal layer 14b, and is further electrically connected to the functional element 22 via the bump 28b and the metal layer 24.

  FIG. 2A is a plan view of the functional element 12, and FIG. 2B is a cross-sectional view of the functional element 22. As shown in FIG. 2A, the functional element 12 is a surface acoustic wave resonator. An IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 10. The IDT 40 has a pair of comb electrodes 40a facing each other. The comb-shaped electrode 40a includes a plurality of electrode fingers 40b and a bus bar 40c that connects the plurality of electrode fingers 40b. The reflectors 42 are provided on both sides of the IDT 40. The IDT 40 excites a surface acoustic wave on the piezoelectric substrate 10b. The IDT 40 and the reflector 42 are made of, for example, an aluminum film or a copper film.

  As shown in FIG. 2B, the functional element 22 is a piezoelectric thin film resonator. A piezoelectric film 46 is provided on the substrate 20. A lower electrode 44 and an upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 20. The lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. The lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film, and the piezoelectric film 46 is an aluminum nitride film, for example. The substrate 20 is an insulating substrate or a semiconductor substrate.

  The functional elements 12 and 22 include electrodes that excite elastic waves. For this reason, the functional elements 12 and 22 are covered with the space | gap 26 so that an elastic wave may not be restrict | limited.

  FIG. 3 is an enlarged view of the vicinity of the through electrode 16a and the bump 28a in the first embodiment. FIG. 3 shows an example of the first embodiment. The support substrate 10a is a sapphire substrate, and the piezoelectric substrate 10b is a 42 ° rotated Y-cut X-propagating lithium titanate substrate. The terminals 18a are a titanium film 18c, a copper film 18d, a nickel film 18e, and a gold film 18f from the substrate 10 side. The through electrode 16a is a seed layer 17a and a plating layer 17b from the outside. The seed layer 17a is a titanium layer and a copper layer, and the plating layer 17b is a copper layer.

  A barrier layer 17 is provided between the metal layer 14a and the piezoelectric substrate 10b, the support substrate 10a, and the through electrode 16a. The barrier layer 17 is a tantalum film, and the metal layer 14a is a gold layer. The annular metal layer 32 is a seed layer 32a and a plating layer 32b from the outside. The seed layer 17a is a titanium layer and a copper layer, and the plating layer 17b is a copper layer. The annular electrode 34 is a titanium layer 34a, a nickel layer 34b, and a gold layer 34c from the substrate 10 side. The bump 28a is a gold bump. The metal layer 24 is a gold layer. The sealing part 30 is a tin silver solder. Since the gold layer 34c has good wettability with tin silver solder, the sealing portion 30 is joined to the gold layer 34c.

  When the through electrode 16a and the bump 28a are made of the same metal, the metal layer 14a and the barrier layer 17 need not be provided. When the through electrode 16a and the bump 28a are different metals, it is preferable to provide a barrier layer 17 that suppresses interdiffusion of atoms between the through electrode 16a and the bump 28a. In order to increase the bonding strength between the barrier layer 17 and the bump 28a, it is preferable to provide a metal layer 14a made of the same metal as the bump 28a.

  The thickness L2 of the piezoelectric substrate 10b and the thickness L1 of the support substrate 10a are, for example, 20 μm and 100 μm. The width W1 (for example, diameter) of the through holes 15a and 15b is 40 μm, for example. The width W2 (for example, the diameter) of the opening 15c is, for example, 70 μm. The width W3 of the upper surface of the support substrate 10a exposed from the opening 15c is, for example, 5 μm. The distance L3 between the upper surface of the support substrate 10a and the upper surface of the through electrode 16a is, for example, 33 μm to 50 μm. An angle θ1 formed between the side surface of the through hole 15a and the lower surface of the support substrate 10a is, for example, 80 ° to 85 °. An angle θ2 formed between the side surface of the opening 15c and the lower surface of the piezoelectric substrate 10b is, for example, 60 ° to 70 °. A distance L4 between the upper surface of the piezoelectric substrate 10b and the lower surface of the metal layer 24 is, for example, 10 μm or more, for example, 20 μm to 30 μm.

[Production Method of Example 1]
4A to 6C are cross-sectional views illustrating the method for manufacturing the electronic component according to the first embodiment. As shown in FIG. 4A, the lower surface of the piezoelectric substrate 10b is bonded to the upper surface of the support substrate 10a. The support substrate 10a and the piezoelectric substrate 10b may be directly bonded via an amorphous layer of several nm or the like, or may be bonded by an adhesive or the like.

  As shown in FIG. 4B, the piezoelectric substrate 10b is etched to form an opening 15c. As shown in FIG.4 (c), the through-hole 15a is formed in the support substrate 10a in the opening 15c. At this time, the through hole 15a does not penetrate the support substrate 10a. The through hole 15a is formed, for example, by laser beam irradiation.

  As shown in FIG. 4D, seed layers 17a and 32a (see FIG. 3) are formed on the inner surface of the through hole 15a, the inner surface of the opening 15c, and the upper surface of the piezoelectric substrate 10b by using a sputtering method, for example. Plating layers 17b and 32b (see FIG. 3) are formed by passing a current through the seed layer. Through the CMP (Chemical Mechanical Polishing) method, the through electrodes 16a and 16b, the annular metal layer 32 and the upper surface of the piezoelectric substrate 10b are planarized. Thereby, the through electrodes 16a and 16b and the annular metal layer 32 embedded in the through hole 15a and the opening 15c are formed.

  As shown in FIG. 5A, a mask layer 50 having an opening 52 is formed on the piezoelectric substrate 10b. The opening 52 is formed on the through electrode 16a. The upper portion of the through electrode 16a is etched using the mask layer 50 as a mask. As shown in FIG. 5B, a barrier layer 17 is formed on the top of the through hole 15a, in the opening 15c, and on the top surface of the through electrode 16a. Further, the barrier layer 17 is formed on the through electrode 16b. The barrier layer 17 is formed using a vacuum deposition method and a lift-off method. As shown in FIG. 5C, the functional element 12 is formed on the piezoelectric substrate 10b.

  As shown in FIG. 6A, a mask layer 54 having an opening 56 is formed on the piezoelectric substrate 10b. Metal layers 14a and 14b are formed using a vacuum deposition method. By lifting off, the metal layer 14a is formed on the barrier layer 17 in the through hole 15a and the opening 15c, and the metal layer 14b is formed on the barrier layer 17 on the through electrode 16b. In FIG. 6A and subsequent figures, illustration of the barrier layer 17 is omitted. As shown in FIG. 6B, an annular electrode 34 is formed on the outer edge of the substrate 20 using a vacuum deposition method and a lift-off method.

  As shown in FIG. 6C, the substrate 20 is flip-chip mounted on the substrate 10. The bump 28a is a gold bump formed by using, for example, a plating method. For this reason, the cross section of the bump 28a is rectangular, for example, and the height of the bump 28a is larger than the width. A lower portion of the bump 28a is embedded in the through hole 15a. Thereby, stress is applied to the bump 28a in the lateral direction, and the bonding between the bump 28a and the substrate 10 becomes strong. Since the bump 28b has a large area, it is firmly bonded to the metal layer 14b. The bump 28a may be a stud bump. In order to ensure the height of the bump 28a, the bump 28a may be formed by stacking a plurality of stud bumps.

  Thereafter, the lower surface of the support substrate 10a is polished using a CMP method or the like. Thus, the through electrodes 16a and 16b are exposed on the lower surface of the support substrate 10a. Terminals 18a and 18b are formed in contact with the through electrodes 16a and 16b, respectively. Thereby, the electronic component which concerns on Example 1 shown to Fig.1 (a) and FIG.1 (b) is manufactured.

[Comparative Example 1]
FIG. 7 is a cross-sectional view of an electronic component according to Comparative Example 1. As shown in FIG. 7, the through electrode 16 is embedded in the through hole 15b, and the upper surface of the through electrode 16 and the upper surface of the piezoelectric substrate 10b are flat. A metal layer 14 is provided on the through electrode 16. Bumps 28 are bonded on the metal layer 14. In order to reduce the chip area, it is preferable that the through electrode 16 and the bump 28 overlap in plan view.

  However, when the substrate 20 is flip-chip mounted on the substrate 10, stress is applied from the bump 28 to a region 58 where the opening 15 c and the piezoelectric substrate 10 b are in contact with each other. As a result, cracks and the like are introduced into the piezoelectric substrate 10b. Thus, the piezoelectric substrate 10b is mechanically deteriorated. In order to suppress this, like the bump 28b and the through electrode 16b in FIG. 1, the bump 28b and the through electrode 16b are arranged so as not to overlap in a plan view. Thereby, the stress applied from the bump 28b to the vicinity of the opening 15c can be suppressed. However, since the bump 28b and the through electrode 16b do not overlap, the chip area increases.

[Effect of Example 1]
According to the first embodiment, the support substrate 10a includes the through hole 15a (first through hole) in which the through electrode 16a (first through electrode) is embedded. The piezoelectric substrate 10b has an opening 15c through which the through hole 15a is exposed, and is bonded onto the support substrate 10a. The bump 28a (first bump) overlaps the through hole 15a in a plan view and is connected to the through electrode 16a in the opening 15c. The substrate 10 (device chip) is mounted on the piezoelectric substrate 10b via the bumps 28a so as to face the piezoelectric substrate 10b via the gap 26.

  Since the bumps 28a overlap with the through holes 15a, the chip area can be reduced. By connecting the bump 28a to the through electrode 16a in the opening 15c, the stress applied to the piezoelectric substrate 10b from the bump 28a can be suppressed. Therefore, deterioration such as destruction of the piezoelectric substrate 10b can be suppressed.

  The bump 28a does not contact the piezoelectric substrate 10b. Thereby, the stress applied to the piezoelectric substrate 10b from the bump 28a can be further suppressed.

  The bonding region between the through electrode 16a and the bump 28a is farther from the substrate 10 than the bonding region between the support substrate 10a and the piezoelectric substrate 10b, and a part of the bump 28a is embedded in the upper portion of the through hole 15a. Thereby, the bumps 28a are joined to the upper portions of the through holes 15a, and the bumps 28a can be firmly bonded to the through electrodes 16a. In FIG. 3, the distance L3 is preferably about 1/3 to 1/2 of the thickness L1 of the support substrate 10a in order to fit the bumps 28a to the through holes 15a. When the thickness L1 of the support substrate 10a is 100 μm, the distance L3 is preferably 33 μm to 50 μm.

  The functional element 22 is opposed to the piezoelectric substrate 10b through the air gap 26, and is electrically connected through the through electrode 16a and the bump 28a. Thereby, the terminal 18a and the functional element 22 can be electrically connected.

  The support substrate 10a and the piezoelectric substrate 10b have a through hole 15b (second through hole) in which the through electrode 16b (second through electrode) is embedded. The metal layer 14b (wiring) is provided on the upper surface of the piezoelectric substrate 10b and connected to the through electrode 16b. The bump 28b (second bump) does not overlap with the through hole 15b in a plan view and overlaps with the metal layer 14b and is connected to the metal layer 14b. The substrate 20 is mounted on the piezoelectric substrate 10b via bumps 28a and 28b. Thus, the substrate 20 may be flip-chip mounted on the substrate 10 via the bumps 28b in addition to the bumps 28a.

  The functional element 12 (elastic wave element) is provided on the upper surface of the piezoelectric substrate 10b so as to face the substrate 20 through the air gap 26, and is electrically connected to the through electrode 16b. When the angle θ2 of the side surface of the opening 15c is large, the coverage of the metal layer 14a is poor, and it is difficult to connect the metal layer 14a to the functional element 12. Therefore, the through electrodes 16a and the bumps 28a that are not electrically connected to the functional element 12 (elastic wave element) are provided so as to overlap in plan view. The through electrode 16b and the bump 28b that are electrically connected to the functional element 12 can be provided so as not to overlap in plan view.

  When the piezoelectric substrate 10b is a lithium tantalate substrate or a lithium niobate substrate, the piezoelectric substrate 10b is easily damaged mechanically. Therefore, it is preferable to provide the through electrode 16a and the bump 28a.

[Modification 1 of Example 1]
FIG. 8 is a cross-sectional view of the electronic component according to the first modification of the first embodiment. As shown in FIG. 8, the through electrode 16 a and the bump 28 a may be used for the through electrode and the bump electrically connected to the functional element 12. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  When the angle θ2 of the side surface of the opening 15c of the piezoelectric substrate 10b is as small as 60 ° or less, for example, the coverage of the metal layer 14a is improved. Therefore, the through electrode 16a and the functional element 12 can be electrically connected via the metal layers 14a and 14b. For this reason, all the bumps 28a can be overlapped with the through electrodes 16a. Therefore, the chip area can be further reduced.

[Modification 2 of Embodiment 1]
FIG. 9 is a cross-sectional view of the electronic component according to the second modification of the first embodiment. As shown in FIG. 9, the through electrode 16a is provided up to the upper surface of the support substrate 10a. Other configurations are the same as those of the first embodiment, and the description thereof is omitted. When the bonding strength between the bump 28a and the through electrode 16a is sufficiently high, the bump 28a may not be embedded in the upper portion of the through hole 15a.

  In the first embodiment and its modification, the example in which the sealing portion 30 is provided so as to surround the substrate 10 has been described, but the sealing portion 30 may not be provided. Although the acoustic wave element has been described as an example of the functional elements 12 and 22, the functional element 22 may be a passive element such as an inductor or a capacitor, an active element including a transistor, or a MEMS (Micro Electro Mechanical Systems) element.

  Each of the functional elements 12 and 22 may form an elastic wave filter. The functional elements 12 and 22 may form a multiplexer such as a duplexer, a triplexer, or a quadplexer.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10, 20 Substrate 10a Support substrate 10b Piezoelectric substrate 12, 22 Functional element 14a, 14b, 24 Metal layer 15a, 15b Through hole 15c Opening 16a, 16b Through electrode 18a, 18b Terminal 26 Gap 28a, 28b Bump

Claims (7)

A support substrate having a first through hole in which the first through electrode is embedded;
A piezoelectric substrate having an opening through which the first through hole is exposed and bonded onto the support substrate;
A first bump that overlaps the first through hole in plan view and is connected to the first through electrode in the opening;
A device chip mounted on the piezoelectric substrate via the first bump so as to face the piezoelectric substrate via a gap;
An electronic component comprising:   The electronic component according to claim 1, wherein the first bump does not contact the piezoelectric substrate.   A bonding region between the first through electrode and the first bump is farther from the device chip than a bonding region between the support substrate and the piezoelectric substrate, and a part of the first bump is embedded in the first through hole. The electronic component according to claim 1 or 2.   4. The electron according to claim 1, further comprising a functional element provided on the device chip so as to face the piezoelectric substrate through the gap and electrically connected to the first through electrode through the first bump. parts. The support substrate and the piezoelectric substrate have a second through hole in which a second through electrode is embedded,
The electronic component includes a wiring provided on the piezoelectric substrate and connected to the second through hole, and a second bump that does not overlap the second through hole in a plan view and overlaps the wiring and is connected to the wiring. And
5. The electronic component according to claim 1, wherein the device chip is mounted on the piezoelectric substrate via the first bump and the second bump. 6.   The electronic component according to claim 5, further comprising an acoustic wave element provided on the piezoelectric substrate so as to face the device chip through the gap and electrically connected to the second through electrode. The electronic component according to claim 1, wherein the piezoelectric substrate is a lithium tantalate substrate or a lithium niobate substrate.

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