JP2018532271A - インターコネクトのための選択的なボトムアップ式金属フィーチャ充填 - Google Patents

インターコネクトのための選択的なボトムアップ式金属フィーチャ充填 Download PDF

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JP2018532271A
JP2018532271A JP2018519330A JP2018519330A JP2018532271A JP 2018532271 A JP2018532271 A JP 2018532271A JP 2018519330 A JP2018519330 A JP 2018519330A JP 2018519330 A JP2018519330 A JP 2018519330A JP 2018532271 A JP2018532271 A JP 2018532271A
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Prior art keywords
metal
dielectric layer
cobalt
gas
concave feature
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JP2018519330A
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Japanese (ja)
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JP2018532271A5 (https=
Inventor
ユ，カイ−フン
エヌ． タピリー，カンダバラ
エヌ． タピリー，カンダバラ
ディー． クラーク，ロバート
ディー． クラーク，ロバート
ジェイ． ルーシンク，ゲリット
ジェイ． ルーシンク，ゲリット
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Publication of JP2018532271A publication Critical patent/JP2018532271A/ja
Publication of JP2018532271A5 publication Critical patent/JP2018532271A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4405—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
JP2018519330A 2015-10-15 2016-10-14 インターコネクトのための選択的なボトムアップ式金属フィーチャ充填 Pending JP2018532271A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562242167P 2015-10-15 2015-10-15
US62/242,167 2015-10-15
PCT/US2016/057181 WO2017066671A1 (en) 2015-10-15 2016-10-14 Selective bottom-up metal feature filling for interconnects

Publications (2)

Publication Number Publication Date
JP2018532271A true JP2018532271A (ja) 2018-11-01
JP2018532271A5 JP2018532271A5 (https=) 2019-08-15

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JP2018519330A Pending JP2018532271A (ja) 2015-10-15 2016-10-14 インターコネクトのための選択的なボトムアップ式金属フィーチャ充填

Country Status (4)

Country Link
US (1) US10014213B2 (https=)
JP (1) JP2018532271A (https=)
KR (1) KR102740084B1 (https=)
WO (1) WO2017066671A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2021015030A1 (https=) * 2019-07-25 2021-01-28
JP2021520637A (ja) * 2018-04-03 2021-08-19 東京エレクトロン株式会社 完全自己整合方式を使用するサブトラクティブ相互接続形成

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US10580644B2 (en) 2016-07-11 2020-03-03 Tokyo Electron Limited Method and apparatus for selective film deposition using a cyclic treatment
US11404313B2 (en) 2017-04-26 2022-08-02 Applied Materials, Inc. Selective tungsten deposition at low temperatures
US10256144B2 (en) 2017-04-26 2019-04-09 Applied Materials, Inc. Process integration approach of selective tungsten via fill
KR102640002B1 (ko) * 2018-07-17 2024-02-27 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치, 기록매체, 및 프로그램
JP2020043139A (ja) * 2018-09-06 2020-03-19 東京エレクトロン株式会社 埋め込み方法及び処理システム
JP7182970B2 (ja) * 2018-09-20 2022-12-05 東京エレクトロン株式会社 埋め込み方法及び処理システム
US11387112B2 (en) * 2018-10-04 2022-07-12 Tokyo Electron Limited Surface processing method and processing system
KR102759932B1 (ko) * 2018-10-10 2025-01-23 도쿄엘렉트론가부시키가이샤 반도체 소자의 함입형 형상부를 저-저항률 금속으로 충전하기 위한 방법
US20200251340A1 (en) * 2019-02-04 2020-08-06 Applied Materials, Inc. Methods and apparatus for filling a feature disposed in a substrate
US11282745B2 (en) * 2019-04-28 2022-03-22 Applied Materials, Inc. Methods for filling features with ruthenium
US11164780B2 (en) 2019-06-07 2021-11-02 Applied Materials, Inc. Process integration approach for selective metal via fill
US11094588B2 (en) 2019-09-05 2021-08-17 Applied Materials, Inc. Interconnection structure of selective deposition process
WO2022243274A1 (en) 2021-05-19 2022-11-24 Merck Patent Gmbh Selective deposition of ruthenium film by utilizing ru(i) precursors
TWI844913B (zh) 2022-08-11 2024-06-11 力晶積成電子製造股份有限公司 內連線結構
US20260011548A1 (en) * 2024-07-02 2026-01-08 Applied Materials, Inc. Reduced underlayer oxidation during gap fill

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JPH03202471A (ja) * 1989-09-26 1991-09-04 Canon Inc 堆積膜形成法
JPH0637038A (ja) * 1992-07-15 1994-02-10 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPH10214896A (ja) * 1996-11-29 1998-08-11 Toshiba Corp 半導体装置の製造方法及び製造装置
JP2001085378A (ja) * 1999-09-13 2001-03-30 Sony Corp 半導体装置およびその製造方法
US20100248473A1 (en) * 2009-03-31 2010-09-30 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
JP2013526012A (ja) * 2010-03-30 2013-06-20 東京エレクトロン株式会社 半導体装置のための金属含有キャップ層の表面洗浄及び選択的堆積

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US7998864B2 (en) * 2008-01-29 2011-08-16 International Business Machines Corporation Noble metal cap for interconnect structures
US7830010B2 (en) 2008-04-03 2010-11-09 International Business Machines Corporation Surface treatment for selective metal cap applications
US7670894B2 (en) 2008-04-30 2010-03-02 Intel Corporation Selective high-k dielectric film deposition for semiconductor device
GB2473200B (en) * 2009-09-02 2014-03-05 Pragmatic Printing Ltd Structures comprising planar electronic devices
EP2674996A1 (en) * 2012-06-15 2013-12-18 Imec VZW Method for growing nanostructures in recessed structures
US9236292B2 (en) * 2013-12-18 2016-01-12 Intel Corporation Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
US9488615B2 (en) * 2014-12-17 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Biosensor with a sensing surface on an interlayer dielectric

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03202471A (ja) * 1989-09-26 1991-09-04 Canon Inc 堆積膜形成法
JPH0637038A (ja) * 1992-07-15 1994-02-10 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPH10214896A (ja) * 1996-11-29 1998-08-11 Toshiba Corp 半導体装置の製造方法及び製造装置
JP2001085378A (ja) * 1999-09-13 2001-03-30 Sony Corp 半導体装置およびその製造方法
US20100248473A1 (en) * 2009-03-31 2010-09-30 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
JP2013526012A (ja) * 2010-03-30 2013-06-20 東京エレクトロン株式会社 半導体装置のための金属含有キャップ層の表面洗浄及び選択的堆積

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021520637A (ja) * 2018-04-03 2021-08-19 東京エレクトロン株式会社 完全自己整合方式を使用するサブトラクティブ相互接続形成
JP7348441B2 (ja) 2018-04-03 2023-09-21 東京エレクトロン株式会社 完全自己整合方式を使用するサブトラクティブ相互接続形成
JPWO2021015030A1 (https=) * 2019-07-25 2021-01-28

Also Published As

Publication number Publication date
US20170110368A1 (en) 2017-04-20
WO2017066671A1 (en) 2017-04-20
KR102740084B1 (ko) 2024-12-06
KR20180063317A (ko) 2018-06-11
US10014213B2 (en) 2018-07-03

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