JP2018525861A - ラインアクティビティ検出器を伴うuart - Google Patents

ラインアクティビティ検出器を伴うuart Download PDF

Info

Publication number
JP2018525861A
JP2018525861A JP2017563283A JP2017563283A JP2018525861A JP 2018525861 A JP2018525861 A JP 2018525861A JP 2017563283 A JP2017563283 A JP 2017563283A JP 2017563283 A JP2017563283 A JP 2017563283A JP 2018525861 A JP2018525861 A JP 2018525861A
Authority
JP
Japan
Prior art keywords
uart
edge detector
coupled
module
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017563283A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018525861A5 (https=
Inventor
ロシャン サミュエル,
ロシャン サミュエル,
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of JP2018525861A publication Critical patent/JP2018525861A/ja
Publication of JP2018525861A5 publication Critical patent/JP2018525861A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/069DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by detecting edges or zero crossings
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver only

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2017563283A 2015-06-23 2016-06-22 ラインアクティビティ検出器を伴うuart Pending JP2018525861A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562183272P 2015-06-23 2015-06-23
US62/183,272 2015-06-23
US15/188,464 2016-06-21
US15/188,464 US10425268B2 (en) 2015-06-23 2016-06-21 UART with line activity detector
PCT/US2016/038614 WO2016209861A1 (en) 2015-06-23 2016-06-22 Uart with line activity detector

Publications (2)

Publication Number Publication Date
JP2018525861A true JP2018525861A (ja) 2018-09-06
JP2018525861A5 JP2018525861A5 (https=) 2019-07-11

Family

ID=56345242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017563283A Pending JP2018525861A (ja) 2015-06-23 2016-06-22 ラインアクティビティ検出器を伴うuart

Country Status (7)

Country Link
US (1) US10425268B2 (https=)
EP (1) EP3314450A1 (https=)
JP (1) JP2018525861A (https=)
KR (1) KR20180020164A (https=)
CN (1) CN107810495B (https=)
TW (1) TW201702895A (https=)
WO (1) WO2016209861A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI806483B (zh) * 2022-03-10 2023-06-21 台達電子工業股份有限公司 基於rs232序列埠實現的資料與指令傳輸方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2324688A (en) * 1997-04-25 1998-10-28 Motorola Ltd A modem in which bit rate is determined using the width of a start bit
JPH10313349A (ja) * 1997-05-13 1998-11-24 Fujitsu Ltd データ通信装置
JP2000196700A (ja) * 1998-12-24 2000-07-14 Smc Corp 調歩同期式データ伝送方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4310922A (en) * 1980-01-10 1982-01-12 Lichtenberger W Wayne Bit sampling multiplexer apparatus
JP3166458B2 (ja) * 1993-12-20 2001-05-14 富士通株式会社 タイマー回路
US5715077A (en) * 1994-09-19 1998-02-03 Vlsi Technology, Inc. Multi-mode infrared input/output interface
US5728154A (en) * 1996-02-29 1998-03-17 Minnesota Mining And Manfacturing Company Communication method for implantable medical device
US6385210B1 (en) * 1998-04-17 2002-05-07 Ford Global Technologies, Inc. Method for detecting and resolving data corruption in a UART based communication network
FR2830954A1 (fr) 2001-10-15 2003-04-18 St Microelectronics Sa Dispositif de transmission de donnees asynchrones comprenant des moyens de controle de deviation d'horloge
CN101361313B (zh) * 2006-01-23 2017-06-09 半导体元件工业有限责任公司 形成通信电路的方法
JP5541234B2 (ja) * 2011-06-08 2014-07-09 株式会社デンソー トランシーバ
US20140015362A1 (en) * 2012-07-13 2014-01-16 Hsi-Chieh CHENG Sphere zone coupling of magnetic devices and multiple applications
US20140153623A1 (en) * 2012-11-30 2014-06-05 Dinkle Enterprise Co., Ltd. Device for auto baud rate detection
CN105684385B (zh) * 2013-09-04 2020-05-19 飞利浦灯具控股公司 用于通过dmx网络的互联网协议通信的方法和设备
US10049072B2 (en) * 2013-11-18 2018-08-14 Infineon Technologies Ag Method and apparatus for use in a data processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2324688A (en) * 1997-04-25 1998-10-28 Motorola Ltd A modem in which bit rate is determined using the width of a start bit
JPH10313349A (ja) * 1997-05-13 1998-11-24 Fujitsu Ltd データ通信装置
JP2000196700A (ja) * 1998-12-24 2000-07-14 Smc Corp 調歩同期式データ伝送方法

Also Published As

Publication number Publication date
KR20180020164A (ko) 2018-02-27
US10425268B2 (en) 2019-09-24
CN107810495A (zh) 2018-03-16
TW201702895A (zh) 2017-01-16
CN107810495B (zh) 2021-07-06
WO2016209861A1 (en) 2016-12-29
EP3314450A1 (en) 2018-05-02
US20160380798A1 (en) 2016-12-29

Similar Documents

Publication Publication Date Title
CN107771331B (zh) 独立式uark brk检测
US9852104B2 (en) Coexistence of legacy and next generation devices over a shared multi-mode bus
US20090077298A1 (en) Methods and apparatus for bridged data transmission and protocol translation in a high-speed serialized data system
US10891242B2 (en) Embedded USB2 (eUSB2) repeater operation
EP3268868B1 (en) Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus
US10139875B2 (en) Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus
Mahat Design of a 9-bit UART module based on Verilog HDL
KR101129748B1 (ko) 활성 전원 관리 상태로부터의 탈출 대기 시간의 최적화
CN107534548A (zh) 用于基于脉冲的多线链路的时钟和数据恢复
US8639851B2 (en) Serial bit processor
Gupta et al. Analysis of Universal Asynchronous Receiver-Transmitter (UART)
EP3050261B1 (en) Can fd end-of-frame detector, can bit stream processing device, method for detecting the end of a can fd frame, and method of operating a can bit stream processor
US20150234773A1 (en) Technique to avoid metastability condition and avoid unintentional state changes of legacy i2c devices on a multi-mode bus
JP2018525861A (ja) ラインアクティビティ検出器を伴うuart
CN219181725U (zh) Can数据帧同步结构及氛围灯光流帧同步控制系统
WO2023159415A1 (en) Adaptive low-power signaling to enable link signal error recovery without increased link clock rates
CN210405365U (zh) 多协议聚合传输装置及系统
JPH03174643A (ja) 直列データ母線用アプリケーシヨン特有集積回路
CN115694773B (zh) 私有can总线帧同步结构及其搭建的氛围灯光流控制系统
CN111130675B (zh) 一种基于时间触发网络的时间同步装置
US6697385B1 (en) Circuit(s), method(s) and architecture for configurable packet re-timing in network repeater hubs
CN109842575B (zh) 一种429总线接收节点大容差采样电路
KR20020047962A (ko) 등시전송 효율을 높인 인터페이스 장치 및 방법
TIWARI et al. FPGA IMPLEMENTATION OF ADVANCED UART CONTROLLER USING VHDL

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190604

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190604

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200521

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200804

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20210304