JP2018523405A5 - - Google Patents

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JP2018523405A5
JP2018523405A5 JP2018500909A JP2018500909A JP2018523405A5 JP 2018523405 A5 JP2018523405 A5 JP 2018523405A5 JP 2018500909 A JP2018500909 A JP 2018500909A JP 2018500909 A JP2018500909 A JP 2018500909A JP 2018523405 A5 JP2018523405 A5 JP 2018523405A5
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JP2018500909A 2015-07-20 2016-06-24 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造 Pending JP2018523405A (ja)

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JP2019089969A JP6945589B2 (ja) 2015-07-20 2019-05-10 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造

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US201562194710P 2015-07-20 2015-07-20
US62/194,710 2015-07-20
US15/051,949 2016-02-24
US15/051,949 US9992790B2 (en) 2015-07-20 2016-02-24 Time division duplex (TDD) subframe structure supporting single and multiple interlace modes
PCT/US2016/039408 WO2017014912A1 (en) 2015-07-20 2016-06-24 Time division duplex (tdd) subframe structure supporting single and multiple interlace modes

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JP2018523405A JP2018523405A (ja) 2018-08-16
JP2018523405A5 true JP2018523405A5 (enExample) 2018-10-18

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JP2018500909A Pending JP2018523405A (ja) 2015-07-20 2016-06-24 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造
JP2019089969A Active JP6945589B2 (ja) 2015-07-20 2019-05-10 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造
JP2020086054A Active JP7163338B2 (ja) 2015-07-20 2020-05-15 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造
JP2021212649A Active JP7341215B2 (ja) 2015-07-20 2021-12-27 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造

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JP2020086054A Active JP7163338B2 (ja) 2015-07-20 2020-05-15 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造
JP2021212649A Active JP7341215B2 (ja) 2015-07-20 2021-12-27 シングルインターレースモードおよびマルチインターレースモードをサポートする時分割複信（ｔｄｄ）サブフレーム構造

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US (3) US9992790B2 (enExample)
EP (3) EP4694026A3 (enExample)
JP (4) JP2018523405A (enExample)
KR (2) KR102396226B1 (enExample)
CN (3) CN114629615B (enExample)
AU (3) AU2016296261B2 (enExample)
TW (3) TWI796621B (enExample)
WO (1) WO2017014912A1 (enExample)

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