JP2018520590A - 高速インターリーブアレイの較正 - Google Patents

高速インターリーブアレイの較正 Download PDF

Info

Publication number
JP2018520590A
JP2018520590A JP2017566718A JP2017566718A JP2018520590A JP 2018520590 A JP2018520590 A JP 2018520590A JP 2017566718 A JP2017566718 A JP 2017566718A JP 2017566718 A JP2017566718 A JP 2017566718A JP 2018520590 A JP2018520590 A JP 2018520590A
Authority
JP
Japan
Prior art keywords
adc
component
sub
subcomponent
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017566718A
Other languages
English (en)
Japanese (ja)
Inventor
モシェ・マルキン
Original Assignee
アプライド・マイクロ・サーキット・コーポレーション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アプライド・マイクロ・サーキット・コーポレーション filed Critical アプライド・マイクロ・サーキット・コーポレーション
Publication of JP2018520590A publication Critical patent/JP2018520590A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0204—Channel estimation of multiple channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Radio Transmission System (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
JP2017566718A 2015-06-25 2015-06-25 高速インターリーブアレイの較正 Pending JP2018520590A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/037597 WO2016209231A1 (en) 2015-06-25 2015-06-25 Calibration of high-speed interleaved arrays

Publications (1)

Publication Number Publication Date
JP2018520590A true JP2018520590A (ja) 2018-07-26

Family

ID=57585322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017566718A Pending JP2018520590A (ja) 2015-06-25 2015-06-25 高速インターリーブアレイの較正

Country Status (6)

Country Link
EP (1) EP3314832A4 (ko)
JP (1) JP2018520590A (ko)
KR (1) KR20180034441A (ko)
CN (1) CN108028814B (ko)
CA (1) CA2990153A1 (ko)
WO (1) WO2016209231A1 (ko)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246910A (ja) * 2001-02-20 2002-08-30 Advantest Corp インターリーブａｄ変換方式波形ディジタイザ装置
JP2003133954A (ja) * 2001-10-26 2003-05-09 Agilent Technologies Japan Ltd インターリーブａ／ｄ変換器の校正方法
US20060279445A1 (en) * 2005-06-13 2006-12-14 Kinyua Martin K System and method for improved time-interleaved analog-to-digital converter arrays
JP2010171981A (ja) * 2009-01-26 2010-08-05 Fujitsu Semiconductor Ltd 電流モード回路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8139630B2 (en) * 2005-10-03 2012-03-20 Clariphy Communications, Inc. High-speed receiver architecture
ATE417409T1 (de) * 2006-02-17 2008-12-15 Sicon Semiconductor Ab Zeitverschachtelter analog-digital-wandler
KR20080077755A (ko) * 2007-02-21 2008-08-26 삼성전자주식회사 다중 안테나 시스템에서 신호 보정 장치 및 방법
WO2008156401A1 (en) * 2007-06-21 2008-12-24 Signal Processing Devices Sweden Ab Compensation of mismatch errors in a time-interleaved analog-to-digital converter
JP4623151B2 (ja) * 2008-06-30 2011-02-02 ソニー株式会社 受信装置、受信方法、および無線通信システム
US9036689B2 (en) * 2012-03-29 2015-05-19 Terasquare Co., Ltd. Variable-precision distributed arithmetic multi-input multi-output equalizer for power-and-area-efficient optical dual-polarization quadrature phase-shift-keying system
US8872680B2 (en) * 2012-05-18 2014-10-28 Analog Devices, Inc. Calibrating timing, gain and bandwidth mismatch in interleaved ADCs using injection of random pulses
US9030341B2 (en) * 2012-06-27 2015-05-12 Broadcom Corporation Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)
CN103107966B (zh) * 2013-01-16 2016-03-30 华为技术有限公司 射频信号收发和处理的方法、设备及基站系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246910A (ja) * 2001-02-20 2002-08-30 Advantest Corp インターリーブａｄ変換方式波形ディジタイザ装置
JP2003133954A (ja) * 2001-10-26 2003-05-09 Agilent Technologies Japan Ltd インターリーブａ／ｄ変換器の校正方法
US20060279445A1 (en) * 2005-06-13 2006-12-14 Kinyua Martin K System and method for improved time-interleaved analog-to-digital converter arrays
JP2010171981A (ja) * 2009-01-26 2010-08-05 Fujitsu Semiconductor Ltd 電流モード回路

Also Published As

Publication number Publication date
EP3314832A1 (en) 2018-05-02
KR20180034441A (ko) 2018-04-04
EP3314832A4 (en) 2019-01-30
CA2990153A1 (en) 2016-12-29
WO2016209231A1 (en) 2016-12-29
CN108028814A (zh) 2018-05-11
CN108028814B (zh) 2021-01-05

Similar Documents

Publication Publication Date Title
US9485039B1 (en) Calibration and tracking of receiver
CN111149308B (zh) 多线路时偏的测量和校正方法
KR102570800B1 (ko) 작동 중의 샘플러 오프셋 캘리브레이션
TWI501157B (zh) 減緩資料檢測回授迴路中之潛時的系統與方法
US7787536B2 (en) Adaptive equalizer apparatus with digital eye-opening monitor unit and method thereof
US7158567B2 (en) Method and apparatus for improved high-speed FEC adaptive equalization
CN111868661A (zh) 多线路时偏校正方法和系统
TW200917746A (en) Method and apparatus for baseline wander compensation in ethernet application
US9071262B1 (en) Calibration of high-speed interleaved arrays
TWI420862B (zh) 等化器及其相關之訊號接收器
US9178825B2 (en) Data processing method and apparatus
WO2022105468A1 (zh) 模拟均衡器的校正方法、控制芯片、接收机及存储介质
JP2018520590A (ja) 高速インターリーブアレイの較正
US9160580B2 (en) Adaptive equalizer utilizing eye diagram
US20180048396A1 (en) System, apparatus, and method for at least mitigating a signal reflection
US9294383B2 (en) Baseline wander compensating method, baseline calibration module and ethernet transceiver using the same
WO2008118714A2 (en) Circuits, methods and systems for loss-of-signal detection and equalization
JP6058682B2 (ja) デジタル信号処理装置
US9083446B2 (en) Method and system for processing a signal
US11038518B2 (en) Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit
KR101715084B1 (ko) 무선통신 시스템에서 등화기 샘플링 오류 제거 장치 및 방법
WO2016149871A1 (zh) 接收设备和接收信号的处理方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180622

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20180718

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180823

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190423

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190513

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20191202