WO2008118714A2

WO2008118714A2 - Circuits, methods and systems for loss-of-signal detection and equalization

Info

Publication number: WO2008118714A2
Application number: PCT/US2008/057497
Authority: WO
Inventors: Brian S. Leibowitz; Bruno W. Garlepp; Carl W. Werner; Fred F. Chen
Original assignee: Rambus Incorporated
Priority date: 2007-03-23
Filing date: 2008-03-19
Publication date: 2008-10-02
Also published as: WO2008118714A3

Abstract

A circuit, among other embodiments, includes a combined receiver (sampler), equalizer, adaptive engine (correlator), and LOS circuit. An equalizer circuit provides equalized input signals to the receiver circuit, which outputs data values. The LOS circuit outputs a signal that represents a LOS state when one or more equalized signals fall below an adjustable signal VOffset (or threshold sampling signal). When a LOS state is detected, the adaptation of equalization coefficients is halted until the LOS state is no longer detected, so that the equalizer coefficients will not diverge because of erroneously obtained data values during a LOS state. When a LOS state is not detected, adaptation of equalization coefficients based on received data and error values is allowed to proceed. In one embodiment, portions of the LOS circuit and the adaptive engine circuit are combined. In such an embodiment, adaptation of equalizer coefficients are adjusted based on the received data and error values while the LOS circuit is disabled and LOS status is determined when the adaptive engine is disabled. The adaptive engine is temporarily enabled after the LOS status is determined to be negative (a valid signal is present at the receiver).

Description

CIRCUITS, METHODS AND SYSTEMS FOR LOSS-OF- SIGNAL DETECTION AND EQUALIZATION

FIELD OF THE INVENTION

The present invention relates to high speed signaling.

BACKGROUND OF THE RELATED ART

A signal may be measured to detect a loss-of-signal ("LOS") condition. However, measuring a received signal to determine a LOS condition may be difficult due to a number of factors. First, nominal signal strength of a received signal may vary because a transmitted signal may travel over different channels having, for example, different impedance, length, interconnections and cross-talk, or signal interference. Second, signal strength may vary because different transceivers (transmitters/receivers) are used that have different input/output characteristics and tolerances due to different manufacturing processes. Third, the signal strength may vary over time due to ageing, power supply fluctuations, etc. Additionally, implementing a LOS circuit on an integrated circuit with a receiver, particularly if the LOS circuit is implemented with an analog reference, can be costly in terms of power consumption and surface area occupied on the integrated circuit.

Equalization circuits used to compensate input signals that have been degraded due to inter-symbol interference ("ISI") or noise introduced during the transmission of the signal may also make it difficult to determine a LOS condition. An equalizer circuit may substantially decrease or increase amplitude of a received signal, which in turn may lead to an erroneous determination of a LOS condition if its reference does not adjust accordingly. Also, adaptive equalization circuits may not operate properly, or may diverge, when an LOS condition occurs.

BRIEF DESCRIPTION OF THE DRAWING

Embodiments are illustrated by way of example, and not by way of limitation. In the figures of the accompanying drawing, like reference numerals refer to similar elements.

Fig. 1 illustrates a serial data link system having a circuit including a combined receiver, LOS and equalizer circuit.

Fig. 2 illustrates a circuit including a combined receiver, LOS and equalizer circuit that concurrently equalizes an input signal and detects an LOS condition.

Fig. 3 illustrates a signal eye diagram having a signal envelop (or fuzz band) and adjustable sampling thresholds.

Fig. 4 illustrates a circuit including a combined receiver, LOS and equalizer circuit that detects an LOS condition in response to a control signal.

Fig. 5 illustrates a method to obtain a DOffset value used in adjusting a VOffset (sampling threshold voltage).

Fig. 6 illustrates a method for determining an LOS condition and for adaptively equalizing an input signal.

DETAILED DESCRIPTION

A circuit, among other embodiments, includes a combined receiver (sampler), equalizer and LOS circuit. An equalizer circuit provides equalized input signals to the receiver circuit, which outputs data values. The LOS circuit outputs a signal that represents an LOS state/condition when one or more equalized signals fall below an adjustable VOffset threshold (or a sampling threshold adjusted to a fraction k of the nominal equalized signal swing VSwing). When an LOS state is detected, the adaptation of equalization coefficients is halted until the LOS state is no longer detected, so that the equalizer circuit will not diverge because of erroneously obtained data values during an LOS state. When an LOS state is not detected, adaptation of equalization coefficients based on received data and error values is allowed to proceed.

In an embodiment, the combined receiver, equalizer and LOS circuit includes a first adjust circuit that outputs an adjusted/equalized input signal by summing (differencing) a feedback signal from an equalizer circuit and an input signal. A first sampler outputs a data value to the equalizer circuit and a correlator circuit in response to sampling the equalized input signal. A second adjust circuit outputs an error signal in response to the sum (or difference) of the equalized input signal and an adjustable VOffset signal, which corresponds to the adjustable VOffset level. The error signal is thus indicative of whether the equalized input signal exceeds the adjustable VOffset threshold. A second sampler outputs an error value to the correlator circuit in response to the error signal. The adjustable VOffset signal is output to the second adjust circuit in response to a DOffset value output from the correlator circuit. During equalizer coefficient adaptation, DOffset is adjusted to a value DSwing so that VOffset is equal to VSwing, corresponding to nominal signal amplitude. During LOS determination, DOffset is adjusted to a fraction of DSwing (e.g., k x DSwing, where k < 1 ) so that VOffset is equal to a fraction of the nominal signal amplitude (e.g., VOffset = k x VSwing).

The data and error values are used by a correlator circuit to adjust coefficients of the equalizer circuit during equalization adaptation of the input signal. The equalizer circuit uses the data values and the equalizer coefficients to provide the feedback signal. After adaptively adjusting at least one equalization coefficient of the equalizer circuit using a calculated DSwing value, an LOS circuit is enabled and the correlator circuit is disabled so that coefficients of the equalizer circuit are not adjusted during activation of the LOS circuit. The correlator circuit also outputs a fraction k x DSwing value as a DOffset value during enablement of the LOS circuit. The reduced k x VSwing signal is then used as a sampling threshold VOffset signal in determining an LOS state. When a LOS state is not detected, adaptation of the equalization coefficients is temporarily enabled (correlator circuit enabled), after which the process of checking LOS status is repeated.

In a method embodiment, among other method embodiments, equalization coefficients in an adaptive equalization circuit are initiated. An initial DOffset value, DSwing, is calculated in order to determine an initial VOffset sampling threshold, VSwing, for the second (error) sampler. Adaptive equalization is then enabled using the calculated DSwing value as the DOffset value. At least a single iteration of adaptive equalization is performed. After initialization and during adaptive equalization, the DOffset value is updated so that the sampling threshold VOffset signal tracks the center or mean VSwing value of possible equalized data signal trajectories in an upper fuzz band of a data eye. For example, an input signal is received and summed/differenced with a feedback signal (or equalized/adjusted) from an equalization circuit, such as a Decision Feedback Equalizer ("DFE"). An equalized input signal then may be sampled to obtain a data value. An error value is obtained by sampling the sum/difference of the equalized input signal and the VSwing signal. The data and error values then may be input to an adaptive engine so that equalization coefficients and DSwing (VSwing) value may be adjusted. An LOS circuit then is enabled and a fraction k of the DSwing value is calculated so that a fraction k of the VSwing signal is used as a sampling threshold for the second (error) sampler during LOS detection. If the equalized signal does not cross above k x VSwing signal within a specified time (number of symbol periods), then an LOS condition is detected. In this case, an LOS check is repeated again using the same k x VSwing signal. In the event that an LOS condition occurs N consecutive times, equalization adaptation is re-initialized. If an LOS condition is not detected control transfers such that equalization adaptation of the input signal is repeated.

Fig. 1 illustrates a serial data link system 100 including an integrated circuit 101 , signal path 111 and integrated circuit 102. Integrated circuit 101 transmits a Data signal on signal path 111 using a transmit circuit 103 that includes an output driver 104. The Data signal may include a series of data values represented by signal levels (such as a voltage level/value) in the signal path during successive time periods. The Data signal reaches the integrated circuit 102 as an input signal V_1n and is received by a circuit 105 in integrated circuit 102. Circuit 105 includes an equalizer circuit 106, a loss-of-signal detection (LOS) circuit 107, an adaptive engine 108, a sampler (or receiver) circuit 109, and an adjust circuit 110. In embodiments, adjust circuit 110 may be a sum circuit or difference circuit or other adjust circuit that adjusts an output signal in response to at least two input signals. In particular, adjust circuit 110 receives input signal V_n and outputs an equalized signal V_θq to LOS circuit 107 and to receiver circuit 109. In some embodiments, adjust circuit 110 may simply be a wire connection for combining input signal Vin with a feedback signal current from equalizer circuit 106.

Receiver circuit 109 includes at least one data sampler to sample the equalized signal V_θq and to output Digital Data values/signals. Receiver circuit 109 may also include at least one error sampler (not shown) to sample the equalized signal V_θq and to output Digital Error values/signals (not shown). Adaptive engine 108 receives some or all of the Data values (and the Error values) output from the receiver circuit 109. Adaptive engine 108 may store and use the Data values (as well as the Error values) in adjusting/initializing a set of equalization coefficients COEF, which are used by equalizer circuit 106 in forming a feedback (FDB) (or equalizer) signal. The FDB signal is used by the adjust circuit 110 to adjust the input signal V_1n and produce the equalized signal V_θq.

LOS circuit 107 determines when an LOS state occurs. In embodiments, an LOS state occurs when equalized signal V_θq falls below a sampling threshold during a predetermined period of time. In the event that an LOS state is detected, LOS circuit 107 outputs an LOS signal to adaptive engine circuit 108. In response to the LOS signal, adaptive engine circuit 108 disables adjusting equalization coefficients ("COEF"). In an embodiment, equalizer circuit 106 may provide a feed forward equalizer signal in addition to the FDB signal.

Accordingly, an LOS circuit 107 gates the adjusting of equalization coefficients COEF when an LOS state occurs. By disabling the adjusting of equalization coefficients COEF during an LOS state, equalizer circuit 106 will be prevented from diverging or operating incorrectly because erroneous data values obtained during an LOS state are not being used by the adaptive engine circuit 108 in adjusting the equalization coefficients.

Fig. 2 illustrates a circuit 200 that includes a combined receiver, equalizer and LOS circuit where adaptation of equalization coefficients and LOS state determination occur concurrently. In an embodiment, circuit 200 may be used as circuit 105 illustrated in Fig. 1. Circuit 200 includes adjust circuits 201-203, Digital-to-Analog Converter ("DAC") circuits 204-205, Sampler (receiver) circuits 206-208, DFE circuit 21 1 , Correlator/DOffset circuit 210 and Activity Detect circuit 209. DFE circuit 21 1 and Correlator/DOffset circuit 210 operate similarly to equalizer circuit 106 and adaptive engine circuit 108 shown in Fig. 1. After an initial DOffset value is calculated and output to DAC 204 during initialization of equalization adaptation, a DSwing value is calculated during equalization adaptation and output to DAC 204 as a DOffset value from Correlator/DOffset circuit 210. As shown in the signal eye diagram 300 of Fig. 3, a calculated and updated DSwing value enables a VSwing signal to track a center or mean value of possible equalized signal trajectories in a signal envelope/upper "fuzz band" 301 of data eye 304 at the sample time 305. Signal envelope 301 encloses multiple possible signal trajectories of an equalized signal V_θq around a data eye 304. Calculated DSwing and k x DSwing digital values result in VSwing and k x VSwing signals or voltage values with respect to a reference voltage 303 ("REF") and possible signal trajectories of an equalized signal V_θq

Circuit 200 functions to continually track and update/output a DSwing value as a DOffset value so that a VSwing signal provides a proper reference to sampler 207 to generate Error samples/values used to adjust equalization coefficients COEF during equalization adaptation. Circuit 200 also concurrently detects a LOS condition by Correlator/DOffset circuit 200 updating/outputting a k x DOffset value equal to k x DSwing to DAC 205 so that a k x VSwing signal may be used to determine an LOS condition during equalization adaptation as illustrated in Figs. 2 and 3.

In an embodiment, circuit 200 is initialized by Correlator/DOffset circuit 210 initializing/adjusting/outputting coefficients COEF to DFE circuit 21 1. In an embodiment, Correlator/DOffset circuit 210 receives an INT control signal indicating initialization from an internal register or external source during power-up, reset, calibration and/or periodically. In an embodiment, a DSwing value is calculated for the DOffset value during initialization of equalization coefficients as described in method 500 illustrated in Fig. 5 and described herein. In an embodiment, Correlator/DOffset circuit 210 outputs/adjusts coefficients COEF to DFE circuit 21 1 as well as provides DOffset values (for example calculated DSwing, and k x DSwing values) to DACs 204-205 during equalization and/or LOS detection modes or operation.

After initialization and during an equalization adaptation mode of operation, an input signal V_n and a feedback signal FDB from DFE circuit 21 1 are input to adjust circuit 201. In an embodiment, input signal V_m and a feedback signal FDB are analog voltage signals/values. Input signal V_n may be provided from an external signal path, such as signal path 1 1 1 shown in Fig. 1.

An equalized signal V_θq is output from adjust circuit 201 to Sampler circuit 206 and adjust circuits 202 and 203. Sampler circuit 206 outputs a digital Data value to Correlator/DOffset circuit 210 in response to a Clock signal. Adjust circuit 202 outputs a difference ("DIF") signal to sampler 207 based on the sum/difference of the output of DAC 204 and equalized signal V_θq. DAC 204 outputs an adjustable VOffset signal in response to a DOffset value input to DAC 204 from Correlator/DOffset circuit 210. Sampler circuit 207 outputs a digital Error value in response to a DIF signal and a Clock signal. Adjust circuit 203 outputs a signal to sampler 208 based on the sum/difference of the output of DAC 205 and equalized signal V_θq. DAC 205 outputs a k x VOffset signal in response to a k x DOffset value input to DAC 205 from Correlator/DOffset circuit 210. Sample circuit 208 then outputs a digital Loss Sample value to Activity Detect circuit 209 in response to a Clock signal. In embodiments, DACs 204 and 205 may output current signals or other types of signals representative of VOffset and k x VOffset instead of the actual voltages themselves. Accordingly, each of adjust circuits 202 and 203 needs not necessarily be a voltage summing circuit as shown in Fig. 2, but can be another type of circuit which produces an output signal which is effectively the scaled sum or difference of equalized signal V_θq and the VOffset or k x VOffset values provided by DACs 204 or 205.

Sampler circuits 206-208 are synchronized or phase aligned with respect to a Clock signal. In embodiments, Sampler circuits are responsive to separate clock signals. A Clock signal may be generated by a clock generation or alignment circuit, such as a phase lock loop circuit ("PLL") or delay lock loop circuit ("DLL"), in response to an external clock source or generator. In other embodiments, a Clock signal may be provided by a clock-data recovery ("CDR") circuit that derives the Clock signal from data transitions on the input signal V_m. In an embodiment, a clock source or generator may internally generate a clock signal. In embodiments, other circuit components as described herein, such as DFE circuit 211 , output signals in response to a Clock signal or sub-rate of the Clock signal.

Error and Data values are input to Correlator/DOffset circuit 210 while Data values are input to DFE circuit 211. In an embodiment, Correlator/DOffset circuit 210 is a finite state machine logic block, processor and/or associated firmware software code that adjusts the equalization coefficients COEF or tap values (multiplication factors applied to the stored current and prior data values) of DFE circuit 211 according to Error and Data values received from samplers 206 and 207. In an embodiment, Correlator/DOffset circuit 210 provides adjustments to equalization coefficients COEF in response to received Error and Data values. In an embodiment, equalization coefficients COEF or tap values are calculated/adjusted based on the Data and Error values using a "Sign-Sign Least Mean Square (¹LMS')" method that is well known to those skilled in the art.

In embodiments, DFE circuit 211 may be a signal equalizer circuit that compensates the degrading effects of transmission signal paths, by for example, adjusting a received signal that represents a bit value (or logic value) during a period of time or bit/symbol time according to current equalization coefficients and the previously received and stored data values.

In an embodiment, Correlator/DOffset circuit 210 calculates and stores k x DSwing value in a register which outputs to DAC 205 based on data and error values obtained from equalized signal V_θq. A determination may then be made as to whether equalized signals V_θq is lost (or in an LOS state) by comparing the equalized signal V_θq with the reduced k x VSwing signal. Adjust circuit 203 outputs the sum/difference of equalized signal V_θq and k x VOffset signal (k x VSwing signal) to sampler 208 that outputs Loss Sample values to Activity Detect circuit 209.

Activity Detect circuit 209 continuously monitors the Loss Sample signal. If the Loss Sample signal doesn't indicate at least one sample of an equalized signal V_θq level is greater than k x VSwing during a predetermined period of time, an LOS signal is asserted indicating that an LOS condition has occurred. An LOS signal may then be input to Correlator/DOffset circuit 210, which then disables adaptation of equalization coefficients until an LOS condition no longer exists, or an LOS signal is de-asserted (i.e. a "signal present" condition is determined).

Fig. 4 illustrates a circuit 400 including a combined receiver, LOS and equalizer circuit that adjusts equalization coefficients or detects an LOS condition in response to a control signal. Circuit 400 operates similarly to circuit 200 except that an LOS condition determination mode of operation and an equalization adaptation mode of operation (adjusting equalization coefficients) occur separately and in response to a loss of signal enable (LOS_EN) signal.

Similar to circuit 200, Sampler circuits 206 and 207 obtain Error and Data values. In particular, an equalized signal V_θq from adjust circuit 201 is sampled by Sampler circuit 206 in response to a Clock signal to provide Data values to at least Correlator/DOffset circuit 210. An equalized signal V_θq is also summed/differenced with a VOffset signal in response to a DOffset value provided by Correlator/DOffset circuit 210. A DIF output signal from adjust circuit 202 is then sampled by Sampler circuit 207 in response to a Clock signal to provide digital Error values to at least Correlator/DOffset circuit 210 and Activity Detect circuit 410.

Activity Detect circuit 410 is enabled and Correlator/DOffset circuit 210 is disabled (prevented from adjusting coefficients COEF) in response to an LOS_EN signal that may be output from a register or other control circuit. At the same time, DOffset is set to k x DSwing to set VOffset to k x VSwing. Activity Detect circuit 410, similar to Activity Detect circuit 209, monitors the Error signal, which is similar to the Loss Sample signal in Fig. 2 during this mode of operation. If the Error signal doesn't indicate at least one sample of an equalized signal V_θq is greater than k x VSwing during a predetermined period of time, an LOS signal is asserted indicating that an LOS condition has occurred. If during any predetermined period of time, the Error signal always indicates at least one sample of an equalized signal V_θq level greater than k x VSwing, then the LOS output remains unasserted, indicating that an LOS state has not been detected. LOS_EN is typically kept high as long as LOS remains asserted.

In an embodiment, LOS circuit 107 shown in Fig. 1 includes DAC 204, adjust circuit 202 and Sampler circuit 207 combined with Activity Detect circuit 410.

Fig. 5 illustrates a method 500 for calculating a DSwing value for a DOffset value used in outputting an adjustable VOffset signal during equalization coefficient initialization and adaptation. In embodiments, logic blocks illustrated in Figs. 5 and 6 represent the operation of hardware (e.g., circuits), software (e.g., machine executable instructions), or a user, singly or in combination. For example, circuits 105, 200 or 400 shown in Figs. 1 , 2 and 4, singly or in combination, with other circuits may perform the operations. Other logic blocks that are not shown may be included in various embodiments. Similarly, logic blocks that are shown may be excluded in various embodiments. In an embodiment, method 500 is performed by part of Correlator/DOffset circuit 210 shown in Figs. 2 and 4.

Method 500 begins by initializing DOffset to zero as illustrated by logic block 501 . A determination is made whether a received input signal V_m has a data value that equals 1 as illustrated by logic block 502. When a data value equals 1 , control transitions to logic block 503; otherwise the determination whether a received input signal V_n has a data value that equals 1 is repeated for additionally received input signals V_n during respective symbol times. In logic block 503, a determination is made whether the error value sampled at the same time as the data also equals 1. When the error value does not equal 1 , indicating that the signal level was less than VOffset signal level, control transitions to logic block 505 where DOffset value is decremented to reduce VOffset signal level. When the error value does equal 1 , indicating that the signal level was greater than a VOffset signal level, control transitions to logic block 504 and a DOffset value is incremented to increase a VOffset signal level. In other words, method 500 sets a DOffset value so that a corresponding adjustable VOffset signal results in the approximate same number of error values that are 0 and 1 when a data value equals 1. A determination is made whether N iterations of this procedure have occurred in 506. After N iterations have occurred, control transitions to logic block 507 that stores the final value of DOffset as DSwing value (for example, by copying the value to a register). Otherwise, control transitions to logic block 502 where the steps are repeated until N number of iterations has occurred. In some embodiments, method 500 may be repeated periodically after initialization.

Fig. 6 illustrates method 600 for determining a LOS state and equalizing an input signal V,_n. Method 600 begins as illustrated by reset logic block 601 where a reset of a circuit occurs, which may occur during initialization, calibration, periodically and/or initiated by a user. In an embodiment, a reset operation occurs in response to a control signal by a controller or other integrated circuit.

Logic block 602 represents performing an initial adaptation of a received input signal V_m to obtain initial equalization coefficient values and DOffset values, such as setting/outputting an initial DSwing value as a DOffset value, for a particular circuit or system configuration. In an embodiment, a DSwing value is obtained by method 500 illustrated in Fig. 5. In an embodiment, a plurality of predetermined patterns of values or test values are generated and received by a circuit, such as circuits 101 and 102 shown in Fig. 1. In an embodiment, the test values are a psuedo random bit sequence ("PRBS"). Based on the initialization, the DOffset value is set to the obtained DSwing value as illustrated by logic block 603.

An input signal V_m is received and equalized/adapted using the initialized DSwing value for the DOffset value. In logic block 604, at least one adaptive iteration is performed, where the equalizer coefficients COEF are updated based on observation of the Data and Error signals.

Logic block 605 illustrates then adjusting the DOffset value to a fraction k x DSwing value when the LOS circuit is enabled and equalization adaptation is disabled. For example, a DSwing value input to DAC 204 is changed to a k x DSwing value where k is a fraction as illustrated in Fig. 4.

A determination is then made whether an equalized signal V_θq is lost (below a k x VSwing signal) as illustrated by logic block 606, which may operate according to the above description of Activity Detect circuit 410. If an LOS condition is detected, control transitions to logic block 606 where equalization adaptation of the equalization coefficients remains disabled and logic block 606 repeats the LOS detection test again. If the block detects an LOS condition on N consecutive tests, the receiver is reset by returning control to block 601 in an attempt to restart communication. If an LOS detection test does not find an LOS condition, control transfers to logic block 603 where operations may be repeated including equalizing the input signal V,_n. When control transitions to logic block 603, LOS detection may be disabled until control eventually transitions to once again logic block 605.

Returning to Fig. 1 , while a single transmit and receive circuit is illustrated multiple transmit and receive circuits may be used (or in combination referred to as a transceiver) to output and receive signals on signal path 1 1 1. In embodiments, transmitter and receive circuits, singly or in combination, are dedicated to or shared with particular signal lines in signal path 1 1 1 .

In an embodiment, multiple signal paths may replace a single signal path illustrated in the figures and a single signal path may replace multiple signal paths illustrated in the figures. In embodiments, a signal path may include a bus and/or point-to-point connection. In an embodiment, a signal path includes control and data signal lines. In an alternate embodiment, a signal path includes only data signal lines or only control signal lines. In still other embodiments, signal paths are unidirectional (signals that travel in one direction) or bidirectional (signals that travel in two directions) or combinations of both unidirectional signal lines and bidirectional signal lines. In embodiments, signal paths may include different types of bus or point-to-point link architectures.

In an embodiment, an integrated circuit may be coupled to a plurality of integrated circuit memory devices that may be included in a memory module. In an embodiment, integrated circuits 101 and 102 are separately housed integrated monolithic circuits and/or combined in a single package.

Signals described herein may be transmitted or received between and within circuits by electrical conductors and generated using any number of signaling techniques including, without limitation, modulating the voltage or current level of an electrical signal. The signals may represent any type of control and timing information as well as data.

It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented) as data and/or instructions embodied in various computer- readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer- readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.). When received within a computer system via one or more computer-readable media, such data and/or instruction- based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, netlist generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

The foregoing description of the preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to understand the invention for various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

What is claimed is:

1. A circuit comprising: a receiver circuit to output a data signal in response to an equalized signal; an equalizer circuit to output an equalizer signal in response to the data signal and at least one equalization coefficient that is adjusted based on at least the data signal, the equalized signal formed in response to an input signal and the equalizer signal; and a loss-of-signal circuit to detect a loss-of-signal condition of the equalized signal, and to cause adjusting the at least one equalization coefficient to be disabled in response to a loss-of- signal condition being detected.

2. The circuit of claim 1 , wherein the equalizer circuit includes an equalization adaptation engine to adaptively adjust the at least one equalization coefficient based at least on the data signal, and to disable the adjusting of the at least one equalization coefficient in response to a loss-of-signal condition being detected by the loss-of-signal circuit.

3. The circuit of claim 1 , wherein the loss-of-signal circuit detects the loss-of-signal condition in response to an enable signal.

4. The circuit of claim 1 , wherein the equalizer circuit is a decision feedback equalizer comprising: a first adjust circuit to output the equalizer signal in response to the data signal; and a second adjust circuit to output the equalized signal in response to the input signal and the equalizer signal

5. The circuit of claim 2, further comprising: a first adjust circuit to output a difference signal in response to the equalized signal and an adjustable sampling threshold signal; and a second receiver circuit to output an error signal in response to the difference of the equalized signal and the adjustable sampling threshold signal.

6. The circuit of claim 5, wherein the equalization adaptation engine adjusts the at least one equalization coefficient in response to the data signal and the error signal.

7. The circuit of claim 6, further comprising a digital-to-analog circuit having an output to provide the adjustable sampling threshold signal to the first adjust circuit in response to an offset value provided to an input of the digital-to-analog circuit, wherein the equalization adaptation engine outputs the offset value in response to the data and error values.

8. The circuit of claim 1 , wherein the circuit is included in a serial data link system.

9. A circuit comprising: a first adjust circuit to output an equalized signal in response to a feedback signal and an input signal; a first sampler circuit to output a data signal in response to the equalized signal; a second adjust circuit to output a difference signal in response to the equalized signal and a first adjustable sampling signal; a second sampler circuit to output an error signal in response to the difference signal; an equalizer circuit to output the feedback signal in response to the data signal and at least one equalization coefficient; an adaptation circuit to adjust the at least one equalization coefficient in response to the data and error signals; and a loss-of-signal circuit to detect a loss-of-signal condition and to cause the adaptation circuit to disable the adjusting of the at least one equalization coefficient in response to the loss-of- signal condition being detected.

10. The circuit of claim 9, further comprising: a third adjust circuit to output a signal in response to the equalized signal and a second adjustable samping signal; and a third sampler to output a loss sample signal in response to the signal output from the third adjust circuit; wherein the loss-of-signal circuit responds to the loss sample signal by outputting a signal that represents a loss-of- signal when the loss sample signal indicates the equalized signal is not greater than the second adjustable sampling threshold signal during a predetermined period of time.

1 1. The circuit of claim 10, further comprising: a first digital-to-analog converter to output the first adjustable sampling signal to a first input of the second adjust circuit in response to a first offset value; and a second digital-to-analog converter to output the second adjustable sampling signal to a first input of the third adjust circuit in response to a second offset value, wherein the adaptation circuit outputs the first and second offset values to inputs of the first and second digital-to-analog converters, wherein the second offset value is a fraction of the first offset value.

12. The circuit of claim 9, wherein the loss-of-signal circuit responds to the error signal by outputting a signal that represents a loss-of-signal when the error signal indicates the equalized signal is not greater than the first adjustable sampling threshold during a predetermined period of time.

13. The circuit of claim 9, wherein the circuit operates in a first and a second mode of operation: in the first mode of operation, a first adjustable sampling signal is set according to a first value and the adaptation circuit is enabled to adjust the at least one equalization coefficients and the loss-of signal circuit is disabled to output a signal that represents a loss-of-signal, in the second mode of operation, the first adjustable sampling signal is set according to a second value and the adaptation circuit is disabled so that the at least one equalization coefficient is not adjusted and the loss-of-signal circuit is enabled to output the signal that represents the loss-of-signal.

14. The circuit of claim 13, wherein the second value is a fraction of the first value such that the second value is less than or equal to the first value.

15. A method of operating a circuit comprising: receiving an input signal; adjusting the input signal in response to a feedback signal to obtain an equalized signal; sampling the equalized signal to obtain a data signal; updating at least one equalization coefficient based at least on the data signal, the at least one equalization coefficient being used to form the feedback signal; detecting a loss-of-signal condition in one of the input signal and the equalized signal; and disabling the updating of the at least one equalization coefficient in response to the loss-of-signal condition being detected.

16. The method of claim 15, further comprising: adjusting the equalized signal with a first adjustable offset to obtain a first difference signal; and sampling the first different signal to obtain an error signal.

17. The method of claim 16, further comprising: adjusting the equalized signal with a second adjustable offset to obtain a second difference signal; and sampling the second difference signal to obtain a loss sample signal, the loss sample signal being used to detect the loss-of-signal condition in the equalized signal.

18. The method of claim 15, further comprising: repeating the detecting step in response to the loss-of- signal condition being detected, and resetting the circuit in response to the loss of signal condition being detected a predetermined number of times.

19. The method of claim 15, wherein sampling the equalized signal is performed by a sampling circuit in response to a clock signal.

20. The method of claim 15, wherein the method is a method of operating a circuit in a serial data link system.

21. A computer-readable media including executable instructions to provide information representing a circuit, the represented circuit comprising: a receiver circuit to output a data signal in response to an equalized signal; an equalizer circuit to output an equalizer signal in response to the data signal and at least one equalization coefficient that is adjusted based at least on the data signal, the equalized signal formed in response to an input signal and the equalizer signal; and a loss-of-signal circuit to detect a loss-of-signal condition in one of the equalized signal and the input signal, and to cause adjusting the at least one equalization coefficient to be disabled in response to a loss-of-signal condition being detected.

22. A receiver circuit, comprising: a receiver to output a data value in response to an equalized signal; and means for equalizing an input signal to obtain the equalized signal in response to the data value and an error value; and means for determining when the equalized signal falls below an adjustable sampling signal that is adjusted in response to the data and error values.