JP2018518757A5 - - Google Patents

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Publication number
JP2018518757A5
JP2018518757A5 JP2017560224A JP2017560224A JP2018518757A5 JP 2018518757 A5 JP2018518757 A5 JP 2018518757A5 JP 2017560224 A JP2017560224 A JP 2017560224A JP 2017560224 A JP2017560224 A JP 2017560224A JP 2018518757 A5 JP2018518757 A5 JP 2018518757A5
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JP
Japan
Prior art keywords
layout design
analysis process
design data
parameters
process parameters
Prior art date
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Application number
JP2017560224A
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English (en)
Japanese (ja)
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JP6803857B2 (ja
JP2018518757A (ja
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Publication date
Priority claimed from US14/716,775 external-priority patent/US10055533B2/en
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Publication of JP2018518757A publication Critical patent/JP2018518757A/ja
Publication of JP2018518757A5 publication Critical patent/JP2018518757A5/ja
Application granted granted Critical
Publication of JP6803857B2 publication Critical patent/JP6803857B2/ja
Active legal-status Critical Current
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JP2017560224A 2015-05-19 2016-05-19 レイアウト系検査のための解析プロセス・パラメータの視覚化 Active JP6803857B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/716,775 US10055533B2 (en) 2015-05-19 2015-05-19 Visualization of analysis process parameters for layout-based checks
US14/716,775 2015-05-19
PCT/US2016/033239 WO2016187410A1 (en) 2015-05-19 2016-05-19 Visualization of analysis process parameters for layout-based checks

Publications (3)

Publication Number Publication Date
JP2018518757A JP2018518757A (ja) 2018-07-12
JP2018518757A5 true JP2018518757A5 (enExample) 2019-06-20
JP6803857B2 JP6803857B2 (ja) 2020-12-23

Family

ID=56097313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017560224A Active JP6803857B2 (ja) 2015-05-19 2016-05-19 レイアウト系検査のための解析プロセス・パラメータの視覚化

Country Status (5)

Country Link
US (1) US10055533B2 (enExample)
EP (1) EP3298517A1 (enExample)
JP (1) JP6803857B2 (enExample)
CN (1) CN108140059B (enExample)
WO (1) WO2016187410A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10331547B1 (en) * 2017-05-23 2019-06-25 Cadence Design Systems, Inc. System, method, and computer program product for capture and reuse in a debug workspace
US10885258B1 (en) 2018-09-25 2021-01-05 Synopsys, Inc. Fixing ESD path resistance errors in circuit design layout
US11144690B2 (en) * 2018-12-19 2021-10-12 Synopsys, Inc. Extensible layer mapping for in-design verification
CN113011125B (zh) * 2019-12-18 2023-01-10 海信视像科技股份有限公司 印制电路板核查方法、装置、设备及计算机存储介质

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002189767A (ja) * 2000-12-22 2002-07-05 Mitsubishi Electric Corp インダクタ認識方法、レイアウト検査方法、レイアウト検査プログラムを記録したコンピュータ読取可能な記録媒体および半導体装置の製造方法
US6553542B2 (en) * 2000-12-29 2003-04-22 Texas Instruments Incorporated Semiconductor device extractor for electrostatic discharge and latch-up applications
US7243317B2 (en) 2003-05-30 2007-07-10 Illinios Institute Of Technology Parameter checking method for on-chip ESD protection circuit physical design layout verification
JP3819377B2 (ja) * 2003-06-18 2006-09-06 株式会社東芝 半導体集積回路の静電放電の解析方法
DE10339924B4 (de) * 2003-08-29 2011-05-05 Infineon Technologies Ag ESD-Testanordnung und Verfahren
US10643015B2 (en) * 2006-10-09 2020-05-05 Mentor Graphics Corporation Properties in electronic design automation
CN100511177C (zh) * 2006-11-06 2009-07-08 中兴通讯股份有限公司 一种嵌入式系统的符号定位方法
US7617467B2 (en) * 2006-12-14 2009-11-10 Agere Systems Inc. Electrostatic discharge device verification in an integrated circuit
EP2068259A1 (de) * 2007-12-04 2009-06-10 X-FAB Semiconductor Foundries AG Verfahren und System zur Ueberpruefung des ESD-Verhaltens von integrierten Schaltungen auf Schaltungsebene
US8079005B2 (en) 2008-09-30 2011-12-13 Cadence Design Systems, Inc. Method and system for performing pattern classification of patterns in integrated circuit designs
US20100161304A1 (en) * 2008-12-23 2010-06-24 Voldman Steven H Method of interconnect checking and verification for multiple electrostatic discharge specifications
JP2011065377A (ja) * 2009-09-16 2011-03-31 Renesas Electronics Corp 寄生素子の抽出システムと抽出方法
US8230382B2 (en) * 2010-01-28 2012-07-24 International Business Machines Corporation Model based simulation of electronic discharge and optimization methodology for design checking
US9378324B2 (en) * 2010-02-11 2016-06-28 Jesse Conrad Newcomb System and method of detecting design rule noncompliant subgraphs in circuit netlists
US8694926B2 (en) * 2012-05-30 2014-04-08 Freescale Semiconductor, Inc. Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules
CN105224708B (zh) * 2014-07-03 2019-01-18 台湾积体电路制造股份有限公司 集成电路中网路的确定方法和装置

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