JP2018511947A5 - - Google Patents

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Publication number
JP2018511947A5
JP2018511947A5 JP2017551706A JP2017551706A JP2018511947A5 JP 2018511947 A5 JP2018511947 A5 JP 2018511947A5 JP 2017551706 A JP2017551706 A JP 2017551706A JP 2017551706 A JP2017551706 A JP 2017551706A JP 2018511947 A5 JP2018511947 A5 JP 2018511947A5
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JP
Japan
Prior art keywords
electrical resistivity
length
electrical
gradient
applied energy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017551706A
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English (en)
Japanese (ja)
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JP2018511947A (ja
JP6820136B2 (ja
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Publication date
Priority claimed from US14/674,809 external-priority patent/US10390433B2/en
Application filed filed Critical
Publication of JP2018511947A publication Critical patent/JP2018511947A/ja
Publication of JP2018511947A5 publication Critical patent/JP2018511947A5/ja
Application granted granted Critical
Publication of JP6820136B2 publication Critical patent/JP6820136B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2017551706A 2015-03-31 2016-03-31 集積回路又は印刷回路基板において伝導性及び抵抗性回路構造を形成する方法 Active JP6820136B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/674,809 2015-03-31
US14/674,809 US10390433B2 (en) 2015-03-31 2015-03-31 Methods of forming conductive and resistive circuit structures in an integrated circuit or printed circuit board
PCT/US2016/025442 WO2016161212A1 (en) 2015-03-31 2016-03-31 Methods of forming conductive and resistive circuit structures in an integrated circuit or printed circuit board

Publications (3)

Publication Number Publication Date
JP2018511947A JP2018511947A (ja) 2018-04-26
JP2018511947A5 true JP2018511947A5 (https=) 2019-05-09
JP6820136B2 JP6820136B2 (ja) 2021-01-27

Family

ID=57007343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017551706A Active JP6820136B2 (ja) 2015-03-31 2016-03-31 集積回路又は印刷回路基板において伝導性及び抵抗性回路構造を形成する方法

Country Status (5)

Country Link
US (1) US10390433B2 (https=)
EP (1) EP3278359A4 (https=)
JP (1) JP6820136B2 (https=)
CN (1) CN107210263A (https=)
WO (1) WO2016161212A1 (https=)

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* Cited by examiner, † Cited by third party
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EP3520928A1 (en) * 2018-01-31 2019-08-07 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Method and apparatus for creating and sintering fine lines and patterns
US10643944B2 (en) * 2018-07-30 2020-05-05 Texas Instruments Incorporated Additively manufactured programmable resistive jumpers
US11152454B2 (en) * 2019-02-19 2021-10-19 Semiconductor Components Industries, Llc Method of forming a semiconductor device having a resistor and structure therefor
CN114142246B (zh) * 2021-11-24 2023-06-23 中国人民解放军空军工程大学 一种基于渐变阻抗的宽频大角度超材料吸波体及制备方法

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