JP2018195359A5 - - Google Patents

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JP2018195359A5
JP2018195359A5 JP2017097095A JP2017097095A JP2018195359A5 JP 2018195359 A5 JP2018195359 A5 JP 2018195359A5 JP 2017097095 A JP2017097095 A JP 2017097095A JP 2017097095 A JP2017097095 A JP 2017097095A JP 2018195359 A5 JP2018195359 A5 JP 2018195359A5
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Japan
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data
memory
memory cell
precharge
check
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JP2017097095A
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Japanese (ja)
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JP6915372B2 (ja
JP2018195359A (ja
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JP2017097095A 2017-05-16 2017-05-16 メモリセル、メモリモジュール、情報処理装置およびメモリセルのエラー訂正方法 Active JP6915372B2 (ja)

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Application Number Priority Date Filing Date Title
JP2017097095A JP6915372B2 (ja) 2017-05-16 2017-05-16 メモリセル、メモリモジュール、情報処理装置およびメモリセルのエラー訂正方法

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Application Number Priority Date Filing Date Title
JP2017097095A JP6915372B2 (ja) 2017-05-16 2017-05-16 メモリセル、メモリモジュール、情報処理装置およびメモリセルのエラー訂正方法

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JP2018195359A JP2018195359A (ja) 2018-12-06
JP2018195359A5 true JP2018195359A5 (enExample) 2021-01-14
JP6915372B2 JP6915372B2 (ja) 2021-08-04

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JP2017097095A Active JP6915372B2 (ja) 2017-05-16 2017-05-16 メモリセル、メモリモジュール、情報処理装置およびメモリセルのエラー訂正方法

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Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03138742A (ja) * 1989-10-25 1991-06-13 Toshiba Corp メモリシステム
JP3110032B2 (ja) * 1990-03-30 2000-11-20 株式会社東芝 強誘電体メモリ
JPH0773698A (ja) * 1993-08-31 1995-03-17 Mitsubishi Electric Corp マルチポートメモリ
JPH1093030A (ja) * 1996-09-17 1998-04-10 Toshiba Corp 強誘電体不揮発性メモリ
JP2001320030A (ja) * 2000-05-11 2001-11-16 Nec Corp 強誘電体メモリ及びその製造方法
US7032142B2 (en) * 2001-11-22 2006-04-18 Fujitsu Limited Memory circuit having parity cell array
JP3938298B2 (ja) * 2001-11-22 2007-06-27 富士通株式会社 パリティセルアレイを有するメモリ回路
US6809949B2 (en) * 2002-05-06 2004-10-26 Symetrix Corporation Ferroelectric memory
US6750497B2 (en) * 2002-08-22 2004-06-15 Micron Technology, Inc. High-speed transparent refresh DRAM-based memory cell
WO2011114866A1 (en) * 2010-03-17 2011-09-22 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device

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