JP2018125623A - Ad conversion device and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AD conversion device and an imaging apparatus that allow for suppression of layout size, reduction of time required for AD conversion, and avoidance of complex constitution.SOLUTION: The AD conversion device comprise: a comparison unit 31 that compares a pixel signal including a reset component and a signal component with a first reference signal and a second reference signal; an up counter 34 that counts up a counter clock; and a black level correction unit 35 that corrects a black level of a count value of the up counter 34. The up counter 34 starts counting up when the comparison unit 31 compares the reset component with the first reference signal to invert an output, and stops counting up when the comparison unit 31 compares the signal component with the second reference signal to invert the output. The black level is corrected, and at the same time, imaging data which is obtained by removing the reset component from the signal component is output by subtracting a value obtained by counting the pixel signal from a shielded pixel by the up counter 34 from the count value obtained by counting by the up counter 34.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an AD conversion apparatus and an imaging apparatus.

  Conventionally, imaging devices such as CCDs and CMOSs are used for various purposes. In general, an imaging apparatus includes an AD converter (Analog Digital Converter) for each of a plurality of pixel columns arranged in a matrix. The AD converter receives an analog electrical signal (pixel signal) representing the amount of incident light from a pixel and digitizes the pixel signal.

  Here, the pixel signal is output in a form in which the signal component is added to the reset component. For this reason, the AD converter performs correlated double sampling (CDS). CDS is a technique for extracting an effective signal component by taking a difference between a signal voltage corresponding to a reset component and a signal voltage corresponding to the signal component.

  For example, Patent Document 1 discloses an AD conversion apparatus including a ramp waveform generator, a comparator, and an up / down counter. This AD conversion device counts down when AD converting the reset component, and counts up when AD converting the signal component. The count value thus obtained is a digitized signal component from which the reset component has been removed.

  In order to realize a high speed solid-state imaging device, it is necessary to increase the clock speed and reduce the power consumption of the counter. For this reason, an AD converter using a counter using a Gray code has been proposed particularly for lower bits that require high-speed operation (see, for example, Patent Document 2). By adopting such a configuration, it is possible to cope with an increase in clock speed and to avoid simultaneous inversion of bits, which is a problem in the binary code.

JP 2008-259228 A JP 2011-234326 A

  However, since an up / down counter is required to count the reset component and the signal component, there are problems that the number of elements increases and the column layout size increases. In addition, it takes time to switch between up-counting and down-counting, and there is a problem that the time required for AD conversion becomes long.

  Further, when a gray code counter is used, it is necessary to convert each gray code of the reset component and the signal component into a binary code in order to take a difference between the reset component and the signal component in the CDS. For this reason, there exists a problem that a circuit and control become complicated.

  In view of such circumstances, an object of the present invention is to provide an AD conversion apparatus and an imaging apparatus that can suppress the layout size, reduce the time required for AD conversion, and avoid a complicated configuration.

  An aspect of the present invention that solves the above-described problem is an AD conversion apparatus that converts an analog signal including a reset component and a signal component into a digital signal, and includes a first reference signal and a second reference signal that change in signal level over time. A comparison unit that compares a reference signal and the analog signal; a supply unit that receives a clock; generates a counter clock based on the comparison result of the clock and the comparison unit; and a count unit that counts up the counter clock; And the counting unit counts up the counter clock when the comparing unit compares the first reference signal and the reset component and inverts the output, and the comparing unit counts the second reference signal. When the output is inverted by comparing the signal component with the signal component, the up-counting of the counter clock is stopped In D converter.

  In the first aspect, a count value obtained by digitizing an analog signal can be obtained. The count value becomes a digital signal composed of a true signal component from which the reset component has been removed by simply subtracting the fixed offset value obtained by counting the clocks between the first reference signal and the second reference signal. As described above, the AD conversion apparatus can obtain a count value that can obtain a digital signal composed of true signal components only by reducing the fixed offset value. Further, it can be realized only by an up counter as a counter for counting the count value. In other words, since the conventional up / down counter is not used to perform correlated double sampling, the number of elements can be greatly reduced, the layout size can be reduced, and the circuit configuration is complicated. Can be avoided. Further, in the case of using an up / down counter, a switching time for switching between the up-count and the down-count is required, but in the present invention, such a switching time is unnecessary. Therefore, faster AD conversion can be performed.

  According to a second aspect of the present invention, in the AD conversion device according to the first aspect, the counting unit is configured such that the comparison unit compares the first reference signal with the reset component and inverts the output. A counter enable signal generator for generating a counter enable signal before the comparator compares the second reference signal with the signal component and inverts the output; and inputs the counter enable signal and the clock An AD converter comprising: an AND gate that outputs the counter clock; and an up counter that counts up the counter clock output by the AND gate.

  In the second aspect, the count unit can be realized with a simple circuit configuration.

  According to a third aspect of the present invention, in the AD conversion device according to the first or second aspect, the counting unit is forced between the end of the first reference signal and the start of the second reference signal. The AD converter is characterized by starting up-counting automatically.

  In the third aspect, even if the reset component cannot be detected, a value close to the digital signal that should be output can be output.

  According to a fourth aspect of the present invention, in the AD converter according to any one of the first to third aspects, the counting unit includes a double data rate counter that up-counts rising edges of the counter clock, When the comparison unit compares the first reference signal with the reset component and inverts the output, the clock is used as it is when the clock is at a low level, and the clock is inverted when the clock is at a high level. It is in an AD converter characterized by being used.

  The fourth aspect will be described. The double data rate counter according to the present embodiment realizes the double data rate by starting counting at the rising edge of the clock and holding the high level or low level of the clock at the end to set the least significant bit. According to the fourth aspect, counting can always be started from the rising edge of the clock regardless of the state of the clock at the start of counting, so that correct AD conversion including the least significant bit can be performed.

  According to a fifth aspect of the present invention, in the AD converter according to any one of the first to third aspects, the count unit includes a double data rate counter that counts up the falling edge of the counter clock. When the comparison unit compares the first reference signal and the reset component and inverts the output, the clock is used as it is when the clock is at a high level, and the clock is used when the clock is at a low level. An AD converter characterized in that the clock is inverted and used.

  In the fifth mode, the double data rate counter of this mode starts counting at the falling edge of the clock, and realizes the double data rate by holding the high level or low level of the clock at the end and setting it as the least significant bit doing. According to the fifth aspect, counting can always be started from the falling edge of the clock regardless of the state of the clock at the start of counting, so that correct AD conversion including the least significant bit can be performed.

  According to a sixth aspect of the present invention, in the AD converter according to any one of the first to third aspects, the counting unit includes a double data rate counter that up-counts rising edges of the counter clock, If the clock is high when the comparison unit compares the first reference signal and the reset component and inverts the output, 1 is added to the count value up-counted by the double data rate counter The present invention is an AD converter characterized by

  In the sixth aspect, even when the double rate counter does not start up-counting from the rising edge of the clock, a correct count value including the least significant bit can be output.

  According to a seventh aspect of the present invention, in the AD converter according to any one of the first to third aspects, the count unit includes a double data rate counter that counts up the falling edge of the counter clock. If the clock is low when the comparison unit compares the first reference signal and the reset component and inverts the output, 1 is added to the count value up-counted by the double data rate counter The present invention is an AD converter characterized by

  In the seventh aspect, even when the double rate counter does not start up-counting from the falling edge of the clock, a correct count value including the least significant bit can be output.

  According to an eighth aspect of the present invention, in the AD converter according to any one of the first to seventh aspects, a difference obtained by subtracting a predetermined value from the count value counted by the counting unit is output as a digital signal. A subtracting unit, and the subtracting unit subtracts an offset value obtained by counting the clock supplied between the start of the first reference signal and the start of the second reference signal as the predetermined value from the count value. The AD converter is characterized in that the difference is output as a digital signal.

  In the eighth aspect, it is possible to output a digital signal (imaging data) including a true signal component obtained by performing correlated double sampling from a pixel signal.

  A ninth aspect of the present invention includes the AD converter according to the eighth aspect and a unit pixel that outputs an analog signal including a reset component and a signal component from incident light by a photoelectric conversion element, and the analog signal Is converted into a digital signal by the AD converter and the imaging data is output.

  In the ninth aspect, an analog pixel signal obtained from a unit pixel is digitized by an AD converter, and imaging data can be obtained. The AD converter performs correlated double sampling in order to digitize an analog signal, and can be realized by using only an up counter as a counter used at this time. In other words, since the conventional up / down counter is not used to perform correlated double sampling, the number of elements can be greatly reduced, the size of the layout of the imaging device can be reduced, and the circuit configuration can be reduced. Can be prevented from becoming complicated. Further, in the case of using an up / down counter, a switching time for switching between the up-count and the down-count is required, but in the present invention, such a switching time is unnecessary. Therefore, the imaging apparatus can perform faster AD conversion and output a digital signal (imaging data) at a higher speed.

  A tenth aspect of the present invention is a unit pixel that outputs an analog signal including a reset component and a signal component from incident light by the photoelectric conversion element and the AD conversion device according to any one of the first to seventh aspects. The light-shielded pixel that is the light-shielded unit pixel, the count value obtained from the AD converter that receives an analog signal from the unit pixel, and the analog signal from the light-shielded pixel as input. A signal processing unit that outputs a difference from the count value obtained from the AD converter as imaging data.

  In the tenth aspect, as a means for subtracting the offset value from the count value, the offset value can be automatically reduced only by performing black level correction. Thereby, it is possible to obtain a digital signal (imaging data) composed of a true signal component in which the analog signal is black level corrected and the offset value is reduced. Thus, in the imaging apparatus of this aspect, it is not necessary to prepare a subtracting circuit for subtracting the offset value from the count value. Thereby, it is possible to avoid further complicating the circuit structure.

  According to the present invention, an AD conversion device and an imaging device that can suppress the layout size, reduce the time required for AD conversion, and avoid a complicated configuration are provided.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment. 1 is a block diagram of an AD conversion apparatus according to a first embodiment. 3 is a timing chart of the AD conversion apparatus according to the first embodiment. 6 is a block diagram of an AD conversion apparatus according to Embodiment 2. FIG. 6 is a timing chart of the AD conversion apparatus according to the second embodiment. FIG. 6 is a block diagram of an AD conversion apparatus according to a third embodiment. 10 is a timing chart of the AD conversion apparatus according to the third embodiment. FIG. 10 is a block diagram of an AD conversion apparatus according to a fourth embodiment.

<Embodiment 1>
FIG. 1 is a block diagram illustrating a configuration of an imaging apparatus according to the present embodiment. The imaging device of this embodiment is a CMOS image sensor with a column-parallel ADC.

  The imaging device 10 includes a pixel array unit 12, a row scanning circuit 13, a column processing unit 14, a reference voltage supply unit 15, a column in which a large number of unit pixels 11 including photoelectric conversion elements are two-dimensionally arranged in a matrix (matrix shape). A scanning circuit 16, a horizontal output line 17, a timing control circuit 18, and a signal processing unit 19 are provided.

  Based on the master clock MCLK, the timing control circuit 18 generates a clock signal, a control signal, and the like that serve as a reference for operations of the row scanning circuit 13, the column processing unit 14, the reference voltage supply unit 15, the column scanning circuit 16, and the like. , To the row scanning circuit 13, the column processing unit 14, the reference voltage supply unit 15, the column scanning circuit 16, and the like.

  Peripheral driving systems and signal processing systems that drive and control each unit pixel 11 of the pixel array unit 12, that is, a row scanning circuit 13, a column processing unit 14, a reference voltage supply unit 15, a column scanning circuit 16, a horizontal output line 17, and The timing control circuit 18 and the like are integrated on the same chip (semiconductor substrate) as the pixel array unit 12.

  Although not shown here as the unit pixel 11, in addition to a photoelectric conversion element (for example, a photodiode), for example, an electric charge obtained by photoelectrically converting incident light with the photoelectric conversion element is FD (floating diffusion). A three-transistor configuration having a transfer transistor for transferring to a portion, a reset transistor for controlling the potential of the FD portion, and an amplifying transistor for outputting a signal corresponding to the potential of the FD portion, and further for performing pixel selection A four-transistor structure having a separate selection transistor can be used. Here, the analog signal output from the unit pixel 11 is referred to as a pixel signal.

  In the pixel array unit 12, the unit pixels 11 are two-dimensionally arranged for m rows and n columns, and row control lines 21 (21-1 to 21-m) are arranged for each row with respect to the pixel arrangement of m rows and n columns. ), And column signal lines 22 (22-1 to 22-n) are wired for each column. Each one end of the row control lines 21-1 to 21 -m is connected to each output end corresponding to each row of the row scanning circuit 13. The row scanning circuit 13 is configured by a shift register or the like, and controls the row address and row scanning of the pixel array unit 12 via the row control lines 21-1 to 21-m.

  The column processing unit 14 includes, for example, AD converters (hereinafter referred to as ADC) 30-1 to 30-n provided for each pixel column of the pixel array unit 12, that is, for each of the column signal lines 22-1 to 22-n. Then, the pixel signal output for each column from each unit pixel 11 of the pixel array unit 12 is converted into a digital signal and output. The ADCs 30-1 to 30-n for the column signal lines 22-1 to 22-n are also collectively referred to as ADC30. Details of the ADC 30 will be described later.

  The reference voltage supply unit 15 generates a reference voltage having a so-called ramp (RAMP) waveform in which the signal level changes in an inclined manner as time elapses. Specifically, the reference voltage supply unit 15 uses a DAC (digital-analog conversion circuit). Generate a reference voltage. The means for generating the RAMP waveform reference voltage is not limited to the DAC.

  The reference voltage supply unit 15 generates a RAMP waveform reference voltage based on the clock CLK supplied from the timing control circuit 18 according to the control signal supplied from the timing control circuit 18, and the ADCs 30-1 to 30-of the column processing unit 14. n.

  The column scanning circuit 16 is configured by a shift register or the like, and controls column addresses and column scanning of the ADCs 30-1 to 30-n in the column processing unit 14. Under the control of the column scanning circuit 16, N-bit digital signals AD-converted by the ADCs 30-1 to 30-n are sequentially output via the horizontal output line 17. The horizontal output line 17 is composed of N-bit signal lines.

  In addition, the imaging apparatus 10 includes a pixel called a so-called optical black (OB) (hereinafter referred to as a light-shielded pixel 11D) as a configuration for correcting the black level variation due to the influence of dark current. The configuration of the light-shielding pixel 11D is the same as that of the unit pixel 11, but is in a state of being shielded from light. The light shielding pixel 11D is connected to the ADC 30D, and the analog signal output from the light shielding pixel 11D is converted into a digital signal by the ADC 30D. The configuration of the ADC 30D is the same as that of the ADC 30 described above.

  The signal processor 19 corrects the black level by taking the difference between the pixel signal obtained from the unit pixel 11 that is not shielded from light and the pixel signal obtained from the shielded pixel 11D that is shielded from light. Although details will be described later, the signal processing unit 19 receives a digital signal obtained from the ADC 30 and a digital signal obtained from the ADC 30D, and outputs a difference between these as imaging data. The signal processing unit 19 may perform not only such black level correction but also various image processing functions such as digital signal buffering, variation correction, and color tone correction. Further, the signal processing unit 19 may convert N-bit parallel imaging data into serial imaging data and output the serial imaging data to a device outside the imaging device 10.

  FIG. 2 is a block diagram of the ADC. The ADCs 30-1 to 30-n and the ADC 30D all have the same configuration, and here, the ADC 30-n will be described.

  The ADC 30-n includes a comparison unit 31, a CE generation circuit 32, an AND gate 33, and an up counter 34. The CE generation circuit 32, the AND gate 33, and the up counter 34 are an example of a counting unit described in the claims.

  The comparison unit 31 includes a potential VSL of the column signal line 22-n corresponding to a signal output from each unit pixel 11 in the n-th column of the pixel array unit 12, and a reference voltage potential supplied from the reference voltage supply unit 15. Compare with RAMP. For example, when the potential RAMP is higher than the potential VSL, the output (Comp.out) becomes low level, and when the potential RAMP is equal to or lower than the potential VSL, the output (Comp.out) becomes high level.

  The CE generation circuit 32 detects only the rising edge of the output of the comparison unit 31 and inverts the value held each time. For example, when the CE generation circuit 32 is reset, the low level is held. Next, when the rising edge of the output of the comparison unit 31 is detected, the high level is held. Next, when the rising edge of the output of the comparison unit 31 is detected, the low level is held. As described above, the comparison unit 31 compares the first reference signal with the reset component and inverts the output until the comparison unit 31 compares the second reference signal with the signal component and inverts the output. A signal output to the counter is referred to as a counter enable signal and is hereinafter abbreviated as a CE (Counter Enable) signal. The CE signal is input to the AND gate 33.

  The AND gate 33 outputs a logical product of the CE signal and the clock CLK supplied from the timing control circuit 18. The output of the AND gate 33 is referred to as a counter clock (Counter CLK).

  The up counter 34 is an asynchronous counter, which receives a counter clock from the AND gate 33 and performs up counting in synchronization with the counter clock. Here, the up counter 34 performs an up count using a binary code. The value counted by the up counter 34 of the ADC 30 is referred to as a count value. Note that the up-counter 34 is not limited to an up-count using a binary code, and may perform an up-count using a gray code.

  The operation of the imaging apparatus 10 having the above-described configuration will be described using the timing chart of FIG. In the figure, RAMP is represented by a one-dot chain line, and the others are represented by a solid line.

  VSL represents the potential of the signal output from the unit pixel 11, and RAMP represents the reference voltage of the RAMP waveform output from the reference voltage supply unit 15. CLK represents the clock CLK supplied from the timing control circuit 18. Comp. “out” represents the output of the comparison unit 31, “CE” represents the CE signal of the CE generation circuit 32, and “Counter CLK” represents the counter clock output from the AND gate 33.

  Although a description of a specific operation of the unit pixel 11 is omitted, as is well known, the unit pixel 11 performs a reset operation and a transfer operation. In the reset operation, the potential of the FD portion when reset to a predetermined potential is output from the unit pixel 11 to the column signal lines 22-1 to 22-n as a reset component. In the transfer operation, the potential of the FD portion when the photoelectric conversion charge is transferred from the photoelectric conversion element is output as a signal component from the unit pixel 11 to the column signal lines 22-1 to 22-n. In the figure, Vr is the potential of the reset component, and Vs is the potential of the signal component including the reset component.

The RAMP waveform includes a first reference signal V _ref1 and a second reference signal V _ref2 . The signal level of the first reference signal V _ref1 gradually decreases from the reference potential V ₀ with the lapse of time from t ₀ to t ₂ , and the second reference signal V _ref2 is lapsed from the time of t ₃ to t _5. the signal level from the accompanying reference potential V ₀ which is gradually decreased. The first reference signal V _ref1 is compared with the reset component and compared with the second reference signal V _ref2 .

In the present embodiment, the clock CLK is generated only when the first reference signal V _ref1 and the second reference signal V _ref2 are generated.

  A row i is selected by row scanning by the row scanning circuit 13, and pixel signals are read from the unit pixels 11 of the selected row i to the column signal lines 22-1 to 22-n and input to the comparison unit 31.

Next, the pixel signal composed of the reset component supplied from the unit pixel 11 is digitized. Specifically, the reference voltage supply unit 15 starts supplying the first reference signal V _ref1 to the comparison unit 31 (time t ₀ ). Further, the clock CLK is supplied while the first reference signal V _ref1 is supplied (time t _{0 to} t ₂ ).

With time, the first reference signal _{V ref1} is the signal level decreases, the potential VSL of the column signal line 22-n, intersect at a potential Vr at time _{t 1,} the time _t 1 ~t ₂ In the reset component potential The potential becomes lower than Vr.

When the first reference signal V _ref1 falls below the reset component potential Vr, the output of the comparison unit 31 is inverted from the low level to the high level (time t ₁ ). The CE generation circuit 32 detects a rising edge of the output of the comparison unit 31, holds a high level, and outputs a high level CE signal. The AND gate 33 outputs the clock CLK as a counter clock while the CE signal is at a high level. That, the AND gate 33, from the time _{t 1} when the potential Vr of the first reference signal _{V ref1} and the reset component is equal, over until time _{t 2} when _the first reference signal _{V ref1} is completed, it outputs a counter clock To do.

The up counter 34 counts up while the counter clock is input from the AND gate 33 (time t _{1 to} t ₂ ). Here, it is assumed that the count value at this time is counted from “0” to “C ₁ ” (positive integer).

Next, the pixel signal composed of the reset component and the signal component supplied from the unit pixel 11 is digitized. Specifically, the reference voltage supply unit 15 starts supplying the second reference signal V _ref2 to the comparison unit 31 (time t ₃ ).

Further, the clock CLK is supplied while the second reference signal V _ref2 is supplied (time t _{3 to} t ₅ ). As described above, the CE generation circuit 32 is configured to detect only the rising edge of the signal output from the comparison unit 31. When the reset component is detected, the CE generation circuit 32 maintains the high level as a result of detecting the rising edge of the signal output from the comparison unit 31.

Since such a high-level CE signal and the clock CLK are input, the AND gate 33 outputs a counter clock from the start of supply of the second reference signal V _ref2 (time t ₃ ).

With the elapse of time, the second reference signal _{V ref2} is the signal level decreases, the potential VSL of the column signal line 22-n, intersects the potential Vs at time _{t 4,} than the time _t 4 in ~t ₅ potential Vs The potential is lowered.

When the second reference signal V _ref2 falls below the potential Vs of the signal component including the reset component, the output of the comparison unit 31 is inverted from the low level to the high level (time t ₄ ). The CE generation circuit 32 detects the rising edge of the output of the comparison unit 31, inverts the high level held so far, and holds the low level. Since the CE signal becomes low level, the AND gate 33 does not output the clock CLK as a counter clock.

In this way, from the time _{t 3} when started second reference signal _{V ref2,} over until time _{t 4} when the potential Vs of the signal component comprising a second reference signal _{V ref2} and reset components are equal, the AND A counter clock is output from the gate 33.

The up counter 34 counts up while the counter clock is input from the AND gate 33 (time t _{3 to} t ₄ ). This up-counting is continued from the value previously counted at time t _{1 to} t ₂ . The final count value counted at time t ₄ when the stop is "C" (a positive integer).

The value counted by the up counter 34 between time t ₃ and time t ₄ is “C ₂ ” (a positive integer). Accordingly, as shown in Equation 1, the count value C is the sum of the count value C ₁ and the count value C _2.
(Formula 1) C = C ₁ + C ₂

The counting unit including the CE generation circuit 32, the AND gate 33, and the up counter 34 generates a counter clock based on the clock CLK and the comparison result in the comparison unit 31, and the up counter 34 increases the counter clock. Count. Specifically, when the comparison unit 31 compares the first reference signal V _ref1 with the potential Vr representing the reset component and inverts the output (time t ₁ ), the up counter 34 counts up the counter clock. ing. In the counting unit, when the comparison unit 31 compares the second reference signal V _ref2 with the potential Vs representing the signal component including the reset component and inverts the output (time t ₄ ), the up counter 34 Counter clock up-count is stopped.

By subtracting a predetermined value from the count value C output by the up counter 34, a true signal component obtained by removing the reset component from the pixel signal obtained from the unit pixel 11 can be obtained. The predetermined value is an offset value (in the figure, the clock CLK supplied from the start of the first reference signal V _ref1 (time t ₀ ) to the start of the second reference signal V _ref2 (time t ₃ )). It is expressed as Offset).

  First, it will be described that a signal component is obtained by subtracting the offset value from the count value C.

Here, it is assumed that the counter clock is generated from the start of supply of the first reference signal V _ref1 (time t ₀ ) until the first reference signal V _ref1 crosses the potential Vr (time t ₁ ). In the meantime, a value obtained by counting the counter clock by the up counter 34 is defined as C ₀ .

The offset value is a value obtained by counting the clock CLK supplied between the start of the first reference signal V _ref1 (time t ₀ ) and the start of the second reference signal V _ref2 (time t ₃ ). In the present embodiment, since the clock CLK is generated only while the first reference signal V _ref1 is generated (time t _{0 to} t ₂ ), the clock CLK is generated from time t ₀ to time t ₂ . A value obtained by counting the clock CLK is an offset value.

Therefore, as shown in Expression 2, the offset value is equal to the sum of the count value C ₁ counted by the up counter 34 and the virtually assumed count value C ₀ .
(Formula 2) Offset = C ₀ + C ₁

From (Equation 1) and (Equation 2), the difference obtained by subtracting the offset value from the count value C, as shown in Equation 3, the count value C _2, equal to the difference between the count value C _0.
(Equation _{3) C-Offset = C 2} -C 0

The count value C ₀ is a value counted until the signal level of the RAMP waveform decreases from the reference potential V ₀ to the reset component potential Vr, that is, a value obtained by digitizing the reset component.

Count value C ₂ is counted value between the reference potential V ₀ which is RAMP waveform until the signal level falls to the potential Vs of the signal components including a reset component, i.e., digitized signal components including the reset component Value.

Count value obtained by subtracting the count value C ₀ C ₂ to is a value obtained by digitizing a real signal component (imaging data). Therefore, the difference obtained by subtracting the offset value from the count value C output from the up counter 34 is a value obtained by digitizing the true signal component obtained by performing the correlated double sampling.

The offset value is a fixed value because it is obtained by counting the clock CLK generated at the time when the first reference signal _Vref1 is generated. Therefore, a counter for counting the offset value is not necessary. If the time length of the first reference signal V _ref1 is determined, the offset value can be fixedly determined. The offset value is a value common to all ADCs 30.

  By providing a subtracting circuit (corresponding to a subtracting unit in claims) for subtracting the offset value from the count value C obtained by the up counter 34, it is possible to obtain imaging data obtained by digitizing a true signal component. However, by executing the black level correction described below, it is possible to obtain imaging data based on the count value C without specially providing a subtracting circuit. Such processing is performed by the signal processing unit 19.

  The signal processing unit 19 includes a circuit for removing the influence of dark current, which is performed by a general imaging device. Specifically, the signal processing unit 19 receives the count value C from the up counter 34 via the horizontal output line 17. The signal processing unit 19 also receives a count value (hereinafter referred to as dark current count value D) from the ADC 30D that digitizes the pixel signal from the light-shielding pixel 11D. The signal processing unit 19 outputs the difference between the count value C and the dark current count value D as imaging data.

If the true signal component obtained by subtracting the offset value from the count value C is defined as Signal, Expression 3 can be expressed as Expression 4. Here, since the dark signal component is included in the true signal component when the black level is not corrected, when the dark current component is DC (Dark Current), it can be expressed as shown in Equation 5. The dark current count value D can also be expressed as in Equation 6 in the same manner as in Equation 5.
(Equation _{4) C-Offset = C 2} -C 0 = Signal
(Formula 5) C = Signal + DC + Offset
(Formula 6) D = 0 + DC + Offset

Since the dark current count value D is based on the analog signal of the light shielding pixel 11D, the signal component is zero and includes the dark current component DC and an offset value. In other words, the value obtained by subtracting the offset value from the dark current count value D represents the black level signal of only the dark current. Since the offset value is common to all the ADCs 30, when Expression 6 is subtracted from Expression 5, as shown in Expression 7, a digital signal (imaging data) representing a dark signal component and a true signal component from which the offset value has been removed. )
(Formula 7) CD = Signal

  As described above, the signal processing unit 19 obtains a difference between the count value C of the unit pixel 11 that is not shielded from light and the dark current count value D of the shielded pixel 11D that is shielded from light. As a result, the dark current component DC can be removed and the black level can be corrected, and at the same time, the offset value is reduced and the imaging data consisting of the true signal component is output in the same manner as when the correlated double sampling is performed. be able to.

  After a series of CDS and AD conversion is performed in the ADC 30, the N-bit digital signal is held in the up counter 34. The N-bit digital signals AD-converted by the ADCs 30-1 to 30-n of the column processing unit 14 are sequentially scanned by the column scanning circuit 16 through the N-bit width horizontal output line 17 and sequentially signal processing units. 19 is output. The signal processing unit 19 performs black level correction and offset value subtraction, and outputs image data. Thereafter, the same operation is sequentially repeated for each row to generate a two-dimensional image.

  The ADC 30 (AD converter) described above digitizes an analog pixel signal from the unit pixels 11 arranged in a matrix and holds it as a count value in the up counter 34. As described above, the count value becomes a digital signal (imaging data) including a true signal component only by reducing the fixed offset value. As described above, the ADC 30 according to the present embodiment can output a count value that can obtain a digital signal including a true signal component only by reducing a fixed offset value. A configuration for obtaining such a count value is realized by the up counter 34. That is, since the conventional up / down counter is not used to perform correlated double sampling, the number of elements can be greatly reduced, and the layout size of the ADC 30 and the imaging device 10 can be reduced.

In addition, when an up / down counter is used, a switching time for switching between an up count and a down count is required. In FIG. 3, a switching time is required between the first reference signal V _ref1 and the second reference signal V _ref2 (from time t ₂ to t _{3 in} FIG. ₃ ). However, in the ADC 30 of this embodiment, such a switching time is unnecessary. Therefore, higher-speed AD conversion can be performed, and a 1 / f noise reduction effect can be expected.

  In this embodiment, the up-counter 34 using a binary code has been described as an example, but a gray-code up-counter can also be used. Even when a gray code up counter is used, a memory for holding a reset signal for CDS is not required.

  As described above, even if the gray code up-counter is used, the memory for CDS and the circuit for converting the gray code to the binary code for CDS become unnecessary, and the circuit and control are not complicated. By using a gray code up-counter, it is possible to realize a high-speed clock and low power consumption, and to avoid simultaneous inversion of bits, which is a problem in the binary code.

  Furthermore, the imaging apparatus 10 including the ADC 30 of the present embodiment uses the signal processing unit 19 that performs black level correction as a configuration for subtracting the offset value from the count value obtained by the ADC 30. By providing such a signal processing unit 19, it is possible to perform black level correction, perform correlated double sampling, remove reset components included in pixel signals, and obtain imaging data consisting of true signal components. it can. The signal processing unit 19 that performs black level correction is generally provided in a conventional imaging apparatus. Since the imaging data from which the reset component is removed can be obtained simply by applying such a signal processing unit 19, it is not necessary to prepare a subtracting circuit for subtracting the offset value from the count value obtained by the ADC 30. Thereby, it is possible to avoid further complicating the circuit structure.

<Embodiment 2>
In the present embodiment, the ADC 30 corresponding to the case where the reset component cannot be detected will be described. 4 is a block diagram of the ADC, and FIG. 5 is a timing chart of the ADC. In addition, the same code | symbol is attached | subjected to the same thing as Embodiment 1, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 4, the CE generation circuit 32A of the ADC 30 of this embodiment is provided with a function for forcibly outputting a high-level CE signal. The operation of the CE generation circuit 32A is the same as that of the CE generation circuit 32 of the first embodiment when the forced count start signal (indicated as “Forced Counter Start” in the figure) is at a low level. When the forced count start signal is at a high level, a high level is output as a CE signal regardless of the input.

A high-level forced count start signal is supplied to the CE generation circuit 32A at an arbitrary timing after the first reference signal V _ref1 ends and until the second reference signal V _ref2 starts. .

The operation of the ADC 30 of this embodiment will be described with reference to FIG.
As the time elapses, the signal level of the first reference signal V _ref1 decreases, but may not intersect with the potential VSL of the column signal line 22-n. For example, when strong light is incident on the unit pixel 11, the potential VSL is lower as the signal amount of the pixel signal is larger. Therefore, the potential VSL may be at a low level that does not intersect the first reference signal V _ref1 .

In such a case, the CE signal output from the CE generation circuit 32A remains at a low level. Therefore, in the first reference signal V _ref1 (time t _{0 to} t ₂ ), the counter clock is not output from the AND gate 33 and the up counter 34 does not start up counting.

Next, during the period from the end of the first reference signal V _ref1 to the start of the second reference signal V _ref2 (time t _{2 to} t ₃ ), a high-level forced count start signal is given to the CE generation circuit 32A. Thus, CE generating circuit 32A until it detects a rising edge of the output from the next comparator unit 31 (until the time t _4), holds the high level. The AND gate 33 outputs a counter clock during the second reference signal V _ref2 (time t _{3 to} t ₄ ), and the up counter 34 performs up counting. Thereafter, as in the first embodiment, the imaging data is obtained by subtracting the dark current count value D from the count value C up-counted by the up-counter 34.

  If the CE generation circuit 32A is not provided with a preset function, the CE signal output from the CE generation circuit 32A remains at a low level, so that the counter clock is not output from the AND gate 33. As a result, the count value C of the up counter 34 becomes zero and is output as black image data. That is, although it is actually quite bright, it is output as black image data.

  However, according to the ADC 30 of the present embodiment, by providing the CE generation circuit 32A with a function of forcibly counting the up counter 34, it is possible to output data that is close to the imaging data that should be output instead of black. Can do.

<Embodiment 3>
In the present embodiment, an ADC 30 that uses a double data rate (DDR) counter as an up counter will be described. FIG. 6 is a block diagram of the ADC, and FIG. 7 is a timing chart of the ADC 30. In addition, the same code | symbol is attached | subjected to the same thing as Embodiment 1, and the overlapping description is abbreviate | omitted.

As shown in FIG. 6, in the ADC 30 of this embodiment, when the comparison unit 31 compares the first reference signal _Vref1 with the reset component and inverts the output, if the clock is at a low level, the clock is left as it is. If the clock is high level, the clock is inverted and used.

  As a specific configuration for performing such clock inversion, the ADC 30 includes a DDR counter 34A as an up counter, a comparison unit 31 (not shown), a CE generation circuit 32 (not shown), and clock / clock bar generation. A circuit 37 (in the figure, a CLK or CLKB generation circuit), a latch circuit 38, and a delay circuit 39 are provided.

  When the clock / clock bar generation circuit 37 detects the rising edge of the CE signal, the clock / clock bar generation circuit 37 outputs the clock as it is when the clock is at the high level, and the clock bar (CLKB) obtained by inverting the clock when the clock is at the low level. It is a circuit to output.

  The output of the clock / clock bar generation circuit 37 is input to and held in the latch circuit 38. The delay circuit 39 is used to hold the output of the clock / clock bar generation circuit 37 by the latch circuit 38.

The operation of the ADC 30 of this embodiment will be described with reference to FIG. In the figure, CLK indicates the clock CLK, and CLKB indicates a clock bar obtained by inverting the clock CLK. Further, time t ₁ indicates the time when the reset component is detected (when the first reference signal V _ref1 crosses the potential Vr), similarly to that shown in the first embodiment (FIG. 3). Time t ₄ shows when detecting a signal component including a reset component (when the second reference signal V _ref2 crosses the potential Vs).

First, a case where the clock CLK is at a low level when the rising edge of the CE signal is detected by the clock / clock bar generation circuit 37 (time t ₁ ) will be described. At this time, the clock / clock bar generation circuit 37 outputs the clock CLK as it is. Therefore, when the DDR counter 34A starts counting the counter clock, it starts at the rising edge of the counter clock.

On the other hand, the case where the clock CLK is at the high level when the rising edge of the CE signal is detected by the clock / clock bar generation circuit 37 (time t ₁ ) will be described. At this time, the clock / clock bar generation circuit 37 outputs CLKB obtained by inverting the clock CLK. Since the clock CLK is inverted in this way, the counter clock supplied to the DDR counter 34A becomes the clock bar CLKB, and when the counter clock starts counting, it starts at the rising edge (t _a ) of the counter clock.

If the clock / clock bar generation circuit 37 does not invert the clock CLK, the DDR counter 34A counts up CLK instead of CLKB. If a DDR counter 34A that counts the rising edge of the counter clock, until the rising of the next counter clock (from time t ₁ to tb), must wait, delayed more than a half cycle.

  However, in the ADC 30 of this embodiment, if the clock CLK when the rising edge of the CE signal is detected is inverted, it is inverted. As a result, the DDR counter 34A can always start counting up from the rising edge of the counter clock. That is, it is possible to avoid waiting until the next counter clock rises as described above. Further, since the counter clock is up-counted by the DDR counter 34A, the frequency of the counter can be doubled, and AD conversion by the ADC 30 can be speeded up.

When a DDR counter that counts the falling edge of the clock is used, the following configuration is used. When the rising edge of the CE signal is detected by the clock / clock bar generation circuit 37 (time t ₁ ), when the clock CLK is at a high level, the clock / clock bar generation circuit 37 outputs the clock CLK as it is. On the other hand, when the rising edge of the CE signal is detected by the clock / clock bar generation circuit 37 (time t ₁ ), when the clock CLK is at the low level, the clock / clock bar generation circuit 37 inverts the clock CLK to Bar CLKB is output. Since the clock CLK is inverted in this way, the counter clock supplied to the DDR counter becomes the clock bar CLKB, and when the counter clock starts counting, it starts at the falling edge of the counter clock. Thus, the DDR counter can always start up counting from the falling edge of the clock. That is, it is possible to avoid waiting until the next clock fall.

<Embodiment 4>
In the present embodiment, an ADC 30 that uses a double data rate (DDR) counter as an up counter will be described. FIG. 8 is a block diagram of the ADC. In addition, the same code | symbol is attached | subjected to the same thing as Embodiment 3, and the overlapping description is abbreviate | omitted.

As shown in FIG. 8, the ADC 30 of this embodiment has a DDR counter if the clock is high when the comparison unit 31 compares the first reference signal V _ref1 with the reset component and inverts the output. 1 is added to the count value up-counted by 34A.

  As a specific configuration for realizing such processing, the ADC 30 includes a DDR counter 34A as an up counter, a comparison unit 31 (not shown), a CE generation circuit 32 (not shown), and a clock level detection circuit 40 ( In the figure, a CLK H or L detection circuit), a latch circuit 41, and an adder 42 are provided.

  The clock level detection circuit 40 holds the signal level of the clock CLK when the rising edge of the CE signal that is the output of the CE generation circuit 32 described in the first embodiment is detected.

  The latch circuit 41 outputs the clock CLK as a counter clock when the CE signal, which is the output of the CE generation circuit 32 described in the first embodiment, is at a high level, and holds the clock CLK at that time when the CE signal is at a low level. . The output of the latch circuit 41 is input to the DDR counter 34A and counted up.

  If the output of the clock level detection circuit 40 is at a high level, the adder 42 adds 1 to the count value up-counted by the DDR counter 34A and outputs the result, and the output of the clock level detection circuit 40 is at a low level. Then, the count value up-counted by the DDR counter 34A is output as it is.

As described in Embodiment 3, when the clock CLK is at the high level when it detects a rising edge of the CE signal, DDR counter 34A until the next rise of the counter clock (from time t ₁ to tb), standby Must. In this case, since the DDR counter 34A cannot count the counter clock during standby, the count value to be finally output is one less than the correct count value.

  The ADC 30 of this embodiment adds 1 to the count value output by the DDR counter 34A when the clock CLK is at the high level when the rising edge of the CE signal is detected, so that the correct count value can be output. it can.

  When a DDR counter that counts the falling edge of the clock is used, the adder 42 adds 1 to the count value up-counted by the DDR counter and outputs it when the output of the clock level detection circuit 40 is at a low level. To do.

  If the clock CLK is at a low level when the rising edge of the CE signal is detected, the DDR counter must wait until the next falling clock. In this case, since the DDR counter cannot count the clock while waiting, the count value to be finally output is one less than the correct count value. The ADC 30 of this embodiment adds 1 to the count value output by the DDR counter when the clock CLK is at the low level when the rising edge of the CE signal is detected, so that the correct count value can be output.

<Other embodiments>
As mentioned above, although each embodiment of this invention was described, the fundamental structure of this invention is not limited to what was mentioned above.

  In the first to fourth embodiments, the signal processing unit 19 is used as means for subtracting the offset from the count value counted by the ADC 30, but the present invention is not limited to this. For example, each ADC 30 may be provided with a subtracting circuit for subtracting the offset value from the count value up-counted by the up counter 34. As described above, the ADC 30 including the subtracting circuit can output a digital signal (imaging data) including a true signal component obtained by performing correlated double sampling from the pixel signal.

In the first to fourth embodiments, the offset value is obtained by counting the clock CLK only when the first reference signal V _ref1 is generated. However, the present invention is not limited to this. The offset value may be obtained by counting the clock CLK supplied from the start of the first reference signal _{Vref1 to} the start of the second reference signal _Vref2 . In the example of FIG. 3, the clock CLK may be generated also at times t ₂ to t ₃ . Even in this case, imaging data obtained by digitizing the true signal component from which the reset component is removed is obtained by subtracting the offset value from the count value up-counted by the up-counter 34 (or DDR counter 34A). be able to. Further, the first reference signal and the second reference signal are not limited to those exemplified in the first to fourth embodiments. It is only necessary that the waveform has a signal level that changes with time.

  In the first to fourth embodiments, the ADC 30 is used to process the pixel signal of the imaging device, but is not limited to such an application. As long as the analog signal includes a reset component and a signal component, the AD converter of the present invention can be applied. For example, in addition to the light described in the above embodiment, the AD converter of the present invention can also be applied when an analog signal is converted into a digital signal from an element that converts an electromagnetic wave such as radiation into an electrical signal.

DESCRIPTION OF SYMBOLS 10 ... Imaging device, 11 ... Unit pixel, 11D ... Light-shielding pixel, 19 ... Signal processing part, 31 ... Comparison part, 32, 32A ... CE production | generation circuit, 33 ... AND gate, 34 ... Up counter, 34A ... DDR counter, 37 ... Clock / clock bar generation circuit, 38, 41 ... Latch circuit, 39 ... Delay circuit, 40 ... Clock level detection circuit, 42 ... Adder

According to a tenth aspect of the present invention, the AD converter according to the sixth or seventh aspect, a unit pixel that outputs an analog signal including a reset component and a signal component from incident light by a photoelectric conversion element, and light shielding are provided. From the light-shielding pixel that is the unit pixel, the count value obtained from the AD converter that receives an analog signal from the unit pixel, and the AD converter that receives an analog signal from the light-shielded pixel And a signal processing unit that outputs the difference from the obtained count value as imaging data.

Claims (10)

An AD converter for converting an analog signal including a reset component and a signal component into a digital signal,
A comparison unit that compares the analog signal with the first reference signal and the second reference signal whose signal levels change over time;
Receiving a clock, generating a counter clock based on the comparison result of the clock and the comparison unit, and a count unit for counting up the counter clock, and
The counting unit is
When the comparison unit compares the first reference signal and the reset component and inverts the output, the counter clock is up-counted,
The AD conversion apparatus, wherein when the comparison unit compares the second reference signal and the signal component and inverts the output, the counter clock stops counting. The AD converter according to claim 1,
The counting unit is
The comparison unit compares the first reference signal with the reset component and inverts the output until the comparison unit compares the second reference signal with the signal component and inverts the output. A counter enable signal generator for generating a counter enable signal in
An AND gate for receiving the counter enable signal and the clock and outputting the counter clock;
An AD conversion apparatus comprising: an up counter that counts up the counter clock output by the AND gate. In the AD converter according to claim 1 or 2,
The AD converter forcibly starts up counting from the end of the first reference signal to the start of the second reference signal. In the AD converter as described in any one of Claims 1-3,
The counting unit is
A double data rate counter for counting up the rising edge of the counter clock;
When the comparison unit compares the first reference signal and the reset component and inverts the output, the clock is used as it is when the clock is at a low level, and the clock is inverted when the clock is at a high level. An AD converter characterized by being used. In the AD converter as described in any one of Claims 1-3,
The counting unit is
A double data rate counter for counting up the falling edge of the counter clock;
When the comparison unit compares the first reference signal and the reset component and inverts the output, the clock is used as it is when the clock is at a high level, and the clock is used when the clock is at a low level. An AD converter characterized in that the clock is inverted and used. In the AD converter as described in any one of Claims 1-3,
The counting unit is
A double data rate counter for counting up the rising edge of the counter clock;
When the comparison unit compares the first reference signal and the reset component and inverts the output, and the clock is at a high level, the count value incremented by the double data rate counter is set to 1. An AD converter characterized by adding. In the AD converter as described in any one of Claims 1-3,
The counting unit is
A double data rate counter for counting up the falling edge of the counter clock;
When the comparison unit compares the first reference signal with the reset component and inverts the output, when the clock is at a low level, the count value up-counted by the double data rate counter is set to 1. AD converter characterized by adding. In the AD converter as described in any one of Claims 1-7,
A subtraction unit that outputs a difference obtained by subtracting a predetermined value from the count value counted by the count unit as a digital signal;
The subtracting unit obtains, as a digital signal, a difference obtained by subtracting an offset value obtained by counting the clock supplied between the start of the first reference signal and the start of the second reference signal as the predetermined value from the count value. An AD converter characterized by output. An AD conversion apparatus according to claim 8;
A unit pixel that outputs an analog signal including a reset component and a signal component from incident light by a photoelectric conversion element, and converts the analog signal into a digital signal by the AD converter and outputs imaging data; An imaging device. An AD conversion apparatus according to any one of claims 1 to 7,
A unit pixel that outputs an analog signal including a reset component and a signal component from incident light by a photoelectric conversion element;
A light-shielded pixel that is the light-shielded unit pixel;
A difference between the count value obtained from the AD converter that receives an analog signal from the unit pixel and the count value obtained from the AD converter that receives an analog signal from the light-shielded pixel An image pickup apparatus comprising: a signal processing unit that outputs the image data.

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