JP2016184869A - Solid-state image pickup device and driving method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device that can increase the analog-to-digital conversion speed without greatly increasing power consumption.SOLUTION: The solid-state image pickup device includes a pixel for performing photoelectric conversion, a comparison circuit for comparing a reference signal varying with a gradient and an output signal of the pixel, and a counter for receiving a comparison result of the comparison circuit and counting up until the magnitude relationship between the reference signal and the output signal of the pixel is reversed. When the output signal of the pixel is within a first range, the comparison circuit compares the output signal of the pixel and the first reference signal. When the output signal of the pixel is within a second range, the comparison circuit compares the output signal of the pixel and the second reference signal. The comparison range of the first reference signal to be compared by the comparison circuit and the comparison range of the second reference signal to be compared by the comparison circuit are different from each other. The absolute value of the gradient of the first reference signal and the absolute value of the gradient of the second reference signal are different from each other.SELECTED DRAWING: Figure 11

Description

  The present invention relates to a solid-state imaging device and a driving method of the solid-state imaging device.

  In recent years, solid-state imaging devices using a column parallel type analog-digital conversion method have become widespread. A solid-state imaging device of a column parallel type analog-digital conversion system includes a pixel array having a plurality of pixels arranged in a matrix, and a column analog-digital conversion circuit that reads out a pixel signal of each column and performs analog-digital conversion. . The column analog-digital conversion circuit includes a comparator and a counter. As one of analog-digital conversion methods, a method called a single slope method is known.

  In the single slope method, an analog pixel signal is input to one input of a comparator, and a slope signal whose potential changes with a certain slope with time is input to the other input as a reference signal. The counter counts the time from the start of comparison until the output signal of the comparator is inverted, and holds the count value. The count value is output as a digital signal.

  One problem with such a single slope method is that it takes a long time to perform analog-digital conversion processing. For example, when an analog signal is converted into a 10-bit digital value, a period of 1024 clocks is required. In the case of higher resolution without changing the clock frequency, the time required for the analog-digital conversion process increases exponentially according to the number of bits. One way to achieve high resolution at the same time is to increase the clock frequency. However, there is a problem that the power consumption of the comparator and the counter increases in proportion to the clock frequency, which is not practical.

  On the other hand, Patent Document 1 discloses a technique for improving the analog-digital conversion processing speed. Specifically, two reference signals, a first reference signal having a slope from the black signal level toward the saturation signal level, and a second reference signal having a slope different from the slope of the first reference signal, respectively. It has two comparators corresponding to. The first reference signal has a black signal level as a start potential, and the second reference signal has a saturation signal level as a start potential. The first and second reference signals are respectively compared with the pixel signal, and analog-to-digital conversion is performed using the output signal inverted first of the two comparators. By performing such an operation, it is possible to shorten the analog-digital conversion processing time.

JP 2010-251957 A

  However, in the configuration of Patent Document 1, in order to perform analog-digital conversion using two reference signals, it is necessary to simultaneously output two reference signals and simultaneously operate two comparators. Therefore, although the time for analog-digital conversion processing can be shortened, the power consumption is greatly increased compared to the single slope method.

  An object of the present invention is to provide a solid-state imaging device and a driving method of the solid-state imaging device that can increase the analog-digital conversion speed without significantly increasing power consumption.

  The solid-state imaging device of the present invention inputs a pixel that performs photoelectric conversion, a comparison circuit that compares a reference signal that changes with a certain inclination with an output signal of the pixel, and a comparison result of the comparison circuit, and the reference signal and A counter that counts until the magnitude relationship of the output signals of the pixels is reversed, and the comparison circuit, when the output signal of the pixels is within a first range, When the output signal of the pixel is within the second range, the second reference signal is compared with the output signal of the pixel, and the comparison circuit compares the second output signal. The comparison range of one reference signal and the comparison range of the second reference signal compared by the comparison circuit are different from each other, and the absolute value of the slope of the first reference signal and the slope of the second reference signal are different. Absolute values are different from each other.

  Analog-digital conversion speed can be increased without significantly increasing power consumption.

It is a figure which shows the structural example of the solid-state imaging device which concerns on 1st Embodiment. It is a circuit diagram which shows the structural example of a comparison circuit. It is a circuit diagram which shows the structural example of a digital analog converter. It is a figure which shows operation | movement of a digital analog converter. It is a flowchart which shows the correction process of a signal processing part. It is a timing chart which shows analog digital conversion. It is a timing chart which shows analog digital conversion. It is a figure which shows the structural example of the solid-state imaging device which concerns on 2nd Embodiment. It is a circuit diagram which shows the structural example of a digital analog converter. It is a figure which shows operation | movement of a digital analog converter. It is a timing chart which shows a reference signal. It is a circuit diagram which shows the structural example of the comparison circuit which concerns on 3rd Embodiment. It is a figure which shows operation | movement of a digital analog converter. It is a flowchart which shows the correction process of a signal processing part. It is a timing chart which shows a reference signal.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging apparatus according to the first embodiment of the present invention. The pixel unit 100 includes a plurality of pixels 110 arranged in a matrix. A plurality of pixels 110 are provided in a matrix. Each of the plurality of pixels 110 includes a photoelectric conversion unit that performs photoelectric conversion and four transistors (both not shown), and outputs an electrical signal corresponding to the amount of received light. The plurality of column signal lines 101 are provided for each column of the plurality of pixels 110. The vertical selection circuit (VSR) 102 sequentially selects the rows of the plurality of pixels 110 and outputs the signals of the pixels 110 in the selected row to the column signal line 101. Specifically, the vertical selection circuit 102 resets the pixel 110 and causes the column signal line 101 to output a noise signal in a reset release state of the pixel 110. Hereinafter, this operation is referred to as N reading. In addition, the vertical selection circuit 102 causes the column signal line 101 to output an optical signal based on the photoelectric conversion of the pixel 110. Hereinafter, this operation is referred to as S reading.

  Since the pixel 110 is reset to a positive power supply potential by the reset operation, the potential of the column signal line 101 at the time of N reading is a potential that is lower than the positive power supply potential by noise. Further, since the pixel 110 converts light into electrons (negative charge) by photoelectric conversion, the potential of the column signal line 101 at the time of S reading is a potential that is reduced by noise and a photoelectric conversion signal with respect to the positive power supply potential. Become. That is, when the amount of light received by the pixel 110 is small, the potential of the column signal line 101 is relatively high, and when the amount of light received by the pixel 110 is large, the potential of the column signal line 101 is relatively low. The signal processing unit 109 performs correlated double sampling to remove noise generated at the time of reset cancellation by outputting a difference between an optical signal by S reading and a noise signal by N reading.

  The digital-analog converter (DAC) 106 generates a first reference signal Pslope1, a second reference signal Pslope2, and a third reference signal Pslope3 according to the count signal Cnt. Then, the DAC 106 outputs the first reference signal Pslope 1 or the second reference signal Pslope 2 to the signal line A, and outputs the third reference signal Pslope 3 to the signal line B. The first reference signal Pslope1 is a reference signal that changes at a predetermined slope used during N reading. The second reference signal Pslope2 is a reference signal that changes at a predetermined slope used when the analog signal potential Vln (FIG. 2) of the column signal line 101 is larger than the threshold potential Vth during S reading. The third reference signal Pslope3 is a reference signal that changes at a predetermined slope that is used when the analog signal potential Vln of the column signal line 101 is smaller than the threshold potential Vth during S reading. As shown in FIG. 6, the first reference signal Pslope1 and the second reference signal Pslope2 have different inclination polarities. As shown in FIG. 7, the first reference signal Pslope1 and the third reference signal Pslope3 have different absolute values of inclination.

  The plurality of analog-digital converters 103 are provided for each column of the plurality of pixels 110. Each of the plurality of analog-digital converters 103 includes a comparison circuit 104 and a counter 105. A plurality of comparison circuits 104 and counters 105 are provided for each column of pixels 110. The signal lines A and B are connected to the comparison circuit 104 in each column. The analog signal potential Vln is input to the comparison circuit 104 from the pixel 110 through the column signal line 101. Further, a threshold potential Vth for monitoring the analog signal potential Vln of the column signal line 101 is input to the comparison circuit 104. For example, the threshold potential Vth is desirably a potential of the column signal line 101 corresponding to a pixel signal with appropriate exposure that can cover a signal area that is often a main subject. The comparison circuit 104 selects one of the reference signals of the signal lines A and B according to the magnitude relationship between the analog signal potential Vln of the column signal line 101 and the threshold potential Vth, and after the analog signal potential Vln is sufficiently settled. The selected reference signal is compared with the analog signal potential Vln. The comparison circuit 104 inverts the output signal when the magnitude relationship between the selected reference signal and the analog signal potential Vln is reversed.

  The counter 105 performs a count value counting operation in synchronization with the clock signal CLK. The counter 105 has a control terminal and a 1-bit memory, and both are controlled by the comparison circuit 104. The counter 105 performs a counting operation during a period when the comparison result of the comparison circuit 104 is input and a low level is input to the control terminal, and stops the counting operation at the same time as the control terminal changes from the low level to the high level. Holds the count value. The count value held by the counter 105 is a digital signal. Thereby, the analog-digital converter 103 can convert the analog signal of the column signal line 101 into a digital signal. The 1-bit memory of the counter 105 will be described later.

  Each of the plurality of horizontal transfer switches 108 is connected to the counter 105 in each column. A horizontal selection circuit (HSR) 107 turns on the horizontal transfer switch 108 of each column in the order of columns. The count value of the counter 105 of each column is output to the signal processing unit 109 in the column order via the horizontal transfer switch 108. The terminal Out is connected to the input terminal of the signal processing unit 109. The signal processing unit 109 inputs the count value of the counter 105 as a digital signal and performs predetermined signal processing.

  FIG. 2 is a circuit diagram illustrating a configuration example of the comparison circuit 104. The comparison circuit 104 includes comparators 200 and 204, switches 201, 202, 206, and 207, inverters (NOT circuits) 203, 208, and 209, and a logical product (AND) circuit 205, as shown in FIG. Connected to. The comparison circuit 104 receives the reference signal of the signal line A, the reference signal of the signal line B, the analog signal potential Vln of the column signal line 101, the threshold potential Vth, and the state signal Psn. The analog signal potential Vln is an output signal of the pixel 110. The state signal Psn is an external signal, and is a signal that becomes a high level during S reading. Each of the comparators 200 and 204 outputs a high-level output signal when the potential input to the plus input terminal is higher than the potential input to the minus input terminal.

  The analog signal potential Vln of the column signal line 101 is input to the plus input terminal of the comparator 200, and the threshold potential Vth is input to the minus input terminal of the comparator 200. Inverter 203 outputs a logical inversion signal of the output signal of comparator 200. The switch 201 connects the signal line A and the negative input terminal of the comparator 204 according to the output signal of the comparator 200. The switch 202 connects between the signal line B and the negative input terminal of the comparator 204 according to the output signal of the inverter 203. When the analog signal potential Vln is higher than the threshold potential Vth, the switch 201 is turned on and the switch 202 is turned off, and the negative input terminal of the comparator 204 is connected to the signal line A. On the other hand, when the analog signal potential Vln is smaller than the threshold potential Vth, the switch 201 is turned off and the switch 202 is turned on, and the negative input terminal of the comparator 204 is connected to the signal line B.

  The analog signal potential Vln of the column signal line 101 is input to the plus input terminal of the comparator 204. The comparator 204 compares the analog signal potential Vln at the plus input terminal with the reference signal at the minus input terminal. The logical product circuit 205 outputs a logical product signal of the output signal of the comparator 200 and the state signal Psn. The inverter 208 outputs a logical inversion signal of the output signal of the logical product circuit 205. The switch 206 connects between the output terminal of the comparator 204 and the input terminal of the inverter 209 according to the output signal of the AND circuit 205. When the switch 206 is on, the inverter 209 outputs a logic inversion signal of the output signal of the comparator 204 to the control terminal of the counter 105. The switch 207 connects between the output terminal of the comparator 204 and the control terminal of the counter 105 in accordance with the output signal of the inverter 208. The output signal of the comparator 200 is output to the 1-bit memory of the counter 105. When reading S and the analog signal potential Vln is higher than the threshold potential Vth, the switch 206 is turned on and the switch 207 is turned off. In other cases, the switch 206 is turned off and the switch 207 is turned on. That is, during N reading, the switch 206 is always turned off and the switch 207 is turned on. When the analog signal potential Vln is greater than the threshold potential Vth during S reading, the switch 206 is turned on and the switch 207 is turned off. At the time of reading S, if the analog signal potential Vln is smaller than the threshold potential Vth, the switch 206 is turned off and the switch 207 is turned on.

  The counter 105 starts a count value counting operation when the comparator 204 starts a comparison operation. When the control terminal is inverted from a low level to a high level, the counter 105 ends the count value counting operation and holds the count value. The count value held by the counter 105 is a value converted from analog to digital. The value of the 1-bit memory of the counter 105 is determined by the output signal of the comparator 200 in the comparison circuit 104. Specifically, the value of the 1-bit memory of the counter 105 is 1 when the analog signal potential Vln is higher than the threshold potential Vth (low luminance), and when the analog signal potential Vln is lower than the threshold potential Vth (high luminance). Becomes 0. The signal processing unit 109 changes processing according to the value of the 1-bit memory of the counter 105.

  FIG. 3 is a circuit diagram showing a configuration example of the DAC 106 of FIG. As described above, the DAC 106 generates the reference signals Pslope1, Pslope2, and Pslope3, which are substantially linear slope signals. The DAC 106 includes n unit blocks 301 and resistors R1 and R2 for generating slope signals. The unit block 301 has a constant current source 302 that supplies a constant current according to a bias potential, and switches S1 and S2, and each circuit is connected as shown in FIG. In FIG. 3, like the switches S11 and S12, numbers corresponding to the numbers of the unit blocks 301 are added to the end of the word. The switch S1n indicates that it is the switch S1 in the nth unit block 301. The switch S2n indicates that it is the switch S2 in the nth unit block 301. The switches S1 and S2 are controlled by a count signal Cnt. The resistance constant of the resistor R2 is k times the resistance R1, and the current flowing through the constant current source 302 is I. The switch S1 is connected between the constant current source 302 and the resistor R1. The switch S2 is connected between the constant current source 302 and the resistor R2. The signal line A is connected to the resistor R1, and the reference signal Pslope1 or Pslope2 is output. The signal line B is connected to the resistor R2, and the reference signal Pslope3 is output.

  The potential of the signal line A is a potential obtained by multiplying the number of switches S1 that are turned on among the n switches S1 by the current I and the resistance R1. The potential of the signal line B is a potential obtained by multiplying the number of switches S2 that are turned on among the n switches S2 by the current I and the resistance R2. Therefore, by increasing or decreasing the number of switches S1 and S2 that are turned on sequentially, substantially linear slope signals (reference signals) having different slope polarities and absolute slope values are output to the signal lines A and B.

  FIG. 4 is a diagram for explaining the operation of the DAC 106 when the reference signals Pslope1 to Pslope3 are generated. Here, a potential that starts to change approximately linearly with a certain inclination of each reference potential is a start potential, and a potential that finishes changing is an end potential. In FIG. 4, the numbers i and j of unit blocks 301 for turning on the start potential and the end potential of the reference signals Pslope1 to Pslope3, the constant current value I, and the resistance constants R1 and R2 are shown. The potential Vn is an end potential at the time of N reading. The potential Vf is the potential of the column signal line 101 at the time of saturation. n is the number of all unit blocks 301. i is the number of unit blocks 301 that are turned on when the first reference signal Pslope1 reaches the end potential Vn. j is the number of unit blocks 301 that are turned on when the second reference signal Pslope2 becomes the threshold potential Vth. k is a resistance ratio of the resistor R2 to the resistor R1.

  The first reference signal Pslope1 is a reference signal for N reading. The start potential of the first reference signal Pslope1 is the potential nIR1 of the signal line A when all the n switches S11 to S1n are turned on. From there, the number of switches S1 to be turned off is increased one by one. The end potential of the first reference signal Pslope1 is the potential iIR1 (= Vn) of the signal line A when i switches S1 are on. The inclination of the first reference signal Pslope1 is set to -α.

  The second reference signal Pslope2 is a reference signal used when the analog signal potential Vln is within a first range larger than the threshold potential Vth during S reading. The starting potential of the second reference signal Pslope2 is the potential jIR1 (= Vth) of the signal line A when j switches S1 are on. From there, the number of switches S1 to be turned on is increased one by one. The end potential of the second reference signal Pslope2 is the potential nIR1 of the signal line A when all the switches S1 are on. As shown in FIG. 6, the slope of the second reference signal Pslope2 has the same absolute value as the slope of the first Pslope1, has a different polarity, and becomes α.

  The third reference signal Pslope3 is a reference signal used when the analog signal potential Vln is in the second range smaller than the threshold potential Vth during S reading. The starting potential of the third reference signal Pslope3 is the potential (j / k) IR2 (= Vth) of the signal line B when the j / k switches S2 are on. From there, the number of switches S2 to be turned off is increased one by one. The end potential of the third reference signal Pslope3 is the saturation potential Vf. The slope of the third reference signal Pslope3 is −kα because the resistor R2 having a resistance constant k times that of the resistor R1 is used. As shown in FIG. 7, the slope of the third reference signal Pslope3 has the same polarity and a larger absolute value than the slope of the first reference signal Pslope1. The slope of the third reference signal Pslope3 has a different polarity and a larger absolute value than the slope of the second reference signal Pslope2.

  Here, considering the distribution of signals on the high luminance side of a proper exposure image that is generally photographed in large numbers, it is considered that the pixel 110 having a signal near half the saturation level is dominant. Therefore, by setting the threshold potential Vth, which is an intermediate potential between the saturation level and the black level, as the start potential of the third reference signal Pslope3, the counter 105 is quickly stopped, and power consumption can be reduced. The resistance ratio k of the resistor R2 to the resistor R1 is uniquely determined by the threshold potential Vth, the ratio of the difference between the threshold potential Vth and the saturation level with respect to the difference between the black level potential and the threshold potential Vth, and the resistance of the resistor R2 to the resistor R1. The ratio is the same k. As a result, analog-digital conversion can be performed at a higher speed than when a full swing is performed from a black level to a saturation level with a single reference signal having a certain inclination.

  Next, correction processing of the signal processing unit 109 in FIG. 1 will be described. As described above, since the comparison circuit 104 uses different reference signals depending on the situation in the comparison operation, the count value of the counter 105 needs to be corrected. Therefore, the signal processing unit 109 performs correction processing on the digital value based on the value of the 1-bit memory of the counter 105 and the state signal Psn.

  FIG. 5 is a flowchart showing the correction processing of the signal processing unit 109 of FIG. The digital value at the terminal Out in FIG. 1 is C, and the digital value corresponding to the threshold potential Vth is Cth. The signal processing unit 109 inputs the digital value C from the terminal Out. In step S501, the signal processing unit 109 determines whether S reading or N reading is performed based on the state signal Psn. When the state signal Psn is at a low level, the signal processing unit 109 determines that N reading is in progress, and the input digital value C is a signal based on reset, and thus the process proceeds to step S503. On the other hand, when the state signal Psn is at a high level, the signal processing unit 109 determines that the S reading is in progress, and the input digital value C is a signal based on photoelectric conversion, and thus the process proceeds to step S502. .

  In step S502, the signal processing unit 109 determines whether the value of the 1-bit memory of the counter 105 is 1 or 0. When the value of the 1-bit memory of the counter 105 is 1, the signal processing unit 109 is in the case where the analog signal potential Vln is greater than the threshold potential Vth (low luminance), and thus the process proceeds to step S504. On the other hand, when the value of the 1-bit memory of the counter 105 is 0, the signal processing unit 109 is in the case where the analog signal potential Vln is smaller than the threshold potential Vth (high luminance), and thus the process proceeds to step S505.

  In step S503, the signal processing unit 109 does not correct the input digital value C, uses the digital value C as it is as the final digital value, and ends the correction process. In step S504, the signal processing unit 109 sets a value obtained by subtracting the digital value C from the digital value Cth as a final digital value, and ends the correction process. In step S505, the signal processing unit 109 multiplies the digital value C by k, adds the digital value Cth to the multiplication result, and sets the final digital value, and ends the correction process.

  FIG. 6 is a timing chart showing the analog signal potential Vln, the reference signals Pslope1, Pslope2, and the output value of the counter 105 when reading out a certain row of pixels 110, and shows a driving method of the solid-state imaging device. FIG. 6 shows a timing chart when reading out the pixels 110 in the column in which the analog signal potential Vln during S reading is larger than the threshold potential Vth. N reading is performed in a period in which the state signal Psn before time T604 is at a low level. The S reading is performed in a period in which the state signal Psn after time T604 is at a high level.

  First, before the time T601, the reset for resetting the pixel 110 to the positive power supply potential is released, and the analog signal potential Vln of the column signal line 101 becomes a potential that is lower than the positive power supply potential by noise. Yes. The comparison circuit 104 compares the analog signal potential Vln and the threshold potential Vth. Since the analog signal potential Vln is higher than the threshold potential Vth, the switch 201 is turned on and the signal line A is connected to the negative input terminal of the comparator 204. Since the state signal Psn is at a low level indicating N reading, the switch 207 is turned on, and the output signal of the comparator 204 is output to the control terminal of the counter 105 as it is.

  At time T601, since the state signal Psn is at a low level indicating N reading, the DAC 106 starts generating the first reference signal Pslope1 and outputs the first reference signal Pslope1 to the signal line A. At time T601, the signal line A becomes the start potential nIR1 of the first reference signal Pslope1, and the counter 105 starts counting the count value. From time T601 to T603, the first reference signal Pslope1 decreases linearly with time. At time T603, the signal line A becomes the end potential Vn of the first reference signal Pslope1.

  At times T601 to T603, the analog-digital converter 103 performs analog-digital conversion during N reading. At time T602, the magnitude relationship between the analog signal potential Vln and the first reference signal Pslope1 is reversed, so that the output signal of the comparator 204 is inverted from the low level to the high level. Then, the counter 105 finishes counting the count value and holds the count value at that time.

  Next, at times T603 to T604, the horizontal selection circuit 107 turns on the horizontal transfer switch 108 of each column in the column order. The count value held in the counter 105 of each column is output as a digital value C to the signal processing unit 109 via the terminal Out in the column order. As shown in step S503 in FIG. 5, the signal processing unit 109 uses the digital value C as it is as the final digital value.

  As described above, at the time of N reading, the analog signal potential Vln becomes a potential close to the positive power supply potential. Therefore, the first reference signal Pslope1 is linearly decreased from the start potential to the end potential Vn, so that the counter 105 Count periods T601 to T602 are shortened. Thereby, power consumption can be reduced.

  At time T604, the state signal Psn is inverted from the low level to the high level, and switched from N reading to S reading. The count value of the counter 105 is reset. The pixel 110 outputs an optical signal based on photoelectric conversion to the column signal line 101. The analog signal potential Vln of the column signal line 101 is a potential that is reduced by noise and a photoelectric conversion signal with respect to the positive power supply potential. The comparison circuit 104 compares the analog signal potential Vln and the threshold potential Vth. Since the analog signal potential Vln is higher than the threshold potential Vth, the switch 201 is turned on and the signal line A is connected to the negative input terminal of the comparator 204. Since the state signal Psn is at a high level indicating S reading, the switch 206 is turned on, and a logical inversion signal of the output signal of the comparator 204 is output to the control terminal of the counter 105.

  Thereafter, at time T605 to T607 when the analog signal potential Vln is sufficiently settled, the analog-digital converter 103 performs analog-digital conversion at the time of S reading. At time T605, since the state signal Psn is at a high level indicating S reading, the DAC 106 starts generating the second reference signal Pslope2 and outputs the second reference signal Pslope2 to the signal line A. At time T605, the signal line A becomes the start potential Vth of the second reference signal Pslope2, and the counter 105 starts counting the count value. From time T605 to T607, the second reference signal Pslope2 increases linearly with time. At time T607, the signal line A becomes the end potential nIR1 of the second reference signal Pslope2.

  At time T606, the magnitude relationship between the analog signal potential Vln and the first reference signal Pslope1 is reversed, so that the output signal of the comparator 204 is inverted from the high level to the low level. Then, the counter 105 finishes counting the count value and holds the count value at that time. At this time, since the analog signal potential Vln is higher than the threshold potential Vth, 1 is held in the 1-bit memory of the counter 105.

  Next, after time T607, the horizontal selection circuit 107 turns on the horizontal transfer switch 108 of each column in the column order. The count value held in the counter 105 of each column is output as a digital value C to the signal processing unit 109 via the terminal Out in the column order. As shown in step S504 in FIG. 5, the signal processing unit 109 sets a value obtained by subtracting the digital value C from the digital value Cth as the final digital value. Thereafter, the signal processing unit 109 outputs a difference between the final digital value at the time of S reading and the final digital value at the time of N reading as a pixel signal from which noise has been removed.

  As described above, at the time of S reading, the analog signal potential Vln is statistically frequently near the threshold potential Vth. Therefore, the second reference signal Pslope2 is linearly increased from the start potential Vth to the end potential. The count period T605 to T606 of the counter 105 is shortened. Thereby, power consumption can be reduced.

  FIG. 7 is a timing chart showing the analog signal potential Vln, the reference signals Pslope1, Pslope3, and the output value of the counter 105 when reading out a certain row of pixels 110, and shows a driving method of the solid-state imaging device. FIG. 7 shows a timing chart when reading out the pixels 110 in the column in which the analog signal potential Vln during S reading is smaller than the threshold potential Vth. N reading is performed in a period in which the state signal Psn before time T704 is at a low level. The N reading operation before time T704 is the same as the N reading operation before time T604 in FIG.

  The S reading is performed in a period in which the state signal Psn after time T704 is at a high level. At time T704, the state signal Psn is inverted from the low level to the high level, and switched from N reading to S reading. The count value of the counter 105 is reset. The pixel 110 outputs an optical signal based on photoelectric conversion to the column signal line 101. The analog signal potential Vln of the column signal line 101 is a potential that is reduced by noise and a photoelectric conversion signal with respect to the positive power supply potential. The comparison circuit 104 compares the analog signal potential Vln and the threshold potential Vth. Since the analog signal potential Vln is smaller than the threshold potential Vth, the switch 202 is turned on, and the signal line B is connected to the negative input terminal of the comparator 204. Further, the switch 207 is turned on, and the output signal of the comparator 204 is output to the control terminal of the counter 105 as it is.

  Thereafter, at time T705 to T707 when the analog signal potential Vln is sufficiently settled, the analog-digital converter 103 performs analog-digital conversion at the time of S reading. At time T705, since the state signal Psn is at a high level indicating S reading, the DAC 106 starts generating the third reference signal Pslope3 and outputs the third reference signal Pslope3 to the signal line B. At time T705, the signal line B becomes the start potential Vth of the third reference signal Pslope2, and the counter 105 starts counting the count value. At times T705 to T707, the third reference signal Pslope3 decreases linearly with time. At time T707, the signal line B becomes the end potential Vf of the third reference signal Pslope3.

  At time T706, the magnitude relationship between the analog signal potential Vln and the first reference signal Pslope1 is reversed, so that the output signal of the comparator 204 is inverted from the low level to the high level. Then, the counter 105 finishes counting the count value and holds the count value at that time. At this time, since the analog signal potential Vln is smaller than the threshold potential Vth, 0 is held in the 1-bit memory of the counter 105.

  Next, after time T707, the horizontal selection circuit 107 turns on the horizontal transfer switch 108 of each column in the column order. The count value held in the counter 105 of each column is output as a digital value C to the signal processing unit 109 via the terminal Out in the column order. As shown in step S505 in FIG. 5, the signal processing unit 109 multiplies the digital value C by k, and adds the digital value Cth to the multiplication result as the final digital value. Thereafter, the signal processing unit 109 outputs a difference between the final digital value at the time of S reading and the final digital value at the time of N reading as a pixel signal from which noise has been removed.

  As described above, at the time of S reading, the analog signal potential Vln is statistically frequently near the threshold potential Vth. Therefore, the third reference signal Pslope3 is linearly increased from the start potential Vth to the end potential. The count period T705 to T706 of the counter 105 is shortened. Thereby, power consumption can be reduced.

  The comparison range of the second reference signal Pslope2 compared by the comparison circuit 104 and the comparison range of the third reference signal Pslope3 compared by the comparison circuit 104 are different from each other. The absolute value of the slope of the second reference signal Pslope2 and the absolute value of the slope of the third reference signal Pslope3 are different from each other. The luminance of the light received by the pixel 110 when the analog signal potential Vln is smaller than the threshold potential Vth as in S reading in FIG. 7 is such that the analog signal potential Vln is greater than the threshold potential Vth as in S reading in FIG. In this case, the luminance of the light received by the pixel 110 is higher. The absolute value of the slope of the third reference signal Pslope3 is greater than the absolute value of the slope of the second reference signal Pslope2.

  According to the present embodiment, when the analog signal potential Vln is larger than the threshold potential Vth during S reading, the second reference signal Pslope2 increases linearly from the start potential Vth to the end potential nIR1 as shown in FIG. . On the other hand, when the analog signal potential Vln is smaller than the threshold potential Vth during S reading, the third reference signal Pslope3 decreases linearly from the start potential Vth to the end potential Vf as shown in FIG. Therefore, this embodiment can shorten the analog-to-digital conversion time compared to the case where the reference signal changes linearly from the start potential Vf to the end potential nIR1.

  Further, in the present embodiment, the absolute value of the slope of the third reference signal Pslope3 is made larger than the absolute value of the slope of the second reference signal Pslope2, thereby making the analog-digital conversion time of the pixel signal at the time of high luminance in FIG. Can be shortened. Also, as shown in FIG. 6, in the dark signal region that is easily visible, the absolute value of the slope of the second reference signal Pslope2 is made smaller than the absolute value of the slope of the third reference signal Pslope3. As a result, analog-digital conversion can be performed with high resolution without increasing the frequency of the clock signal. In FIG. 7, the absolute value of the slope of the third reference signal Pslope3 is larger than the absolute value of the slope of the second reference signal Pslope2 in the bright signal range in order to increase the analog-digital conversion time. . However, since light shot noise increases in the signal region of the bright part, there is almost no influence on the image quality when the resolution of the analog-digital conversion is lowered in the dark part.

(Second Embodiment)
In the first embodiment, the threshold potential Vth is fixed, but the threshold potential Vth may be variable according to the subject. The second embodiment of the present invention shows an embodiment in which a photometric sensor is provided and the threshold potential Vth and the slope of the reference signal are changed according to the result of the photometric sensor.

  FIG. 8 is a block diagram illustrating a configuration example of a solid-state imaging apparatus according to the second embodiment of the present invention. The solid-state imaging device (FIG. 8) of the present embodiment is obtained by adding a DAC 806 instead of the DAC 106 to the solid-state imaging device (FIG. 1) of the first embodiment, and adding a photometric sensor 810 and a photometric calculation unit 811. It is. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The photometric sensor 810 detects the luminance (brightness) of the subject and outputs the detected luminance to the photometric calculation unit 811. Based on the luminance of the subject detected by the photometric sensor 810, the photometry calculation unit 811 determines whether the subject is a subject that is brighter or darker than the appropriate exposure (reference value), and the determination result is sent to the DAC 806. Output. At this time, the photometry calculating unit 811 sets the threshold potential Vth to Vth1 for an object darker than the appropriate exposure, and sets the threshold potential Vth to Vth2 lower than Vth1 for an object brighter than the appropriate exposure according to the determination result. Set.

  FIG. 9 is a circuit diagram showing a configuration example of the DAC 806 in FIG. The DAC 806 generates reference signals Pslope1 to Pslope5 which are substantially linear slope signals, outputs any one of the reference signals Pslope1 to Pslope3 to the signal line A, and outputs any one of the reference signals Pslope4 and Pslope5 to the signal line B. . The DAC 806 of FIG. 9 is obtained by providing resistors Ra1, Ra2, Rb1, Rb2 and switches Sa1, Sa2, Sb1, Sb2 instead of the resistors R1 and R2 with respect to the DAC 106 of FIG. Hereinafter, differences between the DAC 806 in FIG. 9 and the DAC 106 in FIG. 3 will be described.

  A series connection circuit of the switch Sa1 and the resistor Ra1 is connected between the signal line A and the ground potential node. A series connection circuit of the switch Sa2 and the resistor Ra2 is connected between the signal line A and the ground potential node. A series connection circuit of the switch Sb1 and the resistor Rb1 is connected between the signal line B and the ground potential node. A series connection circuit of the switch Sb2 and the resistor Rb2 is connected between the signal line B and the ground potential node.

  The resistance constant of the resistor Rb1 is g times the resistance constant of the resistor Ra1. The resistance constant of the resistor Rb2 is h times the resistance constant of the resistor Ra2. Further, the resistance ratio g of the resistor Rb1 to the resistor Ra1 is uniquely determined by the threshold potential Vth1. The ratio of the difference between the threshold potential Vth1 and the saturation level with respect to the difference between the black level potential and the threshold potential Vth1, and the resistance ratio of the resistor Rb1 to the resistor Ra1 are the same g. Similarly, the resistance ratio h of the resistor Rb2 to the resistor Ra2 is uniquely determined by the threshold potential Vth2. The ratio of the difference between the threshold potential Vth2 and the saturation level with respect to the difference between the black level potential and the threshold potential Vth2 is the same as the resistance ratio of the resistor Rb2 with respect to the resistor Ra2.

  The switches Sa1, Sa2, Sb1, and Sb2 are controlled by the photometric calculation unit 811. When the subject is darker than the appropriate exposure, the photometry calculation unit 811 turns on the switches Sa1 and Sb1 and turns off the switches Sa2 and Sb2. Conversely, when the subject is brighter than the appropriate exposure, the photometry calculation unit 811 turns off the switches Sa1 and Sb1 and turns on the switches Sa2 and Sb2.

  FIG. 10 is a diagram showing the number i, p, q of unit blocks 301 for turning on the start potential and end potential of the reference signals Pslope 1 to Pslope 5, the constant current value I, and the resistance constants Ra1, Ra2, Rb1, Rb2. . The potential Vn is an end potential at the time of N reading. The potential Vf is the potential of the column signal line 101 at the time of saturation. n is the number of all unit blocks 301. i is the number of unit blocks 301 that are turned on when the first reference signal Pslope1 becomes the potential Vn. p is the number of unit blocks 301 that are turned on when the second reference signal Pslope2 becomes the threshold potential Vth1. q is the number of unit blocks 301 that are turned on when the third reference signal Pslope3 becomes the threshold potential Vth2. g is the resistance ratio of the resistor Ra2 to the resistor Ra1. h represents the resistance ratio of the resistor Rb2 to the resistor Rb1.

  The first reference signal Pslope1 is a reference signal for N reading, as in the first embodiment. The start potential of the first reference signal Pslope1 is the potential nIRa1 of the signal line A when all the n switches S11 to S1n are turned on. From there, the switches S1 to be turned off are sequentially increased one by one. The end potential of the first reference signal Pslope1 is the potential iIRa1 (= Vn) of the signal line A when i switches S1 are on. The inclination of the first reference signal Pslope1 is set to -α.

  The second reference signal Pslope2 is a reference signal used when the analog signal potential Vln is larger than the threshold potential Vth1 when the subject is darker than the appropriate exposure during S reading. The starting potential of the second reference signal Pslope2 is the potential pIRa1 (= Vth1) of the signal line A when the p switches S1 are on. From there, the switches S1 to be turned on are sequentially increased one by one. The end potential of the second reference signal Pslope2 is the potential nIRa1 of the signal line A when all the switches S1 are on. The slope of the second reference signal Pslope2 has the same absolute value, different polarity, and α with respect to the first reference signal Pslope1.

  The third reference signal Pslope3 is a reference signal used when the analog signal potential Vln is larger than the threshold potential Vth2 when the subject is brighter than the appropriate exposure during S reading. The starting potential of the third reference signal Pslope3 is the potential qIRa2 (= Vth2) of the signal line A when the q switches S1 are on. From there, the switches S1 to be turned off are sequentially increased one by one. The end potential of the third reference signal Pslope3 is the potential nIRa1 of the signal line A when all the switches S1 are on. Let the slope of the third reference signal Pslope3 be β. Since the third reference signal Pslope3 uses a resistor Ra2 having a resistance constant larger than that of the resistor Ra1, the slope β of the third reference signal Pslope3 is larger than the slope α of the second reference signal Pslope2.

  The fourth reference signal Pslope4 is a reference signal used when the analog signal potential Vln is smaller than the threshold potential Vth2 when the subject is darker than the appropriate exposure during S reading. The starting potential of the fourth reference signal Pslope4 is the potential (p / g) IRb1 (= Vth2) of the signal line B when the p / g switches S2 are on. From there, the switches S2 to be turned off are sequentially increased one by one. The end potential of the fourth reference signal Pslope4 is the potential Vf. The inclination of the fourth reference signal Pslope4 is −gα because the resistor Rb1 having a resistance constant g times that of the resistor Ra1 is used. The slope of the fourth reference signal Pslope4 is different in polarity from the slope of the second reference signal Pslope2 and has an absolute value of g times.

  The fifth reference signal Pslope5 is a reference signal used when the analog signal potential Vln is smaller than the threshold potential Vth2 when the subject is brighter than the appropriate exposure during S reading. The starting potential of the fifth reference signal Pslope5 is the potential (q / h) IRb2 (= Vth2) of the signal line B when the q / h switches S2 are on. From there, the switches S2 to be turned off are sequentially increased one by one. The end potential of the fifth reference signal Pslope5 is the potential Vf. The slope of the fifth reference signal Pslope5 is −hβ because the resistor Rb2 that is a resistance constant h times that of the resistor Ra2 is used. The inclination of the fifth reference signal Pslope5 is different in polarity from the inclination of the third reference signal Pslope3, and the absolute value thereof is h times.

  The absolute values of the slopes of the reference signals Pslope2, Pslope3, Pslope4, and Pslope5 are different from each other.

  FIG. 11 is a diagram illustrating the reference signals Pslope1 to Pslope5 of the present embodiment. First, the photometric sensor 811 detects the luminance of the subject before analog-digital conversion for N reading starts. The metering calculation unit 811 sets the threshold potential Vth to Vth1 when the subject is darker than the proper exposure, and sets the threshold potential Vth to Vth2 when the subject is brighter than the proper exposure.

  N reading starts, and in the analog-digital conversion period at the time of N reading, the photometric calculation unit 811 turns on the switch Sa1. The first reference signal Pslope1 is output to the signal line A.

  Next, S-read analog-to-digital conversion starts. When the subject is darker than the appropriate exposure, the photometry calculation unit 811 turns on the switches Sa1 and Sb1 and turns off the switches Sa2 and Sb2. As a result, the second reference signal Pslope2 is output to the signal line A, and the fourth reference signal Pslope4 is output to the signal line B. The threshold potential Vth is set to Vth1. When the analog signal potential Vln is within the first range larger than the threshold potential Vth1, the comparator 204 compares the analog signal potential Vln with the second reference signal Pslope2 of the signal line A, and outputs the comparator 204. A logically inverted signal of the signal is input to the control terminal of the counter 105. When the analog signal potential Vln is within the second range smaller than the threshold potential Vth1, the comparator 204 compares the analog signal potential Vln with the fourth reference signal Pslope4 of the signal line B, and compares the comparator 204. Is directly input to the control terminal of the counter 105.

  On the other hand, when the subject is brighter than the appropriate exposure, the photometry calculation unit 811 turns off the switches Sa1 and Sb1 and turns on the switches Sa2 and Sb2. As a result, the third reference signal Pslope3 is output to the signal line A, and the fifth reference signal Pslope1 is output to the signal line B. The threshold potential Vth is set to Vth2. When the analog signal potential Vln is within the third range that is greater than the threshold potential Vth2, the comparator 204 compares the analog signal potential Vln with the third reference signal Pslope3 of the signal line A, and outputs the comparator 204. A logically inverted signal of the signal is input to the control terminal of the counter 105. When the analog signal potential Vln is within the fourth range smaller than the threshold potential Vth2, the comparator 204 compares the analog signal potential Vln with the fifth reference signal Pslope5 of the signal line B, and compares the comparator 204. Is directly input to the control terminal of the counter 105.

  In other respects, the present embodiment performs the same operation as the first embodiment. According to the present embodiment, the threshold potential Vth can be changed according to the luminance of the subject. As a result, analog-to-digital conversion suitable for the luminance of the subject is performed, so that a high-quality image can be obtained regardless of the luminance of the subject. In this embodiment, the threshold potential Vth is binary-controlled based on whether the luminance of the subject is brighter or darker than the appropriate exposure. However, the present invention is not limited to this, and control of three or more values may be performed. In the present embodiment, the threshold potential Vth is changed according to the luminance of the subject by the photometric sensor 810, but the present invention is not limited to this. For example, analog / digital conversion using the threshold potential Vth1 may be selected as a dark mode high image quality mode (first mode), and analog / digital conversion using the threshold potential Vth2 may be selected as a normal mode (second mode).

(Third embodiment)
In the first embodiment, the reference signals Pslope2 and Pslope3 at the time of S reading are different in inclination polarity. However, the present invention is not limited to this. The third embodiment of the present invention shows an example in which the polarities of the slopes of the reference signals Pslope1 to Pslope3 of the first embodiment are the same. Hereinafter, the points of the third embodiment different from the first embodiment will be described.

  In this embodiment, since the reference signals Pslope1 to Pslope3 all have the same polarity, the magnitude relationship between the analog signal potential Vln at the start of the comparison and the reference signal does not change. Therefore, switches 206 and 207, inverters 208 and 209, and an AND circuit 205 for inverting the output signal of the comparator 204 that compares the analog signal potential Vln shown in FIG. 2 of the first embodiment and the reference signal. Is no longer necessary.

  FIG. 12 is a circuit diagram showing a configuration example of the comparison circuit 104 according to the third embodiment of the present invention. The comparison circuit 104 in FIG. 12 is obtained by deleting the switches 206 and 207, the inverters 208 and 209, and the logical product circuit 205 from the comparison circuit 104 in FIG. The comparison circuit 104 includes a comparator 200, switches 201 and 202, an inverter for selecting which of the signal line A and the signal line B is a reference signal according to the magnitude relationship between the analog signal potential Vln and the threshold potential Vth. 203. Further, the comparison circuit 104 includes a comparator 204 for comparing the selected reference signal with the analog signal potential Vln. The output signal of the comparator 204 is always input to the control terminal of the counter 105 as it is.

  FIG. 13 is a diagram showing the number of unit blocks i, j, constant current value I, and resistance constants R1, R2 for turning on the start potential and end potential of the reference signals Pslope1-Pslope3 according to the present embodiment. . The first reference signal Pslope1 of the present embodiment (FIG. 13) is the same as the first reference signal Pslope1 of the first embodiment (FIG. 4). Further, the third reference signal Pslope3 of the present embodiment (FIG. 13) is the same as the third reference signal Pslope3 of the first embodiment (FIG. 4). The second reference signal Pslope2 of the present embodiment (FIG. 13) has a different slope from the second reference signal Pslope2 of the first embodiment (FIG. 4). Hereinafter, the second reference signal Pslope of this embodiment (FIG. 13) will be described.

  The second reference signal Pslope2 is a reference signal used when the analog signal potential Vln is smaller than the threshold potential Vth during S reading. The starting potential of the second reference signal Pslope2 is the potential nIR1 of the signal line A when all the switches S1 are on. From there, sequentially. The switches S1 to be turned off are increased one by one. The end potential of the second reference signal Pslope2 is the potential jIR1 (= Vth) of the signal line A when j switches S1 are on. The slope of the second reference signal Pslope2 is −α, similar to the first reference signal Pslope1.

  FIG. 14 is a flowchart showing the correction processing of the signal processing unit 109 according to this embodiment. The digital value input from the terminal Out by the signal processing unit 109 is C, and the digital value corresponding to the threshold potential Vth is Cth. In step S1401, at the time of reading S, the signal processing unit 109 determines whether the value of the 1-bit memory of the counter 105 is 1 or 0. When the value of the 1-bit memory of the counter 105 is 1, the signal processing unit 109 proceeds to step S1402 because the analog signal potential Vln is greater than the threshold potential Vth (low luminance). On the other hand, when the value of the 1-bit memory of the counter 105 is 0, the signal processing unit 109 is in the case where the analog signal potential Vln is smaller than the threshold potential Vth (high luminance), and thus the process proceeds to step S1403.

  In step S1402, the signal processing unit 109 does not correct the input digital value C, uses the digital value C as it is as the final digital value, and ends the correction process. In step S1403, the signal processing unit 109 multiplies the digital value C by k, adds the digital value Cth to the multiplication result, and sets the final digital value, and ends the correction process. When reading N, as in step S503 of the first embodiment (FIG. 5), the signal processing unit 109 does not correct the input digital value C, but uses the digital value C as it is as the final digital value. End the process.

  FIG. 15 is a diagram illustrating a reference signal according to the present embodiment. In the present embodiment, as in the first embodiment, the first reference signal Pslope1 is used during N reading, and the second reference signal Pslope2 or the third reference signal Pslope3 is used during S reading. The first reference signal Pslope1 is the same as the first reference signal Pslope1 of the first embodiment (FIGS. 6 and 7). The third reference signal Pslope3 is the same as the third reference signal Pslope3 of the first embodiment (FIG. 7).

  The second reference signal Pslope2 has a slope polarity different from that of the second reference signal Pslope2 of the first embodiment (FIG. 6). The second reference signal Pslope2 decreases linearly from the start potential nIR1 to the end potential Vth. The slope of the second reference signal Pslope2 is −α.

  In the present embodiment, as in the first embodiment, it is possible to increase the analog-digital conversion time of the pixel signal at high luminance by increasing the absolute value of the slope of the third reference signal Pslope3. Also, in the dark signal region that is easy to visually recognize, the absolute value of the slope of the second reference signal Pslope2 can be reduced to enable analog-digital conversion with high resolution without increasing the clock frequency. Become.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

103 analog-digital converter, 104 comparison circuit, 105 counter, 110 pixels

Claims (10)

A pixel that performs photoelectric conversion;
A comparison circuit that compares a reference signal that changes at a certain inclination with an output signal of the pixel;
A counter that inputs the comparison result of the comparison circuit and counts until the magnitude relationship between the reference signal and the output signal of the pixel is reversed;
The comparison circuit compares the first reference signal and the output signal of the pixel when the output signal of the pixel is within the first range, and the output signal of the pixel is within the second range. In some cases, the second reference signal is compared with the output signal of the pixel;
The comparison range of the first reference signal compared with the comparison circuit and the comparison range of the second reference signal compared with the comparison circuit are different from each other.
The solid-state imaging device, wherein the absolute value of the slope of the first reference signal and the absolute value of the slope of the second reference signal are different from each other. The luminance of light received by the pixel when the output signal of the pixel is within the second range is the luminance of light received by the pixel when the output signal of the pixel is within the first range. Higher than
The solid-state imaging device according to claim 1, wherein an absolute value of the slope of the second reference signal is larger than an absolute value of the slope of the first reference signal.   3. The solid-state imaging device according to claim 1, wherein the polarity of the slope of the first reference signal and the polarity of the slope of the second reference signal are different from each other. The comparison circuit compares the first reference signal with the output signal of the pixel when the output signal of the pixel is larger than a threshold value, and compares the first reference signal with the output signal of the pixel when the output signal of the pixel is smaller than the threshold value. Comparing the second reference signal and the output signal of the pixel;
The solid-state imaging device according to claim 3, wherein the first reference signal and the second reference signal start to change from the threshold value. The comparison circuit compares a third reference signal with the output signal of the pixel when the signal in the reset release state of the pixel is input, and when the photoelectric conversion signal of the pixel is input, Comparing the first reference signal and the output signal of the pixel, or comparing the second reference signal and the output signal of the pixel;
5. The solid-state imaging device according to claim 1, wherein an absolute value of an inclination of the third reference signal is different from an absolute value of an inclination of the second reference signal.   6. The solid-state imaging device according to claim 5, wherein the absolute value of the slope of the third reference signal is the same as the absolute value of the slope of the first reference signal. Furthermore, it has a photometric sensor that detects the brightness of the subject,
The comparison circuit is
When the brightness of the subject is darker than a reference value, and when the output signal of the pixel is within the first range, the first reference signal and the output signal of the pixel are compared, and If the output signal is within the second range, compare the second reference signal and the output signal of the pixel;
When the brightness of the subject is brighter than the reference value and the output signal of the pixel is within the third range, a third reference signal and the output signal of the pixel are compared, and the output of the pixel If the signal is within the fourth range, compare the fourth reference signal with the output signal of the pixel;
5. The solid-state imaging device according to claim 1, wherein absolute values of inclinations of the first to fourth reference signals are different from each other. The comparison circuit is
In the first mode, when the output signal of the pixel is within the first range, the first reference signal and the output signal of the pixel are compared, and the output signal of the pixel is the second signal. The second reference signal is compared with the output signal of the pixel,
In the second mode, when the output signal of the pixel is within the third range, the third reference signal is compared with the output signal of the pixel, and the output signal of the pixel is within the fourth range. The fourth reference signal is compared with the output signal of the pixel,
5. The solid-state imaging device according to claim 1, wherein absolute values of inclinations of the first to fourth reference signals are different from each other. A plurality of the pixels are provided in a matrix,
The solid-state imaging device according to claim 1, wherein a plurality of the comparison circuits and the counters are provided for each column of the pixels. A pixel that performs photoelectric conversion;
A comparison circuit that compares a reference signal that changes at a certain inclination with an output signal of the pixel;
A solid-state imaging device driving method comprising: a counter that inputs a comparison result of the comparison circuit and performs counting until a magnitude relationship between the reference signal and the output signal of the pixel is reversed;
The comparison circuit, when the output signal of the pixel is within a first range, comparing the first reference signal and the output signal of the pixel;
The comparison circuit includes a step of comparing a second reference signal and the output signal of the pixel when the output signal of the pixel is within a second range;
The comparison range of the first reference signal compared with the comparison circuit and the comparison range of the second reference signal compared with the comparison circuit are different from each other.
The solid-state imaging device driving method, wherein an absolute value of the slope of the first reference signal and an absolute value of the slope of the second reference signal are different from each other.

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