CN110235437A - AD converting means and photographic device - Google Patents
AD converting means and photographic device Download PDFInfo
- Publication number
- CN110235437A CN110235437A CN201780084740.XA CN201780084740A CN110235437A CN 110235437 A CN110235437 A CN 110235437A CN 201780084740 A CN201780084740 A CN 201780084740A CN 110235437 A CN110235437 A CN 110235437A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- signal
- clock
- count
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 claims description 33
- 230000000630 rising effect Effects 0.000 claims description 33
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 7
- 238000004088 simulation Methods 0.000 claims description 5
- 238000012937 correction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 15
- 230000009466 transformation Effects 0.000 description 12
- 230000002596 correlated effect Effects 0.000 description 10
- 238000005070 sampling Methods 0.000 description 10
- 238000001514 detection method Methods 0.000 description 7
- 230000000875 corresponding effect Effects 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 230000001603 reducing effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
AD converting means of the invention has: comparing section (31), is compared to the first contrast signal and the second contrast signal and the picture element signal comprising resetting component and signal component；Count-up counter (34) carries out incremental count to counter clock；Black level correction portion (35), it is modified the black level of the count value of count-up counter (34), wherein, count-up counter (34) is when comparing section (31) is compared to the first contrast signal and reset component and inverts output, it starts counting up, when comparing section (31) is compared the second contrast signal and signal component and inverts output, stop incremental count.By subtracting from by the resulting count value of count-up counter (34) counting by picture element signal resulting value of count-up counter (34) counting from the pixel being blocked, and black level is corrected, while exporting the camera data for eliminating from signal component and resetting component.
Description
Technical field
The present invention relates to AD converting means and photographic devices.
Background technique
In the past, used in a variety of applications using CCD, CMOS as the photographic device of representative.Generally, photographic device is to configuration
Have AD converting means (Analog Digital Converter) for each column (column) of rectangular multiple pixels.AD
Converting means inputs the electric signal (picture element signal) for indicating the simulation of light quantity of incident light from pixel, and carries out to the picture element signal
Digitlization.
Here, the output pixel signal in the form of signal component is plus component is resetted.Therefore, it in AD converting means, holds
Row correlated double samples (Correlated Double Sampling:CDS).CDS is technology below, i.e., by obtaining and again
Difference between the position corresponding signal voltage of component and signal voltage corresponding with signal component, and obtain effective signal component.
For example, in patent document 1, disclosing the AD for having ramp waveform generator, comparator and up-down counter
Converting means.The AD converting means carries out countdown when to component progress AD transformation is resetted, and is carrying out AD to signal component
When transformation, incremental count is carried out.Thus obtained count value is digitized to the signal component progress for eliminating reset component
Count value.
In addition, the high speed in order to realize solid-state imaging apparatus, it is necessary to carry out clock high speed and counter it is low
Consume power.It is proposed to this end that AD converting means below is used particular for the low-order bit for requiring high speed motion
The counter of Gray code is utilized (referring for example to patent document 2).By being set as such structure, the high speed of clock is coped with
Change, in addition avoids the problem that reversion while the bit as binary code.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 2008-259228 bulletin
Patent document 2: Japanese Unexamined Patent Publication 2011-234326 bulletin
Summary of the invention
But in order to count to reset component and signal component, up-down counter is needed, accordingly, there exist below
Problem, i.e. element number increase, and the layout size of column becomes larger.In addition it also has the following problems, that is, needs to be incremented by meter due to switching
The time of number device and down counter, therefore the time required for AD transformation is elongated.
In addition, being reset in the case where having used the counter of Gray code (Gray code) in order to be obtained in CDS
Divide the difference between signal component, needs the respective Gray code for resetting ingredient and signal component being transformed into binary code
(binary code).Therefore become complicated problem with circuit, control.
The present invention given this situation, its object is to: a kind of AD converting means and photographic device are provided, can be pressed down
Layout size processed shortens the time required for AD is converted, avoids as complicated structure.
The embodiments of the present invention to solve the above problems are a kind of AD converting means, will be comprising resetting component and signal
The analog signal of component is transformed to digital signal, which is characterized in that having: comparing section, to signal level
Along with time process, the first contrast signal and the second contrast signal that change and above-mentioned analog signal are compared；It counts
Portion receives the supply of clock, according to the comparison result of the clock and above-mentioned comparing section, generates counter clock, and to the meter
Number device clock carries out incremental count, wherein above-mentioned count section is in above-mentioned comparing section to above-mentioned first contrast signal and above-mentioned reset
When component is compared and inverts output, incremental count is carried out to above-mentioned counter clock, in above-mentioned comparing section to above-mentioned the
When two contrast signals and above-mentioned signal component are compared and invert output, stop the incremental count of above-mentioned counter clock.
In the first embodiment, it can obtain that analog signal is carried out to digitize resulting count value.The count value is
By only being counted from the first contrast signal to the deviant of the resulting fixation of clock the second contrast signal just by having subtracted
It eliminates and resets the digital signal that the resulting real signal component of component is constituted.In this way, can obtain can for AD converting means
Only the count value for the digital signal being made of real signal component can be obtained by subtracting fixed deviant.In addition,
Can the counter counted to count value only be realized with count-up counter.That is, do not have in order to implement correlated double sampling and
Using existing up-down counter, therefore element number can be substantially cut down, the size miniaturization of layout can be made, and avoided
The structure of circuit becomes complicated.In addition, being needed based on switching incremental count and successively decreasing using up-down counter
Several switching times, but in the present invention, do not need such switching time.Therefore, it is able to carry out the AD transformation of higher speed.
Second embodiment of the present invention is a kind of AD converting means, in the AD converting means that first embodiment is recorded
In, it is characterised in that: above-mentioned count section has: counter activation signal generating unit, from above-mentioned comparing section to above-mentioned first
Contrast signal and above-mentioned reset component are compared and output are made to be inverted to above-mentioned comparing section to above-mentioned second contrast signal and upper
State signal component be compared and make output invert until during, generate counter activation signal；AND gate, by above-mentioned meter
Number device activation signal and above-mentioned clock export above-mentioned counter clock as input；Count-up counter, to pass through above-mentioned AND
The above-mentioned counter clock of door output carries out incremental count.
In this second embodiment, count section can be realized with simple circuit structure.
Third embodiment of the present invention is a kind of AD converting means, in the AD transformation that first or second embodiment is recorded
In device, it is characterised in that: above-mentioned count section is in end the opening to above-mentioned second contrast signal from above-mentioned first contrast signal
During until beginning, forcibly start incremental count.
In the third embodiment, even if can also export and answer originally in the case where that can not detect to reset component
The close value of the digital signal of the output.
4th embodiment of the invention is a kind of AD converting means, is remembered in any one embodiment of first~third
In the AD converting means of load, it is characterised in that: above-mentioned count section has: double data rate counter, when to above-mentioned counter
The rising edge of clock carries out incremental count, wherein carries out in above-mentioned comparing section to above-mentioned first contrast signal and above-mentioned reset component
When comparing and inverting output, when above-mentioned clock is low level, above-mentioned clock is directly used, is high level in above-mentioned clock
When, use above-mentioned clock reversally.
Illustrate the 4th embodiment.Double data rate counter of the invention is started counting in the rising edge of clock, is kept
At the end of clock high level or low level as significant bits, it is thus achieved that double data rate.Implement according to the 4th
Mode, can with count clock when starting state independently, started counting always from the rising edge of clock, therefore can be into
The row also correct AD comprising significant bits is converted.
5th embodiment of the invention is a kind of AD converting means, is remembered in any one embodiment of first~third
In the AD converting means of load, it is characterised in that: above-mentioned count section has: double data rate counter, when to above-mentioned counter
The failing edge of clock carries out incremental count, wherein carries out in above-mentioned comparing section to above-mentioned first contrast signal and above-mentioned reset component
When comparing and inverting output, when above-mentioned clock is high level, above-mentioned clock is directly used, is low level in above-mentioned clock
When, use above-mentioned clock reversally.
In the 5th embodiment, the double data rate counter of present embodiment is started counting in the failing edge of clock,
The high level or low level of clock at the end of holding are as significant bits, it is thus achieved that double data rate.According to the 5th
Embodiment, the state of clock when can start with counting independently, are started counting from the failing edge of clock, therefore energy always
The also correct AD comprising significant bits is enough carried out to convert.
Sixth embodiment of the invention is a kind of AD converting means, is remembered in any one embodiment of first~third
In the AD converting means of load, it is characterised in that: above-mentioned count section has: double data rate counter, when to above-mentioned counter
The rising edge of clock carries out incremental count, wherein carries out in above-mentioned comparing section to above-mentioned first contrast signal and above-mentioned reset component
When comparing and inverting output, when above-mentioned clock is high level, it will carry out being incremented by meter by above-mentioned double data rate counter
The resulting count value of number adds 1.
In sixth embodiment, even if do not started counting up from the rising edge of clock in double data rate counter
In the case of, it can also export correct count value also comprising significant bits.
7th embodiment of the invention is a kind of AD converting means, is remembered in any one embodiment of first~third
In the AD converting means of load, it is characterised in that: above-mentioned count section has: double data rate counter, when to above-mentioned counter
The failing edge of clock carries out incremental count, wherein carries out in above-mentioned comparing section to above-mentioned first contrast signal and above-mentioned reset component
When comparing and inverting output, when above-mentioned clock is low level, it will carry out being incremented by meter by above-mentioned double data rate counter
The resulting count value of number adds 1.
In the 7th embodiment, even if do not started counting up from the failing edge of clock in double data rate counter
In the case of, it can also export correct count value also comprising significant bits.
8th embodiment of the invention is a kind of AD converting means, any one embodiment the first~the 7th is remembered
In the AD converting means of load, it is characterised in that: have: subtraction portion will count resulting count value from by above-mentioned count section
It subtracts the resulting difference of specified value to export as digital signal, wherein above-mentioned subtraction portion will subtract conduct from above-mentioned count value
Above-mentioned specified value and count since the first contrast signal to the second contrast signal until during supply it is upper
The resulting difference of the resulting deviant of clock is stated to export as digital signal.
In the 8th embodiment, it can export resulting really by implementing correlated double sampling according to picture element signal
The digital signal (camera data) that signal component is constituted.
9th embodiment of the invention is a kind of photographic device, which is characterized in that is had: what the 8th embodiment was recorded
AD converting means；Unit pixel, by the components of photo-electric conversion, according to incident light, output is comprising resetting component and signal component
Analog signal, wherein above-mentioned analog signal is transformed to by digital signal by above-mentioned AD converting means, exports camera data.
In the 9th embodiment, can by AD converting means to the picture element signal of the simulation obtained from unit pixel into
Digitized obtains camera data.In addition, AD converting means is to digitize analog signal, and carry out correlated double
Sampling, but can the counter at this moment used only be realized with count-up counter.That is, not having to make to implement correlated double sampling
With existing up-down counter, therefore element number can be substantially cut down, the size of the layout of photographic device can be made to minimize,
And the structure that can be avoided circuit becomes complicated.In addition, being needed incremental for switching using up-down counter
The switching time with countdown is counted, but in the present invention, does not need such switching time.Therefore, photographic device can
The AD transformation for carrying out higher speed, being capable of output digit signals (camera data) at high speed.
Tenth embodiment of the invention is a kind of photographic device, which is characterized in that is had: the 6th or the 7th embodiment
The AD converting means of record；Unit pixel, by the components of photo-electric conversion, according to incident light, output is comprising resetting component and letter
The analog signal of number component；Shading pixel is by the above-mentioned unit pixel of shading；Signal processing part, will be from from upper
State above-mentioned count value that the analog signal above-mentioned AD converting means as input of unit pixel obtains with from from above-mentioned screening
The difference for the above-mentioned count value that the analog signal of light pixel above-mentioned AD converting means as input obtains as camera data and
Output.
In the tenth embodiment, as the method for subtracting deviant from count value, as long as carrying out black level amendment,
Deviant can automatically be subtracted.Thereby, it is possible to carry out black level amendment to analog signal, and obtain by having subtracted offset
The digital signal (camera data) that the real signal component of value is constituted.In this way, in the camera device of present embodiment, being not required to
Particularly to prepare the computing circuit for subtracting deviant from count value.Thereby, it is possible to avoid the construction of circuit from becoming in turn
It is complicated.
According to the present invention, a kind of AD converting means and photographic device are provided, layout size is able to suppress, shortens AD transformation
The required time avoids as complicated structure.
Detailed description of the invention
Fig. 1 is the block diagram for indicating the structure of photographic device of embodiment 1.
Fig. 2 is the block diagram of the AD converting means of embodiment 1.
Fig. 3 is the timing diagram of the AD converting means of embodiment 1.
Fig. 4 is the block diagram of the AD converting means of embodiment 2.
Fig. 5 is the timing diagram of the AD converting means of embodiment 2.
Fig. 6 is the block diagram of the AD converting means of embodiment 3.
Fig. 7 is the timing diagram of the AD converting means of embodiment 3.
Fig. 8 is the block diagram of the AD converting means of embodiment 4.
Description of symbols
10: photographic device；11: unit pixel；11D: shading pixel；19: signal processing part；31: comparing section；32,32A:
CE generative circuit；33:AND；34: count-up counter；34A:DDR counter；37: clock/clock generative circuit；38,41:
Latch cicuit；39: delay circuit；40: clock level detection circuit；42: adder.
Specific embodiment
<embodiment 1>
Fig. 1 is the block diagram for indicating the structure of photographic device of present embodiment.The photographic device of present embodiment is installation
The cmos image sensor for the ADC for thering are column to arrange.
Photographic device 10 with having ranks shape (rectangular) two-dimensional arrangement it is many include the components of photo-electric conversion unit pictures
Element 11 made of pixel array unit 12, line-scan circuit 13, column processing portion 14, reference voltage supply unit 15, column scan circuit 16,
Horizontal output line 17, timing control circuit 18 and signal processing part 19.
For timing control circuit 18 according to master clock MCLK, generating becomes line-scan circuit 13, column processing portion 14, reference voltage
The clock signal of the benchmark of the movement of supply unit 15, column scan circuit 16 etc., control signal etc., be supplied to line-scan circuit 13,
Column processing portion 14, reference voltage supply unit 15, column scan circuit 16 etc..
To the constituent parts pixel 11 of pixel array unit 12 on chip (semiconductor substrate) identical with pixel array unit 12
Carry out drive system, signal processing system, the i.e. line-scan circuit 13, column processing portion 14, reference voltage of the periphery of drive control
Supply unit 15, column scan circuit 16, horizontal output line 17 and timing control circuit 18 etc..
As unit pixel 11, in this illustration omitted, other than the components of photo-electric conversion (such as photodiode), such as
It can be used and have and FD (floating will be transferred to charge obtained from incident light progress light-to-current inversion as the components of photo-electric conversion
Diffusion) the transfer transistor in portion, the reset transistor of current potential for controlling the portion FD, output signal corresponding with the current potential in the portion FD
The element of three transistor arrangements of amplifying transistor, four crystal for being also provided additionally with selection transistor for carrying out pixel selection
The element etc. of pipe structure.Here, the analog signal exported from unit pixel 11 is known as picture element signal.
In the unit pixel 11 that pixel array unit 12 is two-dimensionally arranged configured with m row n, and the pixel configuration with m row n column
Accordingly, there is row control line 21 (21-1~21-m) to the wiring of every row, have column signal line 22 (22-1~22-n) to every column wiring.
Each one end of row control line 21-1~21-m is connected to each output end corresponding with each row of line-scan circuit 13.Line-scan circuit
13 are made of shift register etc., carry out the row address of pixel array unit 12 via row control line 21-1~21-m, row scans
Control.
Column processing portion 14 for example has each pixel column for pixel array unit 12, i.e., and each column signal line 22-1~
AD converting means (hereinafter referred to as ADC) 30-1~30-n of 22-n setting, will be every from the constituent parts pixel 11 of pixel array unit 12
The picture element signal of column ground output is transformed to digital signal and exports.In addition, by the ADC30-1 of each column signal line 22-1~22-n
~30-n is referred to as ADC30.ADC30 will be described in detail later.
Reference voltage supply unit 15 generates signal level and passes through the so-called slope changed skewedly along with the time
(RAMP) reference voltage of waveform, specifically, generating reference voltage by DAC (digital-analog transformation circuit).In addition, making
For the unit of the reference voltage of generation RAMP waveform, however it is not limited to DAC.
Reference voltage supply unit 15 is based on according to the control signal provided from timing control circuit 18 from timing control circuit
The 18 clock CLK provided, generate the reference voltage of RAMP waveform, are supplied to the ADC30-1~30-n in column processing portion 14.
Column scan circuit 16 is made of shift register etc., the column address of the ADC30-1~30-n in progress column processing portion 14,
The control of column scan.Under the control of the column scan circuit 16, sequentially pass through via the output of horizontal output line 17 each
ADC30-1~30-n has carried out the digital signal of the N-bit of AD transformation.Horizontal output line 17 by N-bit width signal wire structure
At.
In addition, the structure of the deviation as black level caused by the influence for modifying factor dark current, photographic device 10 has
The pixel (after, referred to as shading pixel 11D) of standby referred to as so-called optical black (Optical Black:OB).Shading pixel
The structure of 11D is identical as unit pixel 11, is by the state of shading.Shading pixel 11D is connect with ADC30D, shading pixel 11D
The analog signal of output is transformed to digital signal by ADC30D.The structure of the ADC30D is knot identical with above-mentioned ADC30
Structure.
Signal processing part 19 is by obtaining the picture element signal that the unit pixel 11 of never shading obtains and the screening from shading
The difference for the picture element signal that light pixel 11D is obtained, Lai Xiuzheng black level.It will be described in detail later, signal processing part 19 will be from
The digital signal and the digital signal conduct input obtained from ADC30D that ADC30 is obtained, export their difference as camera shooting
Data.In addition, signal processing part 19, which can also be more than, carries out such black level amendment, such as digital signal can also be carried out
The various image processing functions such as buffering, drift correction, tonal correction.In addition, signal processing part 19 can also by N-bit and
Capable camera data is transformed to serial camera data, is output to the device of the outside of photographic device 10.
Fig. 2 is the block diagram of ADC.ADC30-1~30-n and ADC30D structure all having the same, here, explanation
ADC30-n。
ADC30-n has comparing section 31, CE generative circuit 32, AND gate 33, count-up counter 34.In addition, CE generative circuit
32, AND gate 33, count-up counter 34 are an embodiments of the count section that claim is recorded.
Comparing section 31 is to the corresponding column signal of the signal exported with the constituent parts pixel 11 of the n-th column from pixel array unit 12
The current potential VSL of line 22-n and the current potential RAMP of the reference voltage supplied from reference voltage supply unit 15 are compared.For example, in electricity
When position RAMP is bigger than current potential VSL, output (Comp.out) is low level, when current potential RAMP is current potential VSL or less, output
It (Comp.out) is high level.
The rising edge of the output of CE generative circuit 32 detection comparing sections 31 makes the value kept reversion every time.For example, right
When CE generative circuit 32 resets, low level is kept.Then, when detecting the rising edge of output of comparing section 31, high electricity is kept
It is flat.Then, when detecting the rising edge of output of comparing section 31, low level is kept.In this way, will join from comparing section 31 to first
It is compared according to signal and reset component and so that output is inverted to comparing section 31 and second contrast signal and signal component are compared
Compared with and the signal that exports is known as counter activation signal during inverting output, referred to as CE (Counter Enable) later
Signal.CE signal becomes the input of AND gate 33.
AND gate 33 exports the logic product of CE signal with the clock CLK provided from timing control circuit 18.By AND gate 33
Output is known as counter clock (Counter CLK).
Count-up counter 34 is out-of-sync counter, is provided to the counter clock from AND gate 33, when with the counter
Clock is synchronously carried out incremental count.Here, count-up counter 34 used the incremental count of binary code.By ADC30
Count-up counter 34 count value be known as count value.In addition, count-up counter 34 is not limited to passing using binary code
It counts up, also may be used the incremental count of Gray code.
Illustrate the movement of the photographic device 10 of above structure using the timing diagram of Fig. 3.In the figure, it is indicated with chain-dotted line
RAMP, it is indicated by the solid line other.
VSL indicates that the current potential for the signal that unit pixel 11 exports, RAMP indicate the RAMP that reference voltage supply unit 15 exports
The reference voltage of waveform.CLK indicates the clock CLK provided from timing control circuit 18.Comp.out indicates the defeated of comparing section 31
Out, CE indicates that the CE signal of CE generative circuit 32, Counter CLK indicate the counter clock exported from AND gate 33.
Specific movement for unit pixel 11, omits the description, but as it is well known, is answered in unit pixel 11
Position movement and transfer movement.It is defeated from unit pixel 11 to column signal line 22-1~22-n as reset component in homing action
The current potential in the portion FD when current potential as defined in being reset to out.In transfer movement, as signal component, believe from 11 nematic of unit pixel
The current potential in the portion FD when number line 22-1~22-n output has transferred the charge of light-to-current inversion from the components of photo-electric conversion.In the figure,
Vr is the current potential for resetting component, and Vs is the current potential comprising resetting the signal component of component.
RAMP waveform includes the first contrast signal Vref1With the second contrast signal Vref2.First contrast signal Vref1Signal
Level is from reference potential V0Start along with from t0To t2Time pass through and decrescence, the second contrast signal Vref2Signal level
From reference potential V0Start along with from t3To t5Time pass through and decrescence.First contrast signal Vref1Compared with resetting component,
And with the second contrast signal Vref2Compare.
In addition, in the present embodiment, only generating the first contrast signal Vref1With the second contrast signal Vref2When generating
Clock CLK.
By row scanning selection certain row i of line-scan circuit 13, from the unit pixel 11 of selection row i to column signal line
22-1~22-n reads in picture element signal, is input to comparing section 31.
Then, the picture element signal being made of the reset component supplied from unit pixel 11 is digitized.Specifically,
Reference voltage supply unit 15 starts to supply the first contrast signal V to comparing section 31ref1(moment t0).In addition, supplying the first reference
Signal Vref1During, supply clock CLK (moment t0~t2)。
Pass through along with the time, the first contrast signal Vref1Signal level reduce, in moment t1With column signal line 22-n's
Current potential VSL is with current potential VrIntersection, in moment t1~t2, current potential become than reset component current potential Vr it is low.
If the first contrast signal Vref1Lower than the current potential Vr for resetting component, then the output of comparing section 31 is inverted from low level
For high level (moment t1).CE generative circuit 32 detects the rising edge of the output of comparing section 31, keeps high level, exports high level
CE signal.AND gate 33 exports clock CLK during CE signal is high level, as counter clock.That is, AND gate 33 exists
From the first contrast signal Vref1T at the time of becoming equal with the current potential Vr for resetting component1To the first contrast signal Vref1End when
Carve t2Until during, output counter clock.
(moment t during having input counter clock from AND gate 33 of count-up counter 341~t2), it carries out being incremented by meter
Number.In this, it is assumed that started counting from " 0 ", and the count at the moment has arrived " C1" (positive integer).
Then, number is carried out to the picture element signal being made of the reset component and signal component that supply from unit pixel 11
Change.Specifically, reference voltage supply unit 15 starts to supply the second contrast signal V to comparing section 31ref2(moment t3)。
In addition, supplying the second contrast signal Vref2During, supply clock CLK (moment t3~t5).As described above,
CE generative circuit 32 is configured to only detect the rising edge for the signal that comparing section 31 exports.In addition, when detecting to reset component, CE
Generative circuit 32 detect comparing section 31 export signal rising edge the result is that keeping high level as former state.
Using the CE signal of such high level and clock CLK as input, therefore AND gate 33 is from being initially supplied the second reference
Signal Vref2When (moment t3) start, export counting clock.
Pass through along with the time, the second contrast signal Vref2Signal level reduce, in moment t4With column signal line 22-n's
Current potential VSL is with current potential Vs intersection, in moment t4~t5, current potential becomes lower than current potential Vs.
If the second contrast signal Vref2Lower than the current potential Vs of the signal component comprising resetting component, then comparing section 31 is defeated
High level (moment t is reversed to from low level out4).CE generative circuit 32 detects the rising edge of the output of comparing section 31, will before this
The high level of holding inverts, and keeps low level.CE signal becomes low level, and therefore, AND gate 33 does not export clock CLK conduct
Counter clock.
In this way, from the second contrast signal Vref2T at the time of beginning3To the second contrast signal Vref2Become and comprising resetting
T at the time of the current potential Vs of the signal component of component is equal4Until during, from 33 output counter clock of AND gate.
(moment t during having input counter clock from AND gate 33 of count-up counter 343~t4), it carries out being incremented by meter
Number.The incremental count is first from moment t1~t2The value of counting starts to continue to count.Assuming that t at the time of stopping counting4Most
Whole count value is " C " (positive integer).
Assuming that from moment t3To moment t4During, it is " C by the value that count-up counter 34 counts2" (positive integer).Cause
This, as shown in formula 1, count value C is count value C1With count value C2Sum.
(formula 1) C=C1+C2
In such count section being made of CE generative circuit 32, AND gate 33 and count-up counter 34, according to when
The comparison result of clock CLK, comparing section 31 generate counter clock, pass through 34 incremental count of the count-up counter counter clock.
Specifically, in comparing section 31 to the first contrast signal Vref1The current potential Vr for resetting component with expression is compared and keeps output anti-
(moment t when turning1), count-up counter 34 carries out incremental count to counter clock.In addition, in the count section, in comparing section
31 couple of second contrast signal Vref2The current potential Vs of signal component with expression comprising resetting component is compared and inverts output
When (moment t4), count-up counter 34 stops the incremental count of counter clock.
By subtracting specified value from the count value C exported by count-up counter 34, can obtain obtaining from unit pixel 11
Picture element signal in eliminate reset component real signal component.The specified value refers to from the first contrast signal
Vref1Beginning (moment t0) to the second contrast signal Vref2Beginning (moment t3) until during the clock CLK that supplies carry out
Count resulting deviant (label is in figure).
Firstly, explanation obtains signal component and subtracting deviant from count value C.
Herein it is assumed that from the first contrast signal Vref1Supply start (moment t0) to the first contrast signal Vref1With electricity
Position Vr intersects (moment t1) until during, produce counter clock, will this period by count-up counter 34 count count
The resulting value of device clock is set as C0。
Deviant is to from the first contrast signal Vref1Beginning (moment t0) to the second contrast signal Vref2Beginning
(moment t3) until during the clock CLK that supplies carry out counting resulting value.In the present embodiment, only join in generation first
According to signal Vref1During (moment t0~t2) clock CLK is generated, therefore to from moment t0To moment t2During generate when
Clock CLK count resulting value as deviant.
Therefore, as shown in formula 2, deviant with by the resulting count value C of 34 count-up counter clock of count-up counter1With
The count value C virtually imagined0And it is equal.
(formula 2) Offset=C0+C1
According to (formula 1) and (formula 2), as shown in formula 3, the resulting difference of deviant is subtracted from count value C and is equal to timing
Value C2With count value C0Difference.
(formula 3) C-Offset=C2-C0
Count value C0It is to the signal level in RAMP waveform from reference potential V0It is reduced to the phase for resetting the current potential Vr of component
Between count value, i.e. to reset component carry out digitizing resulting value.
Count value C2It is to the signal level in RAMP waveform from reference potential V0It is reduced to the signal point comprising resetting component
The value that counts during the current potential Vs of amount carries out digitizing resulting value to the signal component comprising resetting component.
From count value C2Subtract count value C0Resulting value is to carry out digitizing resulting value to real signal component (taking the photograph
As data).Therefore, the difference as obtained from subtracting deviant from the count value C that count-up counter 34 exports is to implementation phase
Real signal component obtained from two re-sampling is closed to carry out digitizing resulting value.
Deviant is in the first contrast signal V of generationref1During the clock CLK that generates carry out counting resulting value,
It therefore is fixed value.It therefore, there is no need to the counter for count offset value.If the first contrast signal Vref1Time span
It is fixed, then determine deviant with being capable of fixing.In addition, deviant is the common value of whole ADC30.
(power is equivalent to by being arranged from the subtraction circuit that the count value C obtained by count-up counter 34 subtracts deviant
The subtraction portion that benefit requires), it can obtain that real signal component is carried out to digitize resulting camera data.But by holding
Row black level amendment described below can also obtain camera shooting number even if subtraction circuit is not arranged particularly according to count value C
According to.Such processing is carried out by signal processing part 19.
Signal processing part 19 has the circuit of the influence of the elimination dark current for carrying out in common photographic device.Tool
It says to body, signal processing part 19 inputs count value C via horizontal output line 17 from count-up counter 34.In addition, signal processing part
19 also carry out digitized ADC30D input count value (hereinafter referred to as dark current to the picture element signal from shading pixel 11D
Count value D).In addition, signal processing part 19 exports the difference of these count values C and dark current count value D as camera data.
If will subtract the resulting real signal component of deviant from count value C is set as Signal, can be such as formula 4
Such representation formula 3.Here, the real signal component in the case where not correcting black level includes dark current component, if will
Dark current component is set as DC (Dark Current), then can indicate as formula 5.For dark current count value D, also can
It is indicated as formula 6 in the same manner as formula 5.
(formula 4) C-Offset=C2-C0=Signal
(formula 5) C=Signal+DC+Offset
(formula 6) D=0+DC+Offset
Analog signal of the dark current count value D based on shading pixel 11D, therefore signal component is 0, includes dark current component
DC and deviant.In other words, subtracting the resulting value of deviant only from dark current count value D indicates the black level signal of dark current.
Deviant is common to whole ADC30, so if subtracting formula 6 from formula 5, then as shown in formula 7, expression, which becomes, to be eliminated
The digital signal (camera data) of the real signal component of dark current component and deviant.
(formula 7) C-D=Signal
In this way, signal processing part 19 obtains the shading pixel 11D of not the count value C of the unit pixel 11 of shading and shading
Dark current count value D difference.Black level amendment is carried out thereby, it is possible to remove dark current component DC, while subtracting offset
Value, and in the same manner as implementing correlated double and sampling, the camera data being made of real signal component can be exported.
After having carried out a series of CDS and AD transformation in ADC30, the number of N-bit is kept in increasing counter 34
Signal.Then, column processing portion will be passed through via the horizontal output line 17 of N-bit width by the column scan of column scan circuit 16
The digital signal that 14 each ADC30-1~30-n has carried out the N-bit of AD transformation outputs sequentially to signal processing part 19.Pass through
Signal processing part 19 carries out the subtraction of black level amendment and deviant, exports camera data.Then, it is repeated by sequentially every row
It is similarly acted, and generates two dimensional image.
ADC30 (AD converting means) described above believes the pixel of the simulation of the unit pixel 11 from rectangular configuration
It number is digitized, remains count value in increasing counter 34.The count value is only fixed by subtracting as described above
The digital signal (camera data) that deviant forms to be made of real signal component.In this way, the ADC30 energy of present embodiment
Enough output only can obtain the count value for the digital signal being made of real signal component by subtracting fixed deviant.
As the structure for obtaining such count value, realized with count-up counter 34.That is, not having to implement correlated double sampling
And existing count-up counter is used, therefore can substantially cut down element number, the layout of ADC30 and photographic device 10 can be made
Size miniaturization.
In addition, using up-down counter, when needing the switching for switching incremental count and countdown
Between.If be illustrated according to Fig. 3, in the first contrast signal Vref1With the second contrast signal Vref2Between (Fig. 3 from the moment
t2To t3) need switching time.But in the ADC30 of present embodiment, such switching time is not needed.Therefore, can
The AD transformation for carrying out higher speed, in addition it is possible to it is expected that the reducing effect of 1/f noise.
In addition, in the present embodiment, to use the count-up counter 34 of binary code to be illustrated for example, but
Also the count-up counter of Gray code can be used.Using the count-up counter of Gray code, it is not necessary to for CDS
With and save the memory of reset signal.
Accordingly even when using the count-up counter of Gray code, the memory of CDS is not needed, in order to which CDS is with and from lattice yet
Thunder code conversion is the circuit of binary code, and circuit, control will not become complicated.In addition, by using the incremental meter of Gray code
Number device, the problem of can be realized the high speed and low consumpting power of clock, and then can be avoided as binary code
Bit while invert.
In turn, the photographic device 10 for having the ADC30 of present embodiment has used the modified signal processing of carry out black level
Portion 19, as the structure for subtracting deviant from the count value obtained by ADC30.By the way that such signal processing part is arranged
19, it is able to carry out black level amendment, and implement correlated double sampling, removes the reset component that picture element signal is included, obtain
The camera data being made of real signal component.Existing photographic device, which typically is provided with, carries out the modified signal processing of black level
Portion 19.Only by applying such signal processing part 19, it will be able to be removed and reset the camera data of component, therefore, no
It needs especially to prepare the subtraction circuit for subtracting deviant from the count value obtained by ADC30.Thereby, it is possible to further keep away
The construction for exempting from circuit becomes complicated.
<embodiment 2>
In the present embodiment, illustrate ADC30 corresponding with the case where resetting component can not be detected.Fig. 4 is the frame of ADC
Figure, Fig. 5 is the timing diagram of ADC.In addition, adding identical appended drawing reference to part same as embodiment 1, omit duplicate
Explanation.
As shown in figure 4, the CE generative circuit 32A of the ADC30 of present embodiment is provided with the CE for forcibly exporting high level
The function of signal.For CE generative circuit 32A, forced counting commencing signal (is recorded as forced counting device to start in the figure
(Forced Counter Start)) movement and embodiment 1 when being low level CE generative circuit 32 it is same.It is forcing to count
When number commencing signal is high level, regardless of inputting, all output high level are as CE signal.
From the first contrast signal Vref1After to the second contrast signal Vref2It is arbitrary fixed during until beginning
When, the forced counting commencing signal of high level is provided to CE generative circuit 32A.
Illustrate the movement of the ADC30 of present embodiment using Fig. 5.
Pass through along with the time, the first contrast signal Vref1Signal level reduce, but sometimes with column signal line 22-n's
Current potential VSL is non-intersecting.For example, the semaphore of picture element signal is bigger when strong light is incident on unit pixel 11, then current potential VSL is got over
It is low, therefore current potential VSL becomes and the first contrast signal V sometimesref1Non-intersecting such low level.
In this case, the CE signal exported from CE generative circuit 32A keeps low level.Therefore, in the first reference
Signal Vref1(moment t0~t2) in, do not start to be incremented by meter from 33 output counter clock of AND gate, increasing counter 34
Number.
Then, from the first contrast signal Vref1End to the second contrast signal Vref2Beginning during (moment t2~
t3), the forced counting commencing signal of high level is provided to CE generative circuit 32A.CE generative circuit 32A is to detecting down as a result,
(to moment t until the rising edge of one output from comparing section 314Until), keep high level.Then, AND gate 33 is
Two contrast signal Vref2During (moment t3~t4), output counter clock, count-up counter 34 carries out incremental count.Then,
In the same manner as embodiment 1, by subtracting dark current count value D from by the resulting count value C of 34 incremental count of count-up counter,
Obtain camera data.
Assuming that in CE generative circuit 32A in the case where Non-precondition function, from the CE signal of CE generative circuit 32A output
Low level is kept, therefore also not from 33 output counter clock of AND gate.As a result, the count value C of count-up counter 34 becomes
0, as black camera data and export.That is, with the practical camera data that there is comparable brightness to be independently used as black and
Output.
But ADC30 according to the present embodiment, it is arranged in CE generative circuit 32A and forcibly carries out count-up counter
The function of 34 counting exports the data close with the camera data that should export thus, it is possible to not output black.
<embodiment 3>
In the present embodiment, illustrate to use double data rate (Double Data Rate:DDR) counter as incremental
The ADC30 of counter.Fig. 6 is the block diagram of ADC, and Fig. 7 is the timing diagram of ADC30.In addition, to part same as embodiment 1
Identical appended drawing reference is added, the repetitive description thereof will be omitted.
As shown in fig. 6, the ADC30 of present embodiment is in comparing section 31 to the first contrast signal Vref1It is carried out with component is resetted
When comparing and inverting output, if clock is low level, then be used directly clock, if clock is high level, makes clock
It inverts and uses.
As the specific structure of the reversion for carrying out such clock, ADC30 has the DDR meter as count-up counter
Number device 34A, comparing section 31 (not shown), CE generative circuit 32 (not shown), clock/clock generative circuit 37 (in the figure for
CLK or CLKB generative circuit), latch cicuit 38 and delay circuit 39.
Clock/clock generative circuit 37 is circuit below, i.e., when detecting the rising edge of CE signal, is in clock
When high level, directly output clock exports the resulting clock item (CLKB) of inverted clock when clock is low level.
In addition, the output of clock/clock generative circuit 37 is input into latch cicuit 38 and keeps.In order to pass through the lock
Circuit 38 is deposited to keep the output of clock/clock generative circuit 37 and use delay circuit 39.
Illustrate the movement of the ADC30 of present embodiment using Fig. 7.The CLK of the figure indicates that clock CLK, CLKB indicate reversion
The resulting clock item of clock CLK.In addition, moment t1Same as content shown in embodiment 1 (Fig. 3), expression detects to reset
(the first contrast signal V when componentref1When intersecting with current potential Vr).Moment t4It indicates to detect the signal component comprising resetting component
When (the second contrast signal Vref2When intersecting with current potential Vs).
Firstly, explanation (moment t when detecting the rising edge of CE signal by clock/clock generative circuit 371) when
Clock CLK is low level situation.At this moment, clock/clock generative circuit 37 directly exports clock CLK.Therefore, it is counted in DDR
It when device 34A starts counting the counting of device clock, is started in the rising edge of counter clock.
On the other hand, illustrate (the moment when detecting the rising edge of CE signal by clock/clock generative circuit 37
t1) clock CLK the case where being high level.At this moment, clock/output of clock generative circuit 37 keeps clock CLK reversion resulting
CLKB.In this way invert clock CLK, therefore the counter clock provided to DDR counter 34A is clock CLKB, is being started
It is the rising edge (t in counter clock when the counting of counter clocka) start.
Assuming that DDR counter 34A is not right in the case where clock/clock generative circuit 37 inverts clock CLK
CLKB and to CLK carry out incremental count.Be the DDR counter 34A counted to the rising edge of counter clock the case where
Under, (from moment t until the rising edge of next counter clock1~tb), it is necessary to it waits, delays the half period or more.
But in the ADC30 of present embodiment, if detecting that the clock CLK when rising edge of CE signal is high electricity
It is flat, then make its reversion.DDR counter 34A can be started counting up from the rising edge of counter clock always as a result,.That is, energy
Enough avoid the case where waiting until the rising edge of next counter clock as described above.In addition, passing through DDR counter
34A carries out incremental count to counter clock, therefore the frequency of counter can be made to become 2 times, and the AD of ADC30 can be made to convert
High speed.
In addition, being constituted as follows using the DDR counter counted to the failing edge of clock.?
(moment t when detecting the rising edge of CE signal by clock/clock generative circuit 371), it is the feelings of high level in clock CLK
Under condition, clock/clock generative circuit 37 directly exports clock CLK.On the other hand, passing through clock/clock generative circuit
37 detect (moment t when the rising edge of CE signal1), in the case where clock CLK is low level situation, clock/clock item generates electricity
Road 37 makes clock CLK invert and export clock CLKB.Make in this way clock CLK invert, to DDR counter provide counter when
Clock is clock CLKB, when starting counting the counting of device clock, is started in the failing edge of counter clock.DDR is counted as a result,
Number device can be started counting up from the failing edge of clock always.That is, can be avoided until the failing edge of next clock
The case where waiting.
<embodiment 4>
In the present embodiment, illustrate to use double data rate (Double Data Rate:DDR) counter as incremental
The ADC30 of counter.Fig. 8 is the block diagram of ADC.In addition, identical appended drawing reference is added to part identical with embodiment 3,
The repetitive description thereof will be omitted.
As shown in figure 8, the ADC30 of present embodiment is in comparing section 31 to the first contrast signal Vref1It is carried out with component is resetted
When comparing and inverting output, if clock is high level, the resulting count value of DDR counter 34A incremental count will be passed through
Add 1.
As the specific structure for realizing such processing, ADC30 has the DDR counter as count-up counter
34A, comparing section 31 (not shown), CE generative circuit 32 (not shown), clock level detection circuit 40 (are in the figure CLKH or L
Detection circuit), latch cicuit 41 and adder 42.
Clock level detection circuit 40 keeps the output i.e. CE for the CE generative circuit 32 for detecting to illustrate in the embodiment 1
The signal level of clock CLK when the rising edge of signal.
If the output for the CE generative circuit 32 that latch cicuit 41 illustrates in the embodiment 1 i.e. CE signal is high level,
Clock CLK is then exported as counter clock, when for low level, keeps clock CLK at this moment.The output quilt of latch cicuit 41
It is input to DDR counter 34A and carries out incremental count.
If the output of 42 clock level detection circuit 40 of adder is high level, will be incremented by by DDR counter 34A
It counts resulting count value to add 1 and export, if the output of clock level detection circuit 40 is low level, directly output passes through
The resulting count value of DDR counter 34A incremental count.
As illustrated in embodiment 3, when detecting the rising edge of CE signal, if clock CLK is high electricity
It is flat, then (from moment t until DDR counter 34A to the rising edge of next counter clock1To tb), it is necessary to it waits.In the feelings
Under condition, DDR counter 34A can not count the counter clock of waiting time, therefore the count value of final output is than correct
The value of count value few 1.
The ADC30 of present embodiment, when clock CLK is high level, DDR is counted when detecting the rising edge of CE signal
The count value of number device 34A output adds 1, therefore can export correct count value.
In addition, using the DDR counter of the failing edge of counting clock, if 42 clock level of adder is examined
The output of slowdown monitoring circuit 40 is low level, then will add 1 output by the resulting count value of DDR counter incremental count.
When detecting the rising edge of CE signal, if clock CLK is low level, DDR counter to next counting
It is had to wait for until the failing edge of device clock.In this case, DDR counter can not count the clock of waiting time, therefore most
The count value exported eventually is fewer than correct count value 1 value.The ADC30 of present embodiment is in the rising edge for detecting CE signal
When, when clock CLK is low level, the count value that DDR counter exports is added 1, therefore correct count value can be exported.
<other embodiments>
It this concludes the description of the embodiments of the present invention, but basic structure of the invention is not limited to above description.
In 1~embodiment of embodiment 4, signal processing part 19 is used to count resulting count value as from ADC30
The unit of offset is subtracted, but it is not limited to this.For example, it is also possible to be arranged in each ADC30 for from by count-up counter 34
The resulting count value of incremental count subtracts the subtraction circuit of deviant.According to the ADC30 for having subtraction circuit in this way, can export
The digital signal (camera data) being made of the real signal component for implementing correlated double sampling according to picture element signal.
In 1~embodiment of embodiment 4, deviant is only generating the first contrast signal Vref1When counting clock CLK,
But it is not limited to this.Deviant can also be counted from the first contrast signal Vref1Start to the second contrast signal Vref2Open
The clock CLK supplied during beginning.It, can also be in moment t if illustrated according to the example of Fig. 32~t3In also generate clock
CLK.In this case, by being subtracted from by the resulting count value of (or the DDR counter 34A) incremental count of count-up counter 34
The deviant can obtain carrying out digitizing resulting camera data to the real signal component for eliminating reset component.Separately
Outside, the first contrast signal and the second contrast signal are not limited to as exemplified by 1~embodiment of embodiment 4.As long as
At least signal level along with the time pass through and change waveform.
In 1~embodiment of embodiment 4, ADC30 is used in order to handle the picture element signal of photographic device, but not
It is limited to such purposes.As long as including the analog signal for resetting component and signal component, it will be able to which application AD of the invention becomes
Changing device.For example, other than the light illustrated in the above-described embodiment, by being telecommunications by electromagnetic waveforms such as radioactive ray
Number element analog signal is transformed to digital signal in the case where, can also apply AD converting means of the invention.
Claims (10)
1. a kind of AD converting means will be transformed to digital signal comprising the analog signal for resetting component and signal component, which becomes
Changing device is characterized in that
Comparing section is passed through and the first contrast signal of signal level variation and the second contrast signal and above-mentioned to along with the time
Analog signal is compared；And
Count section receives the supply of clock, according to the comparison result of the clock and above-mentioned comparing section, generates counter clock, and
Incremental count is carried out to the counter clock,
Above-mentioned count section is compared above-mentioned first contrast signal and above-mentioned reset component in above-mentioned comparing section and keeps output anti-
When turning, incremental count is carried out to above-mentioned counter clock,
When above-mentioned comparing section is compared above-mentioned second contrast signal and above-mentioned signal component and inverts output, in stopping
State the incremental count of counter clock.
2. AD converting means according to claim 1, it is characterised in that:
Above-mentioned count section has:
Counter activation signal generating unit is comparing above-mentioned first contrast signal and above-mentioned reset component from above-mentioned comparing section
Compared with and so that output is inverted to above-mentioned comparing section and above-mentioned second contrast signal and above-mentioned signal component are compared and keep output anti-
During switching to only, counter activation signal is generated；
AND gate exports above-mentioned counter clock using above-mentioned counter activation signal and above-mentioned clock as input；And
Count-up counter carries out incremental count to the above-mentioned counter clock exported by above-mentioned AND gate.
3. AD converting means according to claim 1 or 2, it is characterised in that: above-mentioned count section is from above-mentioned first reference
During the end of signal is until the beginning of above-mentioned second contrast signal, forcibly start incremental count.
4. AD converting means according to any one of claims 1 to 3, it is characterised in that:
Above-mentioned count section has:
Double data rate counter carries out incremental count to the rising edge of above-mentioned counter clock,
When above-mentioned comparing section is compared above-mentioned first contrast signal and above-mentioned reset component and inverts output, above-mentioned
When clock is low level, above-mentioned clock is directly used, when above-mentioned clock is high level, above-mentioned clock is made to invert and use.
5. AD converting means according to any one of claims 1 to 3, it is characterised in that:
Above-mentioned count section has:
Double data rate counter carries out incremental count to the failing edge of above-mentioned counter clock,
When above-mentioned comparing section is compared above-mentioned first contrast signal and above-mentioned reset component and inverts output, above-mentioned
When clock is high level, above-mentioned clock is directly used, when above-mentioned clock is low level, above-mentioned clock is made to invert and use.
6. AD converting means according to any one of claims 1 to 3, it is characterised in that:
Above-mentioned count section has:
Double data rate counter carries out incremental count to the rising edge of above-mentioned counter clock,
When above-mentioned comparing section is compared above-mentioned first contrast signal and above-mentioned reset component and inverts output, above-mentioned
When clock is high level, the count value for carrying out incremental count by above-mentioned double data rate counter is added 1.
7. AD converting means according to any one of claims 1 to 3, it is characterised in that:
Above-mentioned count section has:
Double data rate counter carries out incremental count to the failing edge of above-mentioned counter clock,
When above-mentioned comparing section is compared above-mentioned first contrast signal and above-mentioned reset component and inverts output, above-mentioned
When clock is low level, the count value for carrying out incremental count by above-mentioned double data rate counter is added 1.
8. AD converting means according to any one of claims 1 to 7, characterized by comprising:
Subtraction portion, the difference that specified value is subtracted from the count value counted by above-mentioned count section is defeated as digital signal
Out,
Above-mentioned subtraction portion will be subtracted from above-mentioned count value counted as above-mentioned specified value since the first contrast signal to
The difference of the deviant of the above-mentioned clock supplied during until the beginning of second contrast signal is exported as digital signal.
9. a kind of photographic device, characterized by comprising:
AD converting means according to any one of claims 8；And
Unit pixel, by the components of photo-electric conversion, according to incident light, simulation letter of the output comprising resetting component and signal component
Number,
Above-mentioned analog signal is transformed to digital signal by above-mentioned AD converting means, exports camera data.
10. a kind of photographic device, characterized by comprising:
AD converting means described in claim 6 or 7；
Unit pixel, by the components of photo-electric conversion, according to incident light, simulation letter of the output comprising resetting component and signal component
Number；And
Shading pixel is by the above-mentioned unit pixel of shading；
Signal processing part, from obtaining the above-mentioned AD converting means as input of the analog signal from above-mentioned unit pixel
Above-mentioned count value with it is above-mentioned from the above-mentioned AD converting means as input of the analog signal from above-mentioned shading pixel is obtained
The difference of count value is exported as camera data.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017-014791 | 2017-01-30 | ||
| JP2017014791A JP6195142B1 (en) | 2017-01-30 | 2017-01-30 | AD converter and imaging device |
| PCT/JP2017/033602 WO2018138958A1 (en) | 2017-01-30 | 2017-09-15 | Ad conversion device and image capturing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110235437A true CN110235437A (en) | 2019-09-13 |
Family
ID=59854899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780084740.XA Pending CN110235437A (en) | 2017-01-30 | 2017-09-15 | AD converting means and photographic device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6195142B1 (en) |
| CN (1) | CN110235437A (en) |
| TW (1) | TWI650951B (en) |
| WO (1) | WO2018138958A1 (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304469B (en) * | 2007-05-11 | 2010-10-13 | 索尼株式会社 | Solid imaging apparatus and imaging apparatus |
| US20110121161A1 (en) * | 2009-11-23 | 2011-05-26 | Samsung Electronics Co., Ltd. | Counter circuits, analog to digital converters, image sensors and digital imaging systems including the same |
| WO2011135814A1 (en) * | 2010-04-30 | 2011-11-03 | Sony Corporation | Column a/d converter, column a/d conversion method, solid-state imaging element and camera system |
| CN103051848A (en) * | 2013-01-21 | 2013-04-17 | 长春长光辰芯光电技术有限公司 | Image data analogue-digital conversion method and image sensor |
| CN103686004A (en) * | 2013-12-11 | 2014-03-26 | 格科微电子（上海）有限公司 | Column parallel analog-to-digital converter, pixel photosensitive value output method and CMOS image sensor |
| WO2015111398A1 (en) * | 2014-01-21 | 2015-07-30 | パナソニックＩｐマネジメント株式会社 | Solid-state imaging device |
| CN105338269A (en) * | 2014-08-06 | 2016-02-17 | 爱思开海力士有限公司 | Double data rate counter, and analog-to-digital converter and CMOS image sensor using the same |
| CN105391921A (en) * | 2014-09-02 | 2016-03-09 | 佳能株式会社 | Image capturing apparatus, method of controlling the same, and image sensor |
| JP2016184869A (en) * | 2015-03-26 | 2016-10-20 | キヤノン株式会社 | Solid-state image pickup device and driving method for the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4655500B2 (en) * | 2004-04-12 | 2011-03-23 | ソニー株式会社 | AD converter, semiconductor device for detecting physical quantity distribution, and electronic apparatus |
| JP4786631B2 (en) * | 2007-01-17 | 2011-10-05 | ソニー株式会社 | Solid-state imaging device, imaging device |
| JP4743227B2 (en) * | 2008-05-12 | 2011-08-10 | ソニー株式会社 | AD conversion method, AD conversion apparatus, and semiconductor device and electronic apparatus for detecting physical quantity distribution |
| JP5254140B2 (en) * | 2009-07-14 | 2013-08-07 | 株式会社東芝 | A / D converter and solid-state imaging device including the same |
| JP5868049B2 (en) * | 2011-07-19 | 2016-02-24 | キヤノン株式会社 | Imaging device |
| TWI583195B (en) * | 2012-07-06 | 2017-05-11 | 新力股份有限公司 | A solid-state imaging device and a solid-state imaging device, and an electronic device |
| TWI648986B (en) * | 2014-04-15 | 2019-01-21 | 日商新力股份有限公司 | Image element, electronic equipment |
| TWI669964B (en) * | 2015-04-06 | 2019-08-21 | 日商新力股份有限公司 | Solid-state imaging device, electronic device, and AD conversion device |
-
2017
- 2017-01-30 JP JP2017014791A patent/JP6195142B1/en active Active
- 2017-09-15 WO PCT/JP2017/033602 patent/WO2018138958A1/en active Application Filing
- 2017-09-15 CN CN201780084740.XA patent/CN110235437A/en active Pending
-
2018
- 2018-01-30 TW TW107103155A patent/TWI650951B/en active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304469B (en) * | 2007-05-11 | 2010-10-13 | 索尼株式会社 | Solid imaging apparatus and imaging apparatus |
| US20110121161A1 (en) * | 2009-11-23 | 2011-05-26 | Samsung Electronics Co., Ltd. | Counter circuits, analog to digital converters, image sensors and digital imaging systems including the same |
| WO2011135814A1 (en) * | 2010-04-30 | 2011-11-03 | Sony Corporation | Column a/d converter, column a/d conversion method, solid-state imaging element and camera system |
| CN103051848A (en) * | 2013-01-21 | 2013-04-17 | 长春长光辰芯光电技术有限公司 | Image data analogue-digital conversion method and image sensor |
| CN103686004A (en) * | 2013-12-11 | 2014-03-26 | 格科微电子（上海）有限公司 | Column parallel analog-to-digital converter, pixel photosensitive value output method and CMOS image sensor |
| WO2015111398A1 (en) * | 2014-01-21 | 2015-07-30 | パナソニックＩｐマネジメント株式会社 | Solid-state imaging device |
| CN105338269A (en) * | 2014-08-06 | 2016-02-17 | 爱思开海力士有限公司 | Double data rate counter, and analog-to-digital converter and CMOS image sensor using the same |
| CN105391921A (en) * | 2014-09-02 | 2016-03-09 | 佳能株式会社 | Image capturing apparatus, method of controlling the same, and image sensor |
| JP2016184869A (en) * | 2015-03-26 | 2016-10-20 | キヤノン株式会社 | Solid-state image pickup device and driving method for the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI650951B (en) | 2019-02-11 |
| TW201834400A (en) | 2018-09-16 |
| JP6195142B1 (en) | 2017-09-13 |
| JP2018125623A (en) | 2018-08-09 |
| WO2018138958A1 (en) | 2018-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI392352B (en) | Solid state image capture device, analog/digital conversion method for solid state image capture device, and image capture device | |
| US7292177B2 (en) | Counter circuit, AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus | |
| US7088279B2 (en) | AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus | |
| US8330635B2 (en) | A/D conversion circuit, solid-state image sensor, and camera system | |
| US9398238B2 (en) | Semiconductor device, physical information acquiring apparatus, and signal reading-out method | |
| JP3904111B2 (en) | Solid-state imaging device and signal processing method thereof | |
| EP1655840B1 (en) | Analog-to-digital conversion method, analog-to-digital converter, semiconductor device for detecting distribution of physical quantity, and electronic apparatus | |
| US9041579B2 (en) | Analog-to-digital conversion in pixel arrays | |
| JP4379504B2 (en) | Solid-state imaging device and camera system | |
| EP2547096B1 (en) | Solid-state image sensing apparatus | |
| US20100271525A1 (en) | Integrated AD converter, solid state imaging device, and camera system | |
| KR20090100251A (en) | Analog-to-digital converter, analog-to-digital converting method, solid-state image pickup device, and camera system | |
| CN102461158A (en) | Image sensor adc and cds per column | |
| US9930283B2 (en) | Solid state image sensor and electronic apparatus | |
| CN104580951A (en) | Solid-state image sensing device | |
| KR20080033890A (en) | Solid-image-pickup device, image-pickup device, and method of driving solid-image-pickup device | |
| JP2012204842A (en) | Solid state image pickup device | |
| US9313425B2 (en) | Image pickup device | |
| US20100033601A1 (en) | Solid-state imaging device with a sensor core unit and method of driving the same | |
| CN110235437A (en) | AD converting means and photographic device | |
| JP2014135645A (en) | Solid state imaging device, and drive method therefor | |
| JP3583942B2 (en) | Signal processing device | |
| JP2010087544A (en) | Solid-state imaging element | |
| JPS6110359A (en) | Picture reader |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190913 |