CN103051848A - Image data analogue-digital conversion method and image sensor - Google Patents
Image data analogue-digital conversion method and image sensor Download PDFInfo
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- CN103051848A CN103051848A CN201310021530XA CN201310021530A CN103051848A CN 103051848 A CN103051848 A CN 103051848A CN 201310021530X A CN201310021530X A CN 201310021530XA CN 201310021530 A CN201310021530 A CN 201310021530A CN 103051848 A CN103051848 A CN 103051848A
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Abstract
The invention relates to an image data analogue-digital conversion method and an image sensor. A row selection controller of the image sensor is connected with light sensing unit arrays; each light sensing unit array is connected with a corresponding analogue signal processor through an array bus; each analogue signal processor is connected with a corresponding image data analogue-digital conversion device; and an arithmetic device of each image data analogue-digital conversion device is connected to a multi-path controller. The image data analogue-digital conversion devices adopt the image data analogue-digital conversion method disclosed by the invention to respectively carry out high-level and low-level counting through a low-speed clock pulse and a high-speed clock pulse, and finally obtain quantized pixel image data through operation treatment. The quantized pixel image data is read out of the image sensor array by array by the multi-path controller in a horizontal direction. According to the image data analogue-digital conversion method and the image sensor disclosed by the invention, power consumption of a sensor digital module and ground noises are greatly reduced; and meanwhile, the power consumption of the sensor is not changed along the light intensity so that the image quality of the sensor is further guaranteed.
Description
Technical field
The invention belongs to the acquisition technology field, relate to a kind of view data D conversion method and imageing sensor.
Background technology
The view data D conversion method is mainly used in the analog signal in the image sensor pixel array is quantified as digital signal.Pixel in the imageing sensor is converted to analog electrical signal with light signal, and these signals can process to realize function miscellaneous by some analog and digital signals.
Current, select CMOS technique to be widely used in the Design and manufacture of imageing sensor as the another kind of traditional C CD imageing sensor.It comprises and is called the photosensitive unit array of pixel by us and some are used for reading the auxiliary circuit of array voltage signal.Usually pixel is made of the photodiode of sensitization and the transistor that some are used for pixel is controlled.A typical pixel comprises a photodiode, and one is used for the transistor reset, penetrates grade follower and a transistor that is used for the row choosing for one.When carrying out pixel operation, at first photodiode is reset to a resetting voltage, then photoelectric current can begin photodiode is discharged, after one period time for exposure, photodiode is discharged into a signal voltage, and the difference between resetting voltage and the signal voltage has just represented the intensity of light signal.
At present, particularly in high-speed applications the ramp signal analog to digital converter be widely used in the cmos image sensor.It is by the ramp signal generator, clock-signal generator, and comparator, the count pulse generator sum counter consists of.The analog voltage signal of imageing sensor photosensitive unit output is the output pixel signal after analogue signal processor carries out the correlated-double-sampling processing.Ramp signal is begun along with the time slowly increases or reduces by an initial value.Comparator is placed in the reading circuit of each row, and ramp signal is input to the input of the comparator of each row, and the other end of comparator is picture element signal.When ramp signal reached picture element signal, comparator began turning.By some Digital Logic with for the clock of counting, the pulse of some will be produced and just can be carried out digital quantization to the analog signal of pixel after the counter counting.
In United States Patent (USP) 7880662B2 and United States Patent (USP) 7642947B2, introduced some and directly the difference of resetting voltage and signal voltage has been quantified as the method for digital signal.These methods have all been used one road high-speed clock signal, and its problem is that the clock pulse signal that produces can be counted always.In one 10 analog to digital converter, counter need to be counted the maximum magnitude of voltage of ability quantification 1024 times at least.Particularly in high-resolution imageing sensor, this will cause the digital module power consumption of transducer to become large, and then causes producing a large amount of noises in the substrate of chip.The power consumption of digital module can be along with the Strength Changes of pixel light signal in this analog-to-digital conversion mode in addition, and then causes the chip base noise along with light intensity changes, and picture quality is produced worse impact.The ramp signal analog to digital converter of low-power consumption has larger demand in the high-resolution high speed imaging sensor.
Summary of the invention
The technical problem that the present invention will solve provides and a kind ofly can effectively reduce the rolling counters forward number of times, and then very significantly reduce power consumption and the ground noise of analog to digital converter, the view data D conversion method that the power consumption of unison counter and the size of picture element signal are irrelevant.
In order to solve the problems of the technologies described above, view data D conversion method of the present invention comprises the steps:
Step 1: the pixel reset voltage of analogue signal processor output is sent into an input of comparator, will be sent into for the ramp signal of switch back voltage another input of comparator simultaneously;
Step 2: with the signal of comparator output and at a high speed, low speed two-way clock sends into a count pulse generator, make it produce high-speed pulse and enable with low speed pulse enable clock signal and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse enables to produce the low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 3: the low level count pulse is sent into low counter count, simultaneously, high-order count pulse is sent into high-positioned counter count;
Step 4: the pixel signal voltage of analogue signal processor output is sent into an input of comparator, will be sent into for the ramp signal of switching signal voltage another input of comparator;
Step 5: with the signal of comparator output and at a high speed, low speed two-way clock sends into a count pulse generator, make it produce high-speed pulse and enable with low speed pulse enable two-way clock signal and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse enables to produce the low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 6: the low level count pulse is sent into low counter count, high-order count pulse is sent into high-positioned counter count;
Step 7: the final count value of low counter and high-positioned counter sent into carry out calculation process in the arithmetic unit, the pixel image data after obtaining quantizing.
The n that described high-frequency clock frequency is the low-speed clock frequency times, n is preferably 2
N-LSB, N_LSB is the number of significant digit of low counter.
View data D conversion method of the present invention can adopt following three kinds of quantization methods:
Method one:
In the described step 3, high-positioned counter begins upwards counting from t2 under high-order count pulse control, stop counting at t4, and low counter begins upwards counting from t1 under the control of low level count pulse, finish counting at t2; Wherein t1 for the lower voltage of the ramp signal that is used for switch back voltage to equating with resetting voltage, the moment that comparator begins turning, t2 is the moment that low-speed clock first trailing edge after the comparator upset occurs, and t4 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switch back voltage finishes occurs;
In the described step 6, high-positioned counter begins to continue upwards counting from t6 under high-order count pulse control, finish counting at t8, and low counter begins to continue to begin downward counting from t7 under the control of low level count pulse, finishes counting at t8; Wherein t6 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage begins occurs, t7 equates for the ramp signal that is used for switching signal voltage is reduced to signal voltage, in the moment that comparator begins turning, t8 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 7, arithmetic unit utilizes formula (1) to carry out pixel image data G after calculation process obtains quantizing;
G=MSB*2
N_LSB+LSB （1）
Wherein MSB is the count value of high-positioned counter, and N_LSB is effective counting figure place (not comprising the overflow protection position) of low counter, and LSB is the count value of low counter.
Method two:
In the described step 3, high-positioned counter begins upwards counting from t1 under high-order count pulse control, stop counting at t3, and low counter begins downward counting from t2 under the control of low level count pulse, finish counting at t3; Wherein t1 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switch back voltage begins occurs, t2 for the lower voltage of the ramp signal that is used for switch back voltage to equating with resetting voltage, in the moment that comparator begins turning, t3 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 6, high-positioned counter begins to continue upwards counting from t7 under high-order count pulse control, finish counting at t9, and low counter continues to begin upwards counting from t6 under the control of low level counting pulse signal, finishes counting at t7; Wherein t6 equates for the ramp signal that is used for switching signal voltage is reduced to signal voltage, the moment that comparator begins turning, t7 is the moment that low-speed clock first trailing edge after the comparator upset occurs, and t9 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage finishes occurs;
In the described step 7, arithmetic unit utilizes formula (2) to carry out pixel image data G after calculation process obtains quantizing;
G=S-(MSB*2
N_LSB+LSB) （2）
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place (not comprising the overflow protection position) of low counter, and LSB is the count value of low counter; In the formula-(MSB*2
N_LSB+ LSB) with the picture element signal intensity signal, S is a fixed value.
Method three:
In the described step 3, high-positioned counter begins downward counting from t1 under high-order counting pulse signal control, stop counting at t3, and low counter by begin upwards counting from t2, finishes counting at t3 under the control of low level counting pulse signal; Wherein t1 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switch back voltage begins occurs, t2 for the lower voltage of the ramp signal that is used for switch back voltage to equating with resetting voltage, in the moment that comparator begins turning, t3 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 6, high-positioned counter begins to continue upwards counting from t6 under high-order counting pulse signal control, finish counting at t8, and low counter continues to begin downward counting from t7 under the control of low level counting pulse signal, finishes counting at t8; Wherein t6 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage begins occurs, t7 equates for the ramp signal that is used for switching signal voltage is reduced to signal voltage, in the moment that comparator begins turning, t8 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 7, arithmetic unit utilizes formula (3) to carry out pixel image data G after calculation process obtains quantizing;
G=MSB*2
N_LSB+LSB （3）
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place (not comprising the overflow protection position) of low counter, and LSB is the count value of low counter.
Another technical problem that the present invention will solve is to use the imageing sensor of above-mentioned view data D conversion method.
In order to solve the problems of the technologies described above, imageing sensor of the present invention comprises that row selects controller, and the photosensitive unit array is with the corresponding analogue signal processor of the columns of photosensitive unit array and view data analog-digital commutator, MUX; Described view data analog-digital commutator comprises the ramp signal generator, clock-signal generator, comparator, count pulse generator, high-positioned counter, low counter and arithmetic unit; Row selects controller to be connected with the photosensitive unit array, and each row photosensitive unit is by column bus and the connection of corresponding analogue signal processor, analogue signal processor and corresponding view data analog-digital commutator connection; In the view data analog-digital commutator, an input of comparator is connected to analogue signal processor, and another input of comparator is connected to the output of ramp signal generator; The high speed of the output of comparator and clock signal generator, the output of low speed two-way clock are connected to the input of count pulse generator; The low level count pulse output that count pulse generator produces is connected to low counter, and the high-order count pulse that count pulse generator produces is connected to high-positioned counter; The output of low counter and high-positioned counter is connected to arithmetic unit; The arithmetic unit of each view data analog-digital commutator is connected to MUX.
High-positioned counter of the present invention carries out the high position data counting under high-order counting pulse signal control, low counter is carried out the low data counting under the control of low level counting pulse signal, final quantized data is obtained by simple calculations by the numerical value of two counters, greatly reduce the counts that counter needs, thereby power consumption and the ground noise of Digital Electronics Module have been reduced, simultaneously the power consumption of transducer can be along with light intensity change, and then has guaranteed the picture quality of transducer.For the analog to digital converter of N position, when the high-frequency clock frequency is 2 of low-speed clock frequency
N/2Times the time, power consumption can be reduced to 2 of traditional structure power consumption
-(N/2-1)
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is the structural representation of traditional imageing sensor with the slope analog to digital converter.
Fig. 2 is the counting mode schematic diagram of traditional slope analog to digital converter quantizing pixel signal voltage.
Fig. 3 is the apparatus structure block diagram of realizing view data D conversion method of the present invention.
Fig. 4 is image sensor architecture schematic diagram of the present invention.
Fig. 5 is the counting mode schematic diagram with first embodiment of view data D conversion method quantizing pixel resetting voltage of the present invention and signal voltage difference.
Fig. 6 is the counting mode schematic diagram with second embodiment of view data D conversion method quantizing pixel resetting voltage of the present invention and signal voltage difference.
Fig. 7 is the counting mode schematic diagram with the 3rd embodiment of view data D conversion method quantizing pixel resetting voltage of the present invention and signal voltage difference.
Embodiment
As shown in Figure 1, 2, traditional D conversion method with the slope analog to digital converter is as follows:
Row by conducting delegation selects signal, the photosensitive unit of delegation can be selected, and the analog voltage signal of these photosensitive units is placed and then is admitted in some analog modules (such as amplifier) in the column bus and carries out correlated-double-sampling and process and obtain picture element signal (comprising resetting voltage and light signal voltage).The resetting voltage of pixel at first is placed in the input of comparator, and the other end of comparator is for being used for the ramp signal of switch back voltage, when ramp signal reaches resetting voltage, comparator begins turning, counter begins counting, and when ramp signal finished, counter stopped counting.Then the light signal voltage of pixel places the input of comparator, and this moment, the other end of comparator was the ramp signal for conversion pixel light signal, and when ramp signal voltage reached signal voltage, comparator began turning.Counter continues to begin counting when ramp signal begins, stop counting during the comparator upset.At last the count value of counter is calculated the digital signal of represent pixel light signal size.What the digital signal one after the MUX of horizontal direction will be changed was listed as reads into outside the chip.
As shown in Figure 3, realize that the device of view data D conversion method of the present invention comprises: ramp signal generator, clock-signal generator, comparator, count pulse generator, high-positioned counter, low counter and arithmetic unit; An input of comparator is connected to the output of analogue signal processor; Another input of comparator is connected to the output of ramp signal generator; The high speed of the output of ramp signal generator, comparator and clock signal generator, the output of low speed two-way clock are connected to the input of count pulse generator; Count pulse generator enables and low speed pulse enable two-way clock signal according to the high, low speed two-way clock generating high-speed pulse that ramp signal, comparator output signal and clock signal generator produce, and then enables clock signal and high speed and the high-order count pulse of low speed two-way clock generating and low level count pulse by these two kinds.The low level count pulse output of count pulse generator is connected to low counter, and the high-order count pulse of count pulse generator is connected to high-positioned counter; The output of low counter and high-positioned counter is connected to arithmetic unit.
As shown in Figure 4, imageing sensor of the present invention comprises that row selects controller, and the photosensitive unit array is with the corresponding analogue signal processor of the columns of photosensitive unit array and view data analog-digital commutator, MUX; Row selects controller to be connected with the photosensitive unit array, each row photosensitive unit connects with corresponding analogue signal processor by column bus, one end of the comparator in analogue signal processor and the corresponding view data analog-digital commutator connects, and the arithmetic unit of each view data analog-digital commutator is connected with the MUX of horizontal direction.
Row selects controller to select the photosensitive unit of signal conduction delegation by row, reset aanalogvoltage and the signal imitation voltage of these photosensitive units at first is placed and then is admitted to corresponding analogue signal processor in the column bus, through analogue signal processor carry out correlated-double-sampling process after resetting voltage and the signal voltage of output after processing; The resetting voltage of analogue signal processor output is sent into an input of the comparator of corresponding view data analog-digital commutator; The other end of the ramp signal input comparator that is used for switch back voltage that the ramp signal generator produces; Decline along with ramp signal, pulse signal generator enables and low speed pulse enable two-way clock signal according to the high, low speed two-way clock generating high-speed pulse that ramp signal, comparator output signal and clock signal generator produce, and then enable clock signal by high-frequency clock and high-speed pulse and produce the low level count pulse, produce high-order count pulse by low-speed clock and low speed pulse enable clock signal, the low level count pulse is sent into low counter, and high-order count pulse is sent into high-positioned counter; Low counter is counted under the control of low level counting pulse signal, and high-positioned counter is counted under high-order counting pulse signal control; Then the signal voltage after analogue signal processor carries out the correlated-double-sampling processing is sent into an input of the comparator of corresponding view data analog-digital commutator; The other end of the ramp signal input comparator that is used for switching signal voltage that the ramp signal generator produces; Decline along with ramp signal, count pulse generator enables and low speed pulse enable two-way clock signal according to the high, low speed two-way clock generating high-speed pulse of comparator output signal and the generation of clock signal generator, and then enable clock signal by high-frequency clock and high-speed pulse and produce the low level count pulse, produce high-order count pulse by low-speed clock and low speed pulse enable clock signal, the low level count pulse is sent into low counter and is continued counting, and high-order count pulse is sent into high-positioned counter and continued counting; Pixel image data after the final count value of low counter and high-positioned counter obtains quantizing after internalarithmetic is processed; Pixel image data after each view data analog-digital commutator conversion is read into outside the imageing sensor by the MUX one of horizontal direction with being listed as.
Embodiment one
As shown in Figure 5, for adopting one of implementation method that view data D conversion method of the present invention directly quantizes the difference of pixel reset voltage and signal voltage.In first time quantizing process, resetting voltage is placed on the input of comparator.Ramp signal finishes to t3 from t0.The output of comparator begins turning at t1.Low-speed clock first trailing edge after the comparator upset occurs in t2.Low-speed clock first trailing edge after ramp signal finishes occurs in the t4. high-positioned counter and begins upwards counting from t2, stops counting at t4.Low counter begins upwards at t1, and counting finishes counting at t2.In quantizing for the second time, pixel signal voltage is placed on the input of comparator.Ramp signal is begun by t5, finishes in t9.Low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage begins occurs in the t6. comparator and overturns at t7.Low-speed clock first trailing edge after the comparator upset occurs in the t8. high-positioned counter and begins to continue upwards counting at t6, finishes counting at t8.Low counter begins downward counting at t7, finishes counting at t8.The final numerical value of high-positioned counter and low counter is used for the size of quantizing pixel resetting voltage and signal voltage.Suppose that N_LSB is the counting figure place of low counter, MSB is the numerical value of high-positioned counter, and LSB is the numerical value of low counter, and final quantized value is ' MSB*2
N_LSB+ LSB '.Take 8 of quantization digits as example, high-frequency clock is 16 times of low-speed clock.High-positioned counter begins counting from ' 0000 ', numerical value was ' 0011 ' after counting finished.Low counter begins to count from ' 01111 ', and numerical value was ' 10011 ' after counting finished.Final quantized data position ' 01000011 ' then.Wherein the highest order of low counter is the overflow protection position.
Embodiment two
Fig. 6 another implementation method for adopting view data D conversion method of the present invention directly the difference of pixel reset voltage and signal voltage to be quantized.In first time quantizing process, resetting voltage is placed on the input of comparator.Ramp signal finishes to t4 from t0.The output that low-speed clock first trailing edge after ramp signal begins occurs in the t1. comparator begins turning at t2.Low-speed clock first trailing edge after the comparator upset occurs in the t3. high-positioned counter and begins upwards counting from t1, stops counting at t3.Low counter begins downwards at t2, and counting finishes counting at t3.In for the second time conversion, pixel signal voltage is placed on the input of comparator.Ramp signal is begun by t5, finishes in t8.Comparator overturns at t6.Low-speed clock first trailing edge after comparator upset occurs in t7. low-speed clock first trailing edge after ramp signal finishes and occurs in the t9. high-positioned counter and begin to continue upwards counting at t7, finishes to count at t9.Low counter begins upwards counting at t6, finishes counting at t7.The final numerical value of high-positioned counter and low counter is used for the size of quantizing pixel resetting voltage and signal voltage.Suppose that N_LSB is the counting figure place of low counter, MSB is the numerical value of high-positioned counter, and LSB is the numerical value of low counter, the total bit of N for quantizing, and final quantized value is ' S-(MSB*2
N_LSB+ LSB) '; Wherein S is a fixed value, can select 2 in application process
N-1, also can select other value.Take 8 of quantization digits as example, high-frequency clock is 16 times of low-speed clock.High-positioned counter has, and ' 0000 ' begins counting, and numerical value was ' 0011 ' after counting finished.Low counter begins to count from ' 01111 ', and numerical value was ' 10011 ' after counting finished.Final quantized data position ' 10111100 ' then.Wherein the highest order of low counter is the overflow protection position.
Embodiment three
Fig. 7 another implementation method for adopting view data D conversion method of the present invention directly the difference of pixel reset voltage and signal voltage to be quantized.In first time quantizing process, resetting voltage is placed on the input of comparator.Ramp signal finishes to t4 from t0.The output that low-speed clock first trailing edge after ramp signal begins occurs in the t1. comparator begins turning at t2.Low-speed clock first trailing edge after the comparator upset occurs in the t3. high-positioned counter and begins downward counting from t1, stops counting at t3.Low counter begins upwards at t2, and counting finishes counting at t3.In for the second time conversion, pixel signal voltage is placed on the input of comparator.Ramp signal is begun by t5, finishes in t9.Low-speed clock first trailing edge after the ramp signal of conversion pixel signal voltage begins occurs in t6, and comparator overturns at t7.Low-speed clock first trailing edge after the comparator upset occurs in the t8. high-positioned counter and begins to continue upwards counting at t6, finishes counting at t8.Low counter begins downward counting at t7, finishes counting at t8.The final numerical value of high-positioned counter and low counter is used for the size of quantizing pixel resetting voltage and signal voltage.Suppose that N_LSB is the counting figure place of low counter, MSB is the numerical value of high-positioned counter, and LSB is the numerical value of low counter, and final quantized value is ' MSB*2
N_LSB+ LSB '.Take 8 of quantization digits as example, high-frequency clock is 16 times of low-speed clock.High-positioned counter begins counting by ' 1000 ', and numerical value was ' 0011 ' after counting finished.Low counter begins to count from ' 01111 ', and numerical value was ' 00011 ' after counting finished.Final quantized data position ' 00110011 ' then.Wherein the highest order of low counter is the overflow protection position.
The invention is not restricted to above-described embodiment; can also adopt other counting modes that the difference information of pixel reset voltage and signal voltage is quantized in the view data D conversion method; thereby every any simple deformation of making on claim 1 technical scheme of the present invention basis; such as the counting direction that changes high-positioned counter and low counter (upwards counting changes downward counting into or counts downwards and changes upwards counting into); the trigger point that perhaps changes the counter initial count and finish to count (begins with end and beginning and decline or the rising edge of the high low-speed clock after finishing such as ramp signal; the comparator upset; reach comparator upset afterwards decline or the rising edge of high low-speed clock), all the invention is intended within the protection range.
Claims (6)
1. a view data D conversion method is characterized in that comprising the steps:
Step 1: the pixel reset voltage of analogue signal processor output is sent into an input of comparator, will be sent into for the ramp signal of switch back voltage another input of comparator simultaneously;
Step 2: with the signal of comparator output and at a high speed, low speed two-way clock sends into a count pulse generator, make it produce high-speed pulse and enable with low speed pulse enable clock signal and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse enables to produce the low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 3: the low level count pulse is sent into low counter count, simultaneously, high-order count pulse is sent into high-positioned counter count;
Step 4: the pixel signal voltage of analogue signal processor output is sent into an input of comparator, will be sent into for the ramp signal of switching signal voltage another input of comparator;
Step 5: with the signal of comparator output and at a high speed, low speed two-way clock sends into a count pulse generator, make it produce high-speed pulse and enable with low speed pulse enable two-way clock signal and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse enables to produce the low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 6: the low level count pulse is sent into low counter count, high-order count pulse is sent into high-positioned counter count;
Step 7: the final count value of low counter and high-positioned counter sent into carry out calculation process in the arithmetic unit, the pixel image data after obtaining quantizing.
2. view data D conversion method according to claim 1 is characterized in that n that described high-frequency clock frequency is the low-speed clock frequency doubly, and n is preferably 2
N-LSB, N_LSB is the number of significant digit of low counter.
3. view data D conversion method according to claim 2 is characterized in that:
In the described step 3, high-positioned counter begins upwards counting from t2 under high-order count pulse control, stop counting at t4, and low counter begins upwards counting from t1 under the control of low level count pulse, finish counting at t2; Wherein t1 for the lower voltage of the ramp signal that is used for switch back voltage to equating with resetting voltage, the moment that comparator begins turning, t2 is the moment that low-speed clock first trailing edge after the comparator upset occurs, and t4 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switch back voltage finishes occurs;
In the described step 6, high-positioned counter begins to continue upwards counting from t6 under high-order count pulse control, finish counting at t8, and low counter begins to continue to begin downward counting from t7 under the control of low level count pulse, finishes counting at t8; Wherein t6 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage begins occurs, t7 equates for the ramp signal that is used for switching signal voltage is reduced to signal voltage, in the moment that comparator begins turning, t8 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 7, arithmetic unit utilizes formula (1) to carry out pixel image data G after calculation process obtains quantizing;
G=MSB*2
N_LSB+LSB （1）
Wherein MSB is the count value of high-positioned counter, and N_LSB is effective counting figure place of low counter, and LSB is the count value of low counter.
4. view data D conversion method according to claim 2 is characterized in that:
In the described step 3, high-positioned counter begins upwards counting from t1 under high-order count pulse control, stop counting at t3, and low counter begins downward counting from t2 under the control of low level count pulse, finish counting at t3; Wherein t1 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switch back voltage begins occurs, t2 for the lower voltage of the ramp signal that is used for switch back voltage to equating with resetting voltage, in the moment that comparator begins turning, t3 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 6, high-positioned counter begins to continue upwards counting from t7 under high-order count pulse control, finish counting at t9, and low counter continues to begin upwards counting from t6 under the control of low level counting pulse signal, finishes counting at t7; Wherein t6 equates for the ramp signal that is used for switching signal voltage is reduced to signal voltage, the moment that comparator begins turning, t7 is the moment that low-speed clock first trailing edge after the comparator upset occurs, and t9 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage finishes occurs;
In the described step 7, arithmetic unit utilizes formula (2) to carry out pixel image data G after calculation process obtains quantizing;
G=S-(MSB*2
N_LSB+LSB) （2）
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place of low counter, and LSB is the count value of low counter; S is a fixed value.
5. view data D conversion method according to claim 2 is characterized in that:
In the described step 3, high-positioned counter begins downward counting from t1 under high-order counting pulse signal control, stop counting at t3, and low counter by begin upwards counting from t2, finishes counting at t3 under the control of low level counting pulse signal; Wherein t1 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switch back voltage begins occurs, t2 for the lower voltage of the ramp signal that is used for switch back voltage to equating with resetting voltage, in the moment that comparator begins turning, t3 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 6, high-positioned counter begins to continue upwards counting from t6 under high-order counting pulse signal control, finish counting at t8, and low counter continues to begin downward counting from t7 under the control of low level counting pulse signal, finishes counting at t8; Wherein t6 is the moment that low-speed clock first trailing edge after the ramp signal that is used for switching signal voltage begins occurs, t7 equates for the ramp signal that is used for switching signal voltage is reduced to signal voltage, in the moment that comparator begins turning, t8 is the moment that low-speed clock first trailing edge after the comparator upset occurs;
In the described step 7, arithmetic unit utilizes formula (3) to carry out pixel image data G after calculation process obtains quantizing;
G=MSB*2
N_LSB+LSB （3）
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place of low counter, and LSB is the count value of low counter.
6. one kind is utilized view data D conversion method as claimed in claim 1 to realize the analog-to-digital imageing sensor of view data, it is characterized in that comprising that row selects controller, the photosensitive unit array, with the corresponding analogue signal processor of the columns of photosensitive unit array and view data analog-digital commutator, MUX; Described view data analog-digital commutator comprises the ramp signal generator, clock-signal generator, comparator, count pulse generator, high-positioned counter, low counter and arithmetic unit; Row selects controller to be connected with the photosensitive unit array, and each row photosensitive unit is by column bus and the connection of corresponding analogue signal processor, analogue signal processor and corresponding view data analog-digital commutator connection; In the view data analog-digital commutator, an input of comparator is connected to analogue signal processor, and another input of comparator is connected to the output of ramp signal generator; The high speed of the output of comparator and clock signal generator, the output of low speed two-way clock are connected to the input of count pulse generator; The low level count pulse output that count pulse generator produces is connected to low counter, and the high-order count pulse that count pulse generator produces is connected to high-positioned counter; The output of low counter and high-positioned counter is connected to arithmetic unit; The arithmetic unit of each view data analog-digital commutator is connected to MUX.
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