CN103051848B - Image data analogue-digital conversion and imageing sensor - Google Patents
Image data analogue-digital conversion and imageing sensor Download PDFInfo
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- CN103051848B CN103051848B CN201310021530.XA CN201310021530A CN103051848B CN 103051848 B CN103051848 B CN 103051848B CN 201310021530 A CN201310021530 A CN 201310021530A CN 103051848 B CN103051848 B CN 103051848B
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Abstract
The present invention relates to a kind of image data analogue-digital conversion and imageing sensor.The row of described imageing sensor selects controller to be connected with photosensitive unit array, and each row photosensitive unit is connected with corresponding analogue signal processor by column bus, and analogue signal processor connects with corresponding view data analog-digital commutator; The arithmetic unit of each view data analog-digital commutator is connected to MUX.Wherein view data analog-digital commutator adopts image data analogue-digital conversion of the present invention to carry out high-low position counting respectively by low-speed clock pulse and high-speed clock pulse, finally obtains the pixel image data after quantizing through calculation process.Pixel image data after quantification is read into outside imageing sensor line by line by the MUX of horizontal direction.The present invention greatly reduces power consumption and the ground noise of Digital Electronics Module, and the power consumption of transducer can not change along with light intensity simultaneously, and then ensure that the picture quality of transducer.
Description
Technical field
The invention belongs to acquisition technology field, relate to a kind of image data analogue-digital conversion and imageing sensor.
Background technology
Image data analogue-digital conversion is mainly used in the analog signal in image sensor pixel array to be quantified as digital signal.Light signal is converted to analog electrical signal by the pixel in imageing sensor, and these signals can realize function miscellaneous by some analog and digital signal process.
Current, the another kind as traditional C CD imageing sensor selects CMOS technology to be widely used in the Design and manufacture of imageing sensor.It comprises and is called the photosensitive unit array of pixel by us and some are for reading the auxiliary circuit of array voltage signal.Usual pixel is made up of for the transistor controlled pixel photosensitive photodiode and some.A typical pixel comprises a photodiode, a transistor for resetting, and penetrates grade follower and a transistor for row choosing for one.First a resetting voltage is reset to photodiode when carrying out pixel operation, then photoelectric current can start to discharge to photodiode, after one period of time for exposure, photodiode is discharged into a signal voltage, and the difference between resetting voltage and signal voltage just represents the intensity of light signal.
At present, particularly ramp signal analog to digital converter is widely used in cmos image sensor in high speed applications.It is by ramp signal generator, clock-signal generator, comparator, and count pulse generator sum counter is formed.The analog voltage signal that imageing sensor photosensitive unit exports carries out output pixel signal after correlated-double-sampling process through analogue signal processor.Ramp signal slowly increases along with the time or reduces by an initial value.Comparator is placed in the reading circuit of each row, and ramp signal is input to the input of the comparator of each row, and the other end of comparator is picture element signal.When ramp signal reaches picture element signal, comparator begins turning.By some Digital Logic and the clock for counting, the pulse of some will be produced and just can be carried out digital quantization to the analog signal of pixel after being counted by counter.
In United States Patent (USP) 7880662B2 and United States Patent (USP) 7642947B2, describe the method that the difference of resetting voltage and signal voltage is directly quantified as digital signal by some.These methods all employ a road high-speed clock signal, and its problem is that the clock pulse signal produced can be counted always.In the analog to digital converter of such as 10, at least counter needs the energetic maximum magnitude of voltage of counting 1024.Particularly in high-resolution imageing sensor, this will cause the digital module power consumption of transducer to become large, and then causes producing a large amount of noises in the substrate of chip.In addition in this analog-to-digital conversion mode, the power consumption of digital module can along with the Strength Changes of pixel light signal, and then cause chip base noise to change along with light intensity, produces worse impact to picture quality.The ramp signal analog to digital converter of low-power consumption has larger demand in high-resolution high speed imaging sensor.
Summary of the invention
The technical problem that the present invention will solve is to provide one can effectively reduce rolling counters forward number of times, and then obviously reduce power consumption and the ground noise of analog to digital converter, the image data analogue-digital conversion that the power consumption of unison counter and the size of picture element signal have nothing to do.
In order to solve the problems of the technologies described above, image data analogue-digital conversion of the present invention comprises the steps:
Step one: the pixel reset voltage exported by analogue signal processor sends into an input of comparator, sends into another input of comparator simultaneously by the ramp signal being used for switch back voltage;
Step 2: the signal that comparator is exported and at a high speed, low speed two-way clock sends into a count pulse generator, makes it produce the enable and low speed pulse enable clock signal of high-speed pulse and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse is enable produces low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 3: low level count pulse is sent into low counter and counts, meanwhile, sends high-order count pulse into high-positioned counter and counts;
Step 4: the pixel signal voltage exported by analogue signal processor sends into an input of comparator, sends into another input of comparator by the ramp signal being used for switching signal voltage;
Step 5: the signal that comparator is exported and at a high speed, low speed two-way clock sends into a count pulse generator, makes it produce the enable and low speed pulse enable two-way clock signal of high-speed pulse and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse is enable produces low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 6: low level count pulse is sent into low counter and counts, sends high-order count pulse into high-positioned counter and counts;
Step 7: the final count value of low counter and high-positioned counter is sent in arithmetic unit and carries out calculation process, obtain the pixel image data after quantizing.
Described high-frequency clock frequency is n times of low-speed clock frequency, and n is preferably 2
n-LSB, N_LSB is the number of significant digit of low counter.
Image data analogue-digital conversion of the present invention can adopt following three kinds of quantization methods:
Method one:
In described step 3, high-positioned counter upwards counts under high-order count pulse controls from t2, stops counting at t4, and low counter upwards counts under low level count pulse controls from t1, terminates counting at t2; Wherein t1 is reduced to equal with resetting voltage for the voltage of the ramp signal of switch back voltage, the moment that comparator begins turning, when first trailing edge that t2 is low-speed clock after comparator upset occurs, t4 is that low-speed clock is when the trailing edge of first after the ramp signal for switch back voltage terminates occurs;
In described step 6, high-positioned counter continues upwards to count under high-order count pulse controls from t6, terminates counting at t8, and low counter starts to continue downward counting from t7 under low level count pulse controls, and terminates counting at t8; Wherein t6 is that first trailing edge of low-speed clock after the ramp signal for switching signal voltage starts is when occurring, t7 is reduced to equal with signal voltage for the ramp signal of switching signal voltage, the moment that comparator begins turning, when first trailing edge that t8 is low-speed clock after comparator upset occurs;
In described step 7, arithmetic unit utilizes formula (1) to carry out calculation process and obtains the pixel image data G after quantizing;
G=MSB*2
N_LSB+LSB（1）
Wherein MSB is the count value of high-positioned counter, and N_LSB is effective counting figure place (not comprising overflow protection position) of low counter, and LSB is the count value of low counter.
Method two:
In described step 3, high-positioned counter upwards counts under high-order count pulse controls from t1, stops counting at t3, low counter under low level count pulse controls from t2 downward counting, terminate counting at t3; Wherein t1 is that first trailing edge of low-speed clock after the ramp signal for switch back voltage starts is when occurring, t2 is reduced to equal with resetting voltage for the voltage of the ramp signal of switch back voltage, the moment that comparator begins turning, when first trailing edge that t3 is low-speed clock after comparator upset occurs;
In described step 6, high-positioned counter continues upwards to count under high-order count pulse controls from t7, terminates counting at t9, and low counter continues upwards to count from t6 under low level counting pulse signal controls, and terminates counting at t7; Wherein t6 is reduced to equal with signal voltage for the ramp signal of switching signal voltage, the moment that comparator begins turning, when first trailing edge that t7 is low-speed clock after comparator upset occurs, t9 is that low-speed clock is when the trailing edge of first after the ramp signal for switching signal voltage terminates occurs;
In described step 7, arithmetic unit utilizes formula (2) to carry out calculation process and obtains the pixel image data G after quantizing;
G=S-(MSB*2
N_LSB+LSB)（2）
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place (not comprising overflow protection position) of low counter, and LSB is the count value of low counter; In formula-(MSB*2
n_LSB+ LSB) with picture element signal intensity signal, S is a fixed value.
Method three:
In described step 3, high-positioned counter under high-order counting pulse signal controls from t1 downward counting, stop counting at t3, low counter upwards counts by from t2 under low level counting pulse signal controls, and terminates counting at t3; Wherein t1 is that first trailing edge of low-speed clock after the ramp signal for switch back voltage starts is when occurring, t2 is reduced to equal with resetting voltage for the voltage of the ramp signal of switch back voltage, the moment that comparator begins turning, when first trailing edge that t3 is low-speed clock after comparator upset occurs;
In described step 6, high-positioned counter continues upwards to count under high-order counting pulse signal controls from t6, terminates counting at t8, and low counter continues downward counting from t7 under low level counting pulse signal controls, and terminates counting at t8; Wherein t6 is that first trailing edge of low-speed clock after the ramp signal for switching signal voltage starts is when occurring, t7 is reduced to equal with signal voltage for the ramp signal of switching signal voltage, the moment that comparator begins turning, when first trailing edge that t8 is low-speed clock after comparator upset occurs;
In described step 7, arithmetic unit utilizes formula (3) to carry out calculation process and obtains the pixel image data G after quantizing;
G=MSB*2
N_LSB+LSB（3）
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place (not comprising overflow protection position) of low counter, and LSB is the count value of low counter.
Another technical problem that the present invention will solve applies the imageing sensor of above-mentioned image data analogue-digital conversion.
In order to solve the problems of the technologies described above, imageing sensor of the present invention comprises row and selects controller, photosensitive unit array, the analogue signal processor corresponding to the columns of photosensitive unit array and view data analog-digital commutator, MUX; Described view data analog-digital commutator comprises ramp signal generator, clock-signal generator, comparator, count pulse generator, high-positioned counter, low counter and arithmetic unit; Row selects controller to be connected with photosensitive unit array, and each row photosensitive unit is connected with corresponding analogue signal processor by column bus, and analogue signal processor connects with corresponding view data analog-digital commutator; In view data analog-digital commutator, an input of comparator is connected to analogue signal processor, and another input of comparator is connected to the output of ramp signal generator; The output of comparator and the high speed of clock-signal generator, low speed two-way clock export the input being connected to count pulse generator; The low level count pulse that count pulse generator produces exports and is connected to low counter, and the high-order count pulse that count pulse generator produces is connected to high-positioned counter; The output of low counter and high-positioned counter is connected to arithmetic unit; The arithmetic unit of each view data analog-digital commutator is connected to MUX.
High-positioned counter of the present invention carries out high position data counting under high-order counting pulse signal controls, low counter carries out low data counting under low level counting pulse signal controls, final quantized data is obtained by simple calculations by the numerical value of two counters, greatly reduce the counts that counter needs, thus reduce power consumption and the ground noise of Digital Electronics Module, the power consumption of transducer can not change along with light intensity simultaneously, and then ensure that the picture quality of transducer.For the analog to digital converter of N position, when high-frequency clock frequency is 2 of low-speed clock frequency
n/2times time, power consumption can be reduced to 2 of traditional structure power consumption
-(N/2-1).
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the structural representation of traditional imageing sensor with slope analog to digital converter.
Fig. 2 is the counting mode schematic diagram of traditional slope analog to digital converter quantizing pixel signal voltage.
Fig. 3 is the apparatus structure block diagram realizing image data analogue-digital conversion of the present invention.
Fig. 4 is image sensor architecture schematic diagram of the present invention.
Fig. 5 is the counting mode schematic diagram of first embodiment by image data analogue-digital conversion quantizing pixel resetting voltage of the present invention and signal voltage difference.
Fig. 6 is the counting mode schematic diagram of second embodiment by image data analogue-digital conversion quantizing pixel resetting voltage of the present invention and signal voltage difference.
Fig. 7 is the counting mode schematic diagram of the 3rd embodiment by image data analogue-digital conversion quantizing pixel resetting voltage of the present invention and signal voltage difference.
Embodiment
As shown in Figure 1, 2, traditional D conversion method with slope analog to digital converter is as follows:
Signal is selected by the row of conducting a line, the photosensitive unit of a line can be selected, and the analog voltage signal of these photosensitive units is placed in column bus and is then admitted to (such as amplifier) in some analog modules and carries out correlated-double-sampling process and obtain picture element signal (comprising resetting voltage and photo signal voltage).First the resetting voltage of pixel is placed in the input of comparator, and the other end of comparator is the ramp signal for switch back voltage, when ramp signal reaches resetting voltage, comparator begins turning, counter starts counting, and at the end of ramp signal, counter stops counting.Then the photo signal voltage of pixel is placed in the input of comparator, and now the other end of comparator is the ramp signal for changing pixel light signal, and when ramp signal voltage reaches signal voltage, comparator begins turning.Continue when counter is from ramp signal to start counting, during comparator upset, stop counting.Finally the count value of counter is calculated to the digital signal of represent pixel light signal size.What the digital signal one after conversion arranged by the MUX of horizontal direction reads into outside chip.
As shown in Figure 3, the device realizing image data analogue-digital conversion of the present invention comprises: ramp signal generator, clock-signal generator, comparator, count pulse generator, high-positioned counter, low counter and arithmetic unit; An input of comparator is connected to the output of analogue signal processor; Another input of comparator is connected to the output of ramp signal generator; The output of ramp signal generator, comparator and the high speed of clock-signal generator, low speed two-way clock export the input being connected to count pulse generator; Enable and the low speed pulse enable two-way clock signal of the high, low speed two-way clock generating high-speed pulse that count pulse generator produces according to ramp signal, comparator output signal and clock-signal generator, so by these two kinds of enable clock signals with at a high speed and low speed two-way clock generating high position count pulse and low level count pulse.The low level count pulse of count pulse generator exports and is connected to low counter, and the high-order count pulse of count pulse generator is connected to high-positioned counter; The output of low counter and high-positioned counter is connected to arithmetic unit.
As shown in Figure 4, imageing sensor of the present invention comprise row select controller, photosensitive unit array, the analogue signal processor corresponding to the columns of photosensitive unit array and view data analog-digital commutator, MUX; Row selects controller to be connected with photosensitive unit array, each row photosensitive unit is connected with corresponding analogue signal processor by column bus, analogue signal processor connects with one end of the comparator in corresponding view data analog-digital commutator, and each arithmetic unit of view data analog-digital commutator is connected with the MUX of horizontal direction.
Row selects controller to pass through to go the photosensitive unit selecting signal conduction a line, first the reset analog voltage of these photosensitive units and signal imitation voltage are placed in column bus and are then admitted to corresponding analogue signal processor, carry out resetting voltage after correlated-double-sampling process after output processing and signal voltage through analogue signal processor; The resetting voltage that analogue signal processor exports sends into an input of the comparator of corresponding view data analog-digital commutator; The other end of the ramp signal input comparator for switch back voltage that ramp signal generator produces; Along with the decline of ramp signal, enable and the low speed pulse enable two-way clock signal of the high, low speed two-way clock generating high-speed pulse that pulse signal generator produces according to ramp signal, comparator output signal and clock-signal generator, and then produce low level count pulse by high-frequency clock and the enable clock signal of high-speed pulse, high-order count pulse is produced by low-speed clock and low speed pulse enable clock signal, low level count pulse sends into low counter, and high-order count pulse sends into high-positioned counter; Low counter counts under low level counting pulse signal controls, and high-positioned counter counts under high-order counting pulse signal controls; Then carry out through analogue signal processor the input that the signal voltage after correlated-double-sampling process sends into the comparator of corresponding view data analog-digital commutator; The other end of the ramp signal input comparator for switching signal voltage that ramp signal generator produces; Along with the decline of ramp signal, enable and the low speed pulse enable two-way clock signal of the high, low speed two-way clock generating high-speed pulse that count pulse generator produces according to comparator output signal and clock-signal generator, and then produce low level count pulse by high-frequency clock and the enable clock signal of high-speed pulse, high-order count pulse is produced by low-speed clock and low speed pulse enable clock signal, low level count pulse is sent into low counter and is continued counting, and high-order count pulse is sent into high-positioned counter and continued counting; The final count value of low counter and high-positioned counter obtains the pixel image data after quantizing after internalarithmetic process; Pixel image data after each view data analog-digital commutator conversion is read into outside imageing sensor line by line by the MUX of horizontal direction.
Embodiment one
As shown in Figure 5, for adopting image data analogue-digital conversion of the present invention directly to one of implementation method that the difference of pixel reset voltage and signal voltage quantizes.In first time quantizing process, resetting voltage is placed on the input of comparator.Ramp signal, from t0, terminates to t3.The output of comparator begins turning at t1.First trailing edge of low-speed clock after comparator upset occurs in t2.First trailing edge of low-speed clock after ramp signal terminates occurs in t4. high-positioned counter and upwards counts from t2, stops counting at t4.Low counter starts upwards to count at t1 and terminates to count at t2.In second time quantizes, pixel signal voltage is placed on the input of comparator.Ramp signal, by t5, terminates in t9.First trailing edge of low-speed clock after the ramp signal for switching signal voltage starts occurs in t6. comparator and overturns at t7.First trailing edge of low-speed clock after comparator upset occurs in t8. high-positioned counter to start to continue upwards to count at t6, terminates counting at t8.Low counter starts downward counting at t7, terminates counting at t8.The final numerical value of high-positioned counter and low counter is used for the size of quantizing pixel resetting voltage and signal voltage.Suppose that N_LSB is the counting figure place of low counter, MSB is the numerical value of high-positioned counter, and LSB is the numerical value of low counter, and final quantized value is ' MSB*2
n_LSB+ LSB '.For quantization digit 8, high-frequency clock is 16 times of low-speed clock.High-positioned counter counts from ' 0000 ', and it is ' 0011 ' that counting terminates rear numerical value.Low counter counts from ' 01111 ', and it is ' 10011 ' that counting terminates rear numerical value.Then final quantized data position ' 01000011 '.Wherein the highest order of low counter is overflow protection position.
Embodiment two
Fig. 6 adopts image data analogue-digital conversion of the present invention directly to another implementation method that the difference of pixel reset voltage and signal voltage quantizes.In first time quantizing process, resetting voltage is placed on the input of comparator.Ramp signal, from t0, terminates to t4.The output that first trailing edge of low-speed clock after ramp signal starts occurs in t1. comparator begins turning at t2.First trailing edge of low-speed clock after comparator upset occurs in t3. high-positioned counter and upwards counts from t1, stops counting at t3.Low counter starts counting downwards at t2 and terminates counting at t3.In second time conversion, pixel signal voltage is placed on the input of comparator.Ramp signal, by t5, terminates in t8.Comparator overturns at t6.Low-speed clock comparator upset after first trailing edge occur in first trailing edge of t7. low-speed clock after ramp signal terminates occur in t9. high-positioned counter t7 start continue upwards count, t9 terminate counting.Low counter starts upwards to count at t6, terminates counting at t7.The final numerical value of high-positioned counter and low counter is used for the size of quantizing pixel resetting voltage and signal voltage.Suppose that N_LSB is the counting figure place of low counter, MSB is the numerical value of high-positioned counter, and LSB is the numerical value of low counter, and N is the total bit quantized, and final quantized value is ' S-(MSB*2
n_LSB+ LSB) '; Wherein S is a fixed value, can select 2 in application process
n-1, also can select other value.For quantization digit 8, high-frequency clock is 16 times of low-speed clock.High-positioned counter has, and ' 0000 ' starts counting, and it is ' 0011 ' that counting terminates rear numerical value.Low counter counts from ' 01111 ', and it is ' 10011 ' that counting terminates rear numerical value.Then final quantized data position ' 10111100 '.Wherein the highest order of low counter is overflow protection position.
Embodiment three
Fig. 7 adopts image data analogue-digital conversion of the present invention directly to another implementation method that the difference of pixel reset voltage and signal voltage quantizes.In first time quantizing process, resetting voltage is placed on the input of comparator.Ramp signal, from t0, terminates to t4.The output that first trailing edge of low-speed clock after ramp signal starts occurs in t1. comparator begins turning at t2.First trailing edge of low-speed clock after comparator upset occurs in t3. high-positioned counter downward counting from t1, stops counting at t3.Low counter starts upwards to count at t2 and terminates to count at t3.In second time conversion, pixel signal voltage is placed on the input of comparator.Ramp signal, by t5, terminates in t9.First trailing edge of low-speed clock after the ramp signal of conversion pixel signal voltage starts occurs in t6, and comparator overturns at t7.First trailing edge of low-speed clock after comparator upset occurs in t8. high-positioned counter to start to continue upwards to count at t6, terminates counting at t8.Low counter starts downward counting at t7, terminates counting at t8.The final numerical value of high-positioned counter and low counter is used for the size of quantizing pixel resetting voltage and signal voltage.Suppose that N_LSB is the counting figure place of low counter, MSB is the numerical value of high-positioned counter, and LSB is the numerical value of low counter, and final quantized value is ' MSB*2
n_LSB+ LSB '.For quantization digit 8, high-frequency clock is 16 times of low-speed clock.High-positioned counter counts by ' 1000 ', and it is ' 0011 ' that counting terminates rear numerical value.Low counter counts from ' 01111 ', and it is ' 00011 ' that counting terminates rear numerical value.Then final quantized data position ' 00110011 '.Wherein the highest order of low counter is overflow protection position.
The invention is not restricted to above-described embodiment, the difference information of other counting modes to pixel reset voltage and signal voltage can also be adopted in image data analogue-digital conversion to quantize, thus every any simple deformation of making on the claims in the present invention 1 technical scheme basis, the counting direction (upwards counting changes into counting downwards or counting downwards to change into and upwards counts) of such as change high-positioned counter and low counter, or change counter initial count and terminate counting trigger point (such as ramp signal start with terminate and start and terminate after the decline of high low-speed clock or rising edge, comparator overturns, and the decline of high low-speed clock or rising edge after comparator upset), all the invention is intended within protection range.
Claims (6)
1. an image data analogue-digital conversion, is characterized in that comprising the steps:
Step one: the pixel reset voltage exported by analogue signal processor sends into an input of comparator, sends into another input of comparator simultaneously by the ramp signal being used for switch back voltage;
Step 2: the signal that comparator is exported and at a high speed, low speed two-way clock sends into a count pulse generator, makes it produce the enable and low speed pulse enable two-way clock signal of high-speed pulse and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse is enable produces low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 3: low level count pulse is sent into low counter and counts, meanwhile, sends high-order count pulse into high-positioned counter and counts;
Step 4: the pixel signal voltage exported by analogue signal processor sends into an input of comparator, sends into another input of comparator by the ramp signal being used for switching signal voltage;
Step 5: the signal that comparator is exported and at a high speed, low speed two-way clock sends into a count pulse generator, makes it produce the enable and low speed pulse enable two-way clock signal of high-speed pulse and then produce high-order count pulse and low level count pulse two paths of signals; High-speed pulse is enable produces low level count pulse with high-frequency clock, and low speed pulse enable and low-speed clock produce high-order count pulse;
Step 6: low level count pulse is sent into low counter and counts, sends high-order count pulse into high-positioned counter and counts;
Step 7: the final count value of low counter and high-positioned counter is sent in arithmetic unit and carries out calculation process, obtain the pixel image data after quantizing.
2. image data analogue-digital conversion according to claim 1, it is characterized in that the frequency of described high-frequency clock is n times of low-speed clock frequency, n is 2
n_LSB, N_LSB is the number of significant digit of low counter.
3. image data analogue-digital conversion according to claim 2, is characterized in that:
In described step 3, high-positioned counter upwards counts under high-order count pulse controls from t2, stops counting at t4, and low counter upwards counts under low level count pulse controls from t1, terminates counting at t2; Wherein t1 is reduced to equal with resetting voltage for the voltage of the ramp signal of switch back voltage, the moment that comparator begins turning, when first trailing edge that t2 is low-speed clock after comparator upset occurs, t4 is that low-speed clock is when the trailing edge of first after the ramp signal for switch back voltage terminates occurs;
In described step 6, high-positioned counter continues upwards to count under high-order count pulse controls from t6, terminates counting at t8, and low counter starts to continue downward counting from t7 under low level count pulse controls, and terminates counting at t8; Wherein t6 is that first trailing edge of low-speed clock after the ramp signal for switching signal voltage starts is when occurring, t7 is reduced to equal with signal voltage for the ramp signal of switching signal voltage, the moment that comparator begins turning, when first trailing edge that t8 is low-speed clock after comparator upset occurs;
In described step 7, arithmetic unit utilizes formula (1) to carry out calculation process and obtains the pixel image data G after quantizing;
G＝MSB*2
N_LSB+LSB(1)
Wherein MSB is the count value of high-positioned counter, and N_LSB is effective counting figure place of low counter, and LSB is the count value of low counter.
4. image data analogue-digital conversion according to claim 2, is characterized in that:
In described step 3, high-positioned counter upwards counts under high-order count pulse controls from t1, stops counting at t3, low counter under low level count pulse controls from t2 downward counting, terminate counting at t3; Wherein t1 is that first trailing edge of low-speed clock after the ramp signal for switch back voltage starts is when occurring, t2 is reduced to equal with resetting voltage for the voltage of the ramp signal of switch back voltage, the moment that comparator begins turning, when first trailing edge that t3 is low-speed clock after comparator upset occurs;
In described step 6, high-positioned counter continues upwards to count under high-order count pulse controls from t7, terminates counting at t9, and low counter continues upwards to count from t6 under low level counting pulse signal controls, and terminates counting at t7; Wherein t6 is reduced to equal with signal voltage for the ramp signal of switching signal voltage, the moment that comparator begins turning, when first trailing edge that t7 is low-speed clock after comparator upset occurs, t9 is that low-speed clock is when the trailing edge of first after the ramp signal for switching signal voltage terminates occurs;
In described step 7, arithmetic unit utilizes formula (2) to carry out calculation process and obtains the pixel image data G after quantizing;
G＝S-(MSB*2
N_LSB+LSB)(2)
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place of low counter, and LSB is the count value of low counter; S is a fixed value.
5. image data analogue-digital conversion according to claim 2, is characterized in that:
In described step 3, high-positioned counter under high-order counting pulse signal controls from t1 downward counting, stop counting at t3, low counter upwards counts by from t2 under low level counting pulse signal controls, and terminates counting at t3; Wherein t1 is that first trailing edge of low-speed clock after the ramp signal for switch back voltage starts is when occurring, t2 is reduced to equal with resetting voltage for the voltage of the ramp signal of switch back voltage, the moment that comparator begins turning, when first trailing edge that t3 is low-speed clock after comparator upset occurs;
In described step 6, high-positioned counter continues upwards to count under high-order counting pulse signal controls from t6, terminates counting at t8, and low counter continues downward counting from t7 under low level counting pulse signal controls, and terminates counting at t8; Wherein t6 is that first trailing edge of low-speed clock after the ramp signal for switching signal voltage starts is when occurring, t7 is reduced to equal with signal voltage for the ramp signal of switching signal voltage, the moment that comparator begins turning, when first trailing edge that t8 is low-speed clock after comparator upset occurs;
In described step 7, arithmetic unit utilizes formula (3) to carry out calculation process and obtains the pixel image data G after quantizing;
G＝MSB*2
N_LSB+LSB(3)
Wherein MSB is the count value of high-positioned counter, and N_LSB is the counting figure place of low counter, and LSB is the count value of low counter.
6. one kind utilizes image data analogue-digital conversion as claimed in claim 1 to realize the analog-to-digital imageing sensor of view data, it is characterized in that comprising row selects controller, photosensitive unit array, the analogue signal processor corresponding to the columns of photosensitive unit array and view data analog-digital commutator, MUX; Described view data analog-digital commutator comprises ramp signal generator, clock-signal generator, comparator, count pulse generator, high-positioned counter, low counter and arithmetic unit; Row selects controller to be connected with photosensitive unit array, and each row photosensitive unit is connected with corresponding analogue signal processor by column bus, and analogue signal processor connects with corresponding view data analog-digital commutator; In view data analog-digital commutator, an input of comparator is connected to analogue signal processor, and another input of comparator is connected to the output of ramp signal generator; The output of comparator and the high speed of clock-signal generator, low speed two-way clock export the input being connected to count pulse generator; The low level count pulse that count pulse generator produces exports and is connected to low counter, and the high-order count pulse that count pulse generator produces is connected to high-positioned counter; The output of low counter and high-positioned counter is connected to arithmetic unit; The arithmetic unit of each view data analog-digital commutator is connected to MUX.
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| CN105262965B (en) * | 2015-10-14 | 2018-11-30 | 长春长光辰芯光电技术有限公司 | A kind of high speed analog-to-digital conversion method and device thereof for imaging sensor |
| US10340936B2 (en) * | 2015-11-06 | 2019-07-02 | Ams Sensors Belgium Bvba | Analog-to-digital conversion and method of analog-to-digital conversion |
| CN105811974A (en) * | 2016-04-15 | 2016-07-27 | 陕西源能微电子有限公司 | Energy-saving device applied to analog to digital converter |
| JP6195142B1 (en) * | 2017-01-30 | 2017-09-13 | テックポイント インクＴｅｃｈｐｏｉｎｔ，Ｉｎｃ． | AD converter and imaging device |
| CN107147859B (en) * | 2017-06-06 | 2019-10-18 | 长春长光辰芯光电技术有限公司 | A kind of high speed analog-to-digital conversion device applied in imaging sensor |
| CN108444393B (en) * | 2018-04-04 | 2020-04-03 | 合肥工业大学 | double-A/D (analog/digital) cross-scale grating displacement measuring device and method |
| CN110972518B (en) * | 2019-07-19 | 2022-12-16 | 深圳市汇顶科技股份有限公司 | Image sensor, related chip and electronic device |
| KR20220048639A (en) * | 2020-10-13 | 2022-04-20 | 에스케이하이닉스 주식회사 | Image sensor and analog to digital convertor |
| CN112511772B (en) * | 2020-10-28 | 2024-06-04 | 深圳奥辰光电科技有限公司 | Image sensor, method for enhancing linearity of image sensor and depth camera |
| WO2023039841A1 (en) * | 2021-09-17 | 2023-03-23 | 迪克创新科技有限公司 | Analog-to-digital conversion unit, related image sensor, and electronic device |
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