CN116939385A - Analog-to-digital converter, readout circuit, image sensor and analog-to-digital conversion method - Google Patents
Analog-to-digital converter, readout circuit, image sensor and analog-to-digital conversion method Download PDFInfo
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Abstract
The application is suitable for the field of analog integrated circuit design, and provides an analog-to-digital converter, a reading circuit, an image sensor and an analog-to-digital conversion method. The first ramp generation module in the analog-to-digital converter is used for providing a first ramp signal. The pixel signal quantization module is used for quantizing the pixel signal with p resolution according to the first ramp signal to generate a first quantization result. The second ramp generation module is used for providing M sections of reference ramp signals; the M-section reference ramp signals adopt modes with various resolutions and various slopes; the pixel signal quantization module is further configured to determine a target segment reference ramp signal from the M-segment reference ramp signals according to the first quantization result, and to quantize the pixel signal according to the target segment reference ramp signal with a target resolution corresponding to the target segment reference ramp signal, to generate a second quantization result. The analog-to-digital converter provided by the embodiment of the application solves the problem of low quantization speed of the existing SS ADC.
Description
Technical Field
The application belongs to the field of analog integrated circuit design, and particularly relates to an analog-to-digital converter, a reading circuit, an image sensor and an analog-to-digital conversion method.
Background
CMOS (Complementary Metal-Oxide-Semiconductor) image sensors have gradually taken the leading role in the image acquisition field by virtue of their low power consumption, low cost, etc. Another major advantage of CMOS image sensors is that they can integrate pixel arrays, amplifiers, analog-to-digital converters and even digital signal processing systems on a single chip with a high degree of integration. Among them, analog-to-Digital Converter (ADC) is an important component of a CMOS image sensor readout circuit, and can be generally classified into three types according to the types thereof: the pixel-level ADC, the column-level ADC and the chip-level ADC have good compromise on pixel filling factors, chip area, speed and power consumption, so that the column-level ADC is widely applied to the CMOS image sensor with low power consumption, high speed and high resolution.
The most widely used column-level ADC in CMOS image sensors is a monoclinic ADC (SS ADC) because it is simple in circuit, easy to implement, and consumes less chip area and power consumption by column independent circuitry. But for an SS ADC with n-bit resolution, 2 is needed to complete one quantization n The quantization speed is slow every clock period, so that the SS ADC is not suitable for use in a high frame rate, high resolution CMOS image sensor.
Disclosure of Invention
The embodiment of the application provides an analog-to-digital converter which can solve the problem of low quantization speed of the existing SS ADC.
In a first aspect, an embodiment of the present application provides an analog-to-digital converter, including a first ramp generation module, a second ramp generation module, and a pixel signal quantization module; the first slope generation module and the second slope generation module are electrically connected with the pixel signal quantization module;
the first slope generation module is used for providing a first slope signal;
the pixel signal quantization module is used for quantizing a pixel signal with p resolution according to the first ramp signal to generate a first quantization result;
the second ramp generation module is used for providing M sections of reference ramp signals;
wherein the slope of the ith section reference ramp signal in the M section reference ramp signals is less than or equal to the slope of the (i+1) th section reference ramp signal, and the ith section reference ramp signal corresponds to q i The pixel signal is quantized by resolution, and the (i+1) th segment of reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module is further configured to determine a target segment reference ramp signal from the M-segment reference ramp signals according to the first quantization result, and quantize the pixel signal according to the target segment reference ramp signal with a target resolution corresponding to the target segment reference ramp signal, to generate a second quantization result.
In a possible implementation manner of the first aspect, the second ramp generating module includes a second ramp generator and a slope adjusting module; the second slope generator is electrically connected with the pixel signal quantization module through the slope adjustment module;
the second ramp generator is used for providing a second ramp signal;
the slope adjustment module is used for generating the M sections of reference slope signals according to the second slope signals.
In a possible implementation manner of the first aspect, the slope adjustment module includes N ramp sampling capacitors and N control switches;
the N slope sampling capacitors are connected in parallel, the first end of the Nth slope sampling capacitor is electrically connected with the second slope generator, and the second end of the Nth slope sampling capacitor is electrically connected with the pixel signal quantization module; the latter (N-1) control switches are electrically connected between the first ends of two adjacent slope sampling capacitors, and the first control switch is electrically connected between the first end of the first slope sampling capacitor and a reference potential;
the slope adjustment module samples the second slope signal based on the equivalent capacitors with different capacitance values and generates the M sections of reference slope signals, and N is an integer greater than or equal to 2.
In a possible implementation manner of the first aspect, the capacitance value of the kth slope sampling capacitor satisfies the formula ck=2 k-2 C1, wherein Ck is the capacitance value of the kth slope sampling capacitor, C1 is the capacitance value of the first slope sampling capacitor, and k is an integer greater than or equal to 2 and less than or equal to N.
In a possible implementation manner of the first aspect, the second ramp generating module includes M ramp generators and a second switch module, and the second switch module includes M second switches; each of the ramp generators is electrically connected to the pixel signal quantization module through one of the second switches to provide the M-segment reference ramp signal.
In a possible implementation manner of the first aspect, the first ramp generating module includes a first ramp generator and a first switch, and the first ramp generator is electrically connected with the pixel signal quantization module through the first switch;
the first ramp generator is used for providing the first ramp signal;
the first switch is used for being switched on or off according to a first control signal; the first ramp generator is capable of providing the first ramp signal to the pixel signal quantization module when the first switch is turned on.
In a possible implementation manner of the first aspect, the pixel signal quantization module includes a comparing unit and a counting unit; the comparison unit is respectively and electrically connected with the first slope generation module, the second slope generation module and the counting unit;
the comparing unit is used for receiving the pixel signal and the first slope signal, comparing the pixel signal with the first slope signal and outputting a first comparison signal;
the comparing unit is further configured to receive the pixel signal and the target segment reference ramp signal, compare the pixel signal and the target segment reference ramp signal, and output a second comparison signal;
the counting unit is used for counting at p resolution when the comparison unit compares the pixel signal with the first ramp signal and stopping counting when the first comparison signal output by the comparison unit is inverted, so as to obtain the first quantization result;
the counting unit is used for counting the pixel signal and the target segment reference ramp signal with the target resolution when the comparison unit compares the pixel signal with the target segment reference ramp signal, and stopping counting when a second comparison signal output by the comparison unit is overturned, so that the second quantization result is obtained.
In a possible implementation manner of the first aspect, the comparing unit includes a comparator; the positive input end of the comparator is electrically connected with the first slope generation module and the second slope generation module respectively, the negative input end of the comparator is used for receiving the pixel signals, and the output end of the comparator is electrically connected with the counting unit; and/or the counting unit comprises a counter, and the counter is electrically connected with the output end of the comparator; the counter is configured to output the first quantization result and the second quantization result to obtain an actual quantization result of the pixel signal based on the first quantization result and the second quantization result.
In a possible implementation manner of the first aspect, when m=2 p When the quantization voltage range of each of the M sections of reference ramp signals isV is the quantized voltage range of the analog-to-digital converter;
when M is less than 2 p And the quantization time of each section of reference ramp signal in the M sections of reference ramp signals is the same.
In a possible implementation manner of the first aspect, when M < 2 p In this case, the quantization time of each of the M reference ramp signals is
In a possible implementation manner of the first aspect, when M < 2 p At the time of 2 of the first ramp signal p Dividing the steps into M step groups corresponding to the M sections of reference ramp signals one by one, wherein the ith step group in the M step groups corresponds to the ith section of reference ramp signals, the number of steps corresponding to the first step group to the Mth step group increases progressively, and the number s of the (i+1) th step group i+1 ＝2 t s i T is an integer greater than or equal to 0, s i Is the number of i-th step groups.
In a second aspect, an embodiment of the application provides a readout circuit comprising an analog-to-digital converter as described in any one of the preceding claims.
In a third aspect, an embodiment of the present application provides an image sensor, including the readout circuit described above.
In a possible implementation manner of the third aspect, when the analog-to-digital converter includes the slope adjustment module, the readout circuit further includes a plurality of first switches, a plurality of the slope adjustment modules, and a plurality of the pixel signal quantization modules;
the first slope generators are respectively and electrically connected with each first switch, the plurality of first switches are respectively and electrically connected with the plurality of pixel signal quantization modules in a one-to-one correspondence manner, the second slope generators are respectively and electrically connected with each slope adjustment module, and the plurality of slope adjustment modules are respectively and electrically connected with the plurality of pixel signal quantization modules in a one-to-one correspondence manner; or alternatively
When the analog-to-digital converter comprises M ramp generators, the readout circuit further comprises a plurality of first switches, a plurality of pixel signal quantization modules and a plurality of second switch modules;
the first slope generators are respectively and electrically connected with each first switch, the first switches are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner, the M slope generators are respectively and electrically connected with each second switch module, and the second switch modules are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner.
In a fourth aspect, an embodiment of the present application provides an analog-to-digital conversion method, applied to an analog-to-digital converter as set forth in any one of the preceding claims, including:
the first slope generation module outputs a first slope signal;
the pixel signal quantization module quantizes the pixel signal according to the first ramp signal with p resolution to generate a first quantization result;
the second slope generation module outputs M sections of reference slope signals;
wherein the slope of the ith section reference ramp signal in the M section reference ramp signals is less than or equal to the slope of the (i+1) th section reference ramp signal, and the ith section reference ramp signal corresponds to q i The pixel signal is quantized by resolution, and the (i+1) th segment of reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module determines a target segment reference ramp signal in the M-segment reference ramp signal according to the first quantization result, and is used for quantizing the pixel signal according to the target segment reference ramp signal and a target resolution corresponding to the target segment reference ramp signal to generate a second quantization result.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
the embodiment of the application provides an analog-to-digital converter, wherein a first slope generating module is used for providing a first slope signal. The pixel signal quantization module is used for quantizing the pixel signal with p resolution according to the first ramp signal to generate a first quantization result,the first quantization result is a p-bit digital code value, the quantization process is called a first quantization stage, and the quantization time of the first quantization stage is 2 p For a clock cycle. The second ramp generation module is used for providing M sections of reference ramp signals. Wherein the slope of the ith section of reference slope signal in the M section of reference slope signal is less than or equal to the slope of the (i+1) th section of reference slope signal, and the ith section of reference slope signal corresponds to q i Resolution, i+1st segment reference ramp signal corresponds to q i+1 Resolution, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter. The pixel signal quantization module is used for determining an ith section of reference ramp signal as a target section of reference ramp signal in the M sections of reference ramp signals according to a first quantization result, and the target resolution corresponding to the target section of reference ramp signal is q i The pixel signal quantization module is used for referencing the ramp signal according to the target segment to the target resolution q i Quantizing the pixel signal to generate a second quantized result, wherein the second quantized result is q i The digital code value of the bit refers to the quantization process as a second quantization stage, and the quantization time of the second quantization stage isAnd obtaining an actual quantized result corresponding to the pixel signal based on the first quantized result and the second quantized result in one clock period. The time required for the whole quantization process isWith a clock period of 2, the time required for the whole quantization process of the conventional SS ADC n Compared with the traditional SS ADC, the analog-to-digital converter provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter.
It will be appreciated that the advantages of the second to fourth aspects may be found in the relevant description of the first aspect and are not repeated here.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a conventional SS ADC;
FIG. 2 is a schematic diagram of the working principle of a prior art SS ADC;
FIG. 3 is a schematic diagram of the relationship between the main noise and the pixel signal in an image sensor;
fig. 4 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 7 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 8 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 9 is a schematic diagram illustrating an operation principle of an analog-to-digital converter according to another embodiment of the present application;
FIG. 10 is a schematic diagram illustrating a quantization process of an analog-to-digital converter according to another embodiment of the present application;
Fig. 11 is a schematic diagram illustrating an operation principle of an analog-to-digital converter according to another embodiment of the present application;
fig. 12 is a schematic diagram of a quantization process of an analog-to-digital converter according to another embodiment of the present application.
10. A first ramp generation module; 101. a first ramp generator; 102. a first switch; 20. a second ramp generation module; 201. a second ramp generator; 202. a slope adjustment module; 203. a ramp generator; 204. a second switch module; 2041. a second switch; 30. a pixel signal quantization module; 301. a comparison unit; 302. and a counting unit.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted in context as "when …" or "upon" or "in response to a determination" or "in response to detection. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Fig. 1 is a schematic circuit diagram of a conventional SS ADC, and fig. 2 is a schematic operation principle of the conventional SS ADC. As shown in fig. 1 and 2, the ramp generator generates a ramp signal Vrampi, the positive input terminal of the comparator receives the ramp signal Vrampi, and the negative input terminal of the comparator receives the pixel signal Vin; the ramp signal Vrampi traverses the whole quantization voltage range and is compared with the pixel signal Vin, the counter starts to count, when the ramp signal Vrampi is larger than the pixel signal Vin, the comparator turns over, the counter stops counting, and the counting result is the digital code value of the quantized pixel signal Vin.
From the above description, for an SS ADC with n-bit resolution, 2 is required to complete one quantization n The quantization speed is slow every clock period, so that the SS ADC is not suitable for use in a high frame rate, high resolution CMOS image sensor.
There are two main sources of noise in image sensors: one is the shot noise of photons, which is equal to the square root of the number of electrons in a pixel; the other is quantization noise, which is lower the higher the resolution of the analog-to-digital converter. The relationship between the main noise and the pixel signal in the image sensor can be represented by fig. 3, and it can be seen from fig. 3: in dark light, shot noise is small, and quantization noise plays a leading role; in strong light, shot noise is dominant gradually, and the influence of quantization noise is smaller gradually, at this time, the requirement for the resolution of the analog-to-digital converter is reduced, so that the resolution of the analog-to-digital converter can be switched to improve the quantization speed while reducing the power consumption in consideration of the increase in illumination.
Based on the above-described problems, an embodiment of the present application provides an analog-to-digital converter, which includes a first ramp generation module 10, a second ramp generation module 20, and a pixel signal quantization module 30, as shown in fig. 4. The first ramp generation module 10 and the second ramp generation module 20 are both electrically connected to the pixel signal quantization module 30.
Specifically, the first ramp generating module 10 is configured to provide a first ramp signal Vcoarse, which is a linear ramp signal with a certain slope.
The pixel signal quantization module 30 is configured to quantize the pixel signal Vin with a resolution p according to the first ramp signal, and generate a first quantization result. The first quantization result is a p-bit digital code value, the quantization process is called a first quantization stage, the first quantization stage corresponds to a coarse quantization stage in the prior art, and the quantization time of the first quantization stage is 2 p For a clock cycle.
The second ramp generation module 20 is used to provide an M-segment reference ramp signal. Wherein the slope of the ith section of reference slope signal in the M section of reference slope signal is less than or equal to the slope of the (i+1) th section of reference slope signal, and the ith section of reference slope signal corresponds to q i The resolution quantizes the pixel signal Vin, and the (i+1) th stage reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal Vin, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter.
The pixel signal quantization module 30 is configured to determine, according to the first quantization result, an i-th reference ramp signal vramp_i as a target-segment reference ramp signal, where the target resolution corresponding to the target-segment reference ramp signal vramp_i is q i 。
The pixel signal quantization module 30 is used for providing the target resolution q according to the target segment reference ramp signal Vramp_i i The pixel signal Vin is quantized to generate a second quantization result. The second quantization result is q i The digital code value of the bit refers to the quantization process as the second quantization stage, and the second quantization stage corresponds to the prior artA fine quantization stage in operation, wherein the quantization time of the second quantization stage isFor a clock cycle. And obtaining an actual quantized result corresponding to the pixel signal Vin based on the first quantized result and the second quantized result.
The time required for the whole quantization process isWith a clock period of 2, the time required for the whole quantization process of the conventional SS ADC n Compared with the traditional SS ADC, the analog-to-digital converter provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter.
Note that the quantization referred to in the pixel signal quantization module 30 includes a comparison process and a counting process. The quantization referred to in describing the reference ramp signal includes only a comparison process. Those skilled in the art can operate as the case may be.
As shown in fig. 5, the second ramp generation module 20 includes a second ramp generator 201 and a slope adjustment module 202. The second ramp generator 201 is electrically connected to the pixel signal quantization module 30 through the slope adjustment module 202.
Specifically, the second ramp generator 201 is configured to provide a second ramp signal Vramp, which is a linear ramp signal having a certain slope.
The slope adjustment module 202 is configured to generate an M-segment reference ramp signal according to the second ramp signal Vramp.
Compared with the method of generating a plurality of reference ramp signals by using a plurality of ramp generators, the slope adjustment module 202 in the application can generate M sections of reference ramp signals according to the second ramp signal Vramp, so that the number of ramp generators is reduced, the M sections of reference ramp signals can be generated by only one ramp generator, the chip area is saved, and the power consumption is reduced.
It should be noted that, a designer may set a specific value of the slope of the second ramp signal Vramp generated by the second ramp generator 202 according to actual requirements.
As shown in FIG. 5, the slope adjustment module 202 includes N ramp sampling capacitances C1-CN and N control switches S1-SN. The N ramp sampling capacitors C1-CN are connected in parallel, and a first end of the nth ramp sampling capacitor CN is electrically connected with the second ramp generator 201, and a second end of the nth ramp sampling capacitor CN is electrically connected with the pixel signal quantization module 30. The latter (N-1) control switches S2-SN are electrically connected between the first ends of the adjacent two ramp sampling capacitors, the first control switch S1 being electrically connected between the first end of the first ramp sampling capacitor C1 and the reference potential. The N control switches S1-SN are configured to form equivalent capacitors with different capacitance values according to the first quantization result, where the slope adjustment module 202 samples the second ramp signal Vramp based on the equivalent capacitors with different capacitance values, and generates M reference ramp signals, where N is an integer greater than or equal to 2.
It should be noted that, in practical applications, the reference potential may be selected as the ground potential, that is, the first control switch S1 is connected between the first end of the first slope sampling capacitor C1 and the ground potential.
Specifically, the N control switches S1-SN are used to form equivalent capacitors with different capacitance values according to the first quantization result, and the process is as follows:
In the first stage, the control switch S1 is closed, the control switch S2 is opened, the rest control switches S3-SN are closed, the equivalent capacitance formed after the slope sampling capacitors C2-CN are connected in parallel is connected with the first slope sampling C1 in series, the second slope signal Vramp is sampled by taking the formed equivalent capacitance as the sampling capacitance, the 1 st section reference slope signal is obtained, and the slope of the 1 st section reference slope signal is marked as K1.
In the second stage, the control switches S1-S2 are closed, the control switch S3 is opened, the rest control switches S4-SN are closed, namely the slope sampling capacitors C3-CN are connected in parallel, the slope sampling capacitors C1-C2 are connected in parallel, the parallel connection of the slope sampling capacitors C1-C2 are connected in series, an equivalent capacitor is formed and used as a sampling capacitor to sample the second slope signal Vramp, the 2 nd reference slope signal is obtained, the slope of the 2 nd reference slope signal is marked as K2, and K1 is smaller than K2.
In the third stage, the control switches S1-S3 are closed, the control switch S4 is opened, the rest control switches S5-SN are closed, namely the slope sampling capacitors C4-CN are connected in parallel, the slope sampling capacitors C1-C3 are connected in parallel, the two parallel connection capacitors are connected in series to form an equivalent capacitor as a sampling capacitor to sample a second slope signal Vramp, a 3 rd reference slope signal is obtained, the slope of the 3 rd reference slope signal is recorded as K3, and K2 is smaller than K3;
And the like, obtaining M sections of reference ramp signals, wherein M and N are in one-to-one correspondence.
It should be noted that, as will be understood by those skilled in the art, in the process of forming the reference ramp signal in the mth segment, the control switch S1 needs to be opened, and the remaining control switches S2-SN need to be closed, which is equivalent to connecting the ramp sampling capacitors C1-CN in parallel, so as to form an equivalent capacitor as a sampling capacitor to sample the second ramp signal Vramp. Wherein the sampling of the second ramp signal Vramp is based on sampling at the same point.
Furthermore, if the slopes of the M sections of reference slope signals are equal, the slopes of the M sections of reference slope signals can be equal only by adjusting the control switches of each stage to be consistent.
Further, if the slope of the i-th reference ramp signal in the M-th reference ramp signal is smaller than the slope of the i+1-th reference ramp signal, the capacitance of the k-th ramp sampling capacitor is made to satisfy the formula ck=2 k-2 C1, wherein Ck is the capacitance of the kth slope sampling capacitor, C1 is the capacitance of the first slope sampling capacitor, and k is an integer greater than or equal to 2 and less than or equal to N.
As shown in fig. 6, the second ramp generating module 20 includes M ramp generators 203 and a second switching module 204. The second switch module 204 includes M second switches 2041. Each ramp generator 203 is electrically connected to the pixel signal quantization module 30 through a second switch 2041 to provide M segments of reference ramp signals vramp_1, vramp_2, …, vramp_m.
Specifically, M second switches 2041 in the second switch module 204 are used to turn on or off according to the first quantization result to determine the target segment reference ramp signal vramp_i in the M segments reference ramp signals.
For example, when the second switch module 204 receives the first quantization result, the first quantization result controls the i-th second switch 2041 of the M second switches 2041 to be closed, and the rest of the second switches 2041 to be opened, and provides the i-th segment reference ramp signal vramp_i generated by the i-th ramp generator 203 to the pixel signal quantization module 30, the i-th segment reference ramp signal vramp_i is the target segment reference ramp signal.
As shown in fig. 4, 5 and 6, the first ramp generating module 10 includes a first ramp generator 101 and a first switch 102. The first ramp generator 101 is electrically connected to the pixel signal quantization module 30 through a first switch 102.
Specifically, the first ramp generator 101 is configured to provide a first ramp signal Vcoarse.
The first switch 102 is used for being turned on or off according to a first control signal. When the first switch 102 is turned on, the first ramp generator 101 can provide the first ramp signal Vcoarse to the pixel signal quantization module 30, so that the pixel signal quantization module 30 is configured to quantize the pixel signal Vin with a p resolution according to the first ramp signal Vcoarse, and generate a first quantization result.
It should be noted that, a designer may set a specific value of the slope of the first ramp signal Vcoarse generated by the first ramp generator 101 according to actual requirements. The first control signal may be generated by a controller electrically connected to the analog-to-digital converter.
As shown in fig. 4, the pixel signal quantization module 30 includes a comparison unit 301 and a counting unit 302. The comparing unit 301 is electrically connected to the first ramp generating module 10, the second ramp generating module 20 and the counting unit 302, respectively.
Specifically, the comparing unit 301 in the pixel signal quantizing module 30 receives the first ramp signal Vcoarse and the pixel signal Vin, compares the first ramp signal Vcoarse with the pixel signal Vin, and outputs a first comparison signal, at this time, the counting unit 302 starts counting the upper p bits, and when the first comparison signal output by the comparing unit 301 is inverted, the counting unit 302 stops counting to obtain a first quantized result, where the first quantized result is a p-bit numerical code value. Pixel signal quantization module30 determining an i-th segment reference ramp signal Vramp_i as a target segment reference ramp signal in the M-segment reference ramp signals according to the first quantization result, wherein the target resolution corresponding to the target segment reference ramp signal Vramp_i is q i The comparing unit 301 in the pixel signal quantizing module 30 receives the target segment reference ramp signal vramp_i and the pixel signal Vin, compares the target segment reference ramp signal vramp_i and the pixel signal Vin, and outputs a second comparison signal, at which time the counting unit 302 is low q i The bit starts counting, and when the second comparison signal output by the comparison unit 301 is inverted, the counting unit 302 stops counting to obtain a second quantization result, wherein the second quantization result is q i And obtaining an actual quantized result corresponding to the pixel signal Vin based on the first quantized result and the second quantized result by the numerical code value of the bit.
When the first ramp signal Vcoarse does not reach the pixel signal Vin, the first comparison signal output by the comparison unit 301 is at a low level. When the first ramp signal Vcoarse reaches the pixel signal Vin, the first comparison signal is inverted, and the first comparison signal output by the comparison unit 301 becomes a high level.
Similarly, when the target segment reference ramp signal vramp_i does not reach the pixel signal Vin, the second comparison signal output by the comparison unit 301 is at a low level. When the target segment reference ramp signal vramp_i reaches the pixel signal Vin, the second comparison signal is inverted, and the second comparison signal output from the comparison unit 301 becomes a high level.
As shown in fig. 4, the comparison unit 301 includes a comparator. The positive input end of the comparator is electrically connected with the first slope generating module 10 and the second slope generating module 20 respectively, and is used for receiving the first slope signal Vcoarse and the target segment reference slope signal Vramp_i, the negative input end of the comparator is used for receiving the pixel signal Vin, and the output end of the comparator is electrically connected with the counting unit 302 and is used for outputting a first comparison signal and a second comparison signal to indicate the operation of the counting unit 302.
The counting unit 302 includes a counter. The counter is electrically connected with the output end of the comparator. The counter is used for counting when the comparator starts to compare, stopping counting when the result output by the comparator is overturned, and finally outputting a first quantized result and a second quantized result to obtain an actual quantized result of the pixel signal Vin based on the first quantized result and the second quantized result.
Based on the above description, when m=2 p When the quantization voltage range of each of the M sections of reference ramp signals isV is the quantization voltage range of the analog-to-digital converter.
When M is less than 2 p And the quantization time of each section of reference ramp signal in the M sections of reference ramp signals is the same.
Further, as shown in fig. 9, when m=2 p When the first ramp signal Vcoarse divides the quantization voltage range of the analog-to-digital converter into 2 p Each step corresponds to a section of reference ramp signal, and the quantization range of each section of reference ramp signal is equal to one step height of the first ramp signal Vcoarse.
For a two-step multi-ramp ADC, assuming that it is coarsely quantized to p bits and finely quantized to q bits, it takes a time of (2 p +2 q ) For a clock cycle. As described above, the resolution of the M-segment reference ramp signal generated in the embodiment of the present application may be different, and according to the relationship between shot noise and quantization noise that varies with light intensity, the resolution of the analog-to-digital converter is properly reduced when the pixel signal is large and shot noise is dominant, so as to further increase the quantization speed and reduce the power consumption. Since the quantization range of each segment of the reference ramp signal is equal to the entire quantization rangeTherefore, the analog-to-digital converter provided by the embodiment of the application takes a time of +.>
In practical application, the distribution mode of the reference ramp signal and the sub-slope can be flexibly selected according to requirements of imaging quality, frame rate, chip area, power consumption and the like. As the number of the reference ramp signals is the power exponent of the resolution of the first quantization stage, the number of the ramp generators increases exponentially along with the increase of the resolution of the first quantization stage, and the chip area and the power consumption can be increased, the resolution of the first quantization stage is generally selected to be 2-3 bits, the resolution of the second quantization stage is not lower than 6 bits at the lowest, the resolution of the whole analog-digital converter is not lower than 8-9 bits at the lowest under strong light, and the serious reduction of the image quality can not be caused while the quantization speed is improved.
Further, when M < 2 p In this case, the quantization time of each of the M reference ramp signals is the same, and the quantization time isAs shown in fig. 11, the first ramp signal Vcoarse is 2 p The steps are divided into M step groups corresponding to the M sections of reference slope signals one by one, wherein the ith step group in the M step groups corresponds to the ith section of reference slope signal, the number of steps corresponding to the first step group to the Mth step group increases progressively, and the number s of the (i+1) th step group i+1 ＝2 t s i T is an integer greater than or equal to 0, s i Is the number of i-th step groups.
For a two-step multi-ramp ADC, assuming that it is coarsely quantized to p bits and finely quantized to q bits, it requires (2 p +1) ramp generators, the time required to complete one quantization is (2) p +2 q ) For a clock cycle. The analog-to-digital converter provided by the embodiment of the application properly reduces the resolution of the reference ramp signal based on the characteristic that shot noise and quantization noise change along with the light intensity under the strong light condition, namely when the pixel signal is larger, can have a larger quantization range within the same quantization time, and reduces the number of the reference ramp signals, namely when the analog-to-digital converter comprises the ramp generators, the number of the ramp generators can be reduced.
In practical application, the resolution of the first quantization stage and the distribution mode of the slope of the reference ramp signal can be flexibly selected according to requirements of imaging quality, frame rate, chip area, power consumption and the like. The analog-to-digital converter provided by the embodiment of the application overcomes the defects of large chip area and large power consumption of the traditional two-step multi-slope ADC, so that the resolution of the first quantization stage can be expanded, for example, the resolution of the first quantization stage is 3-5 bits, the resolution of the second quantization stage is least not lower than 5 bits, the resolution of the whole analog-to-digital converter is ensured to be least lower than 8-10 bits under strong light, and the serious degradation of the image quality is not caused while the quantization speed is improved.
The embodiment of the application also provides a readout circuit, which comprises the analog-to-digital converter. The analog-to-digital converter in the readout circuit divides the quantization process into a first quantization stage and a second quantization stage, the first quantization stage: the first ramp generating module 10 is configured to provide a first ramp signal Vcoarse, the pixel signal quantizing module 30 is configured to quantize the pixel signal Vin according to the first ramp signal with p resolution, generate a first quantized result, the first quantized result is a p-bit digital code value, and the quantization time of the first quantized stage is 2 p For a clock cycle. A second quantization stage: the second ramp generating module 20 is configured to provide an M-segment reference ramp signal, where a slope of an i-th segment reference ramp signal in the M-segment reference ramp signal is less than or equal to a slope of an i+1th segment reference ramp signal, and the i-th segment reference ramp signal corresponds to q i The resolution quantizes the pixel signal Vin, and the (i+1) th stage reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal Vin, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter. The pixel signal quantization module 30 is configured to determine, according to the first quantization result, an i-th reference ramp signal vramp_i as a target-segment reference ramp signal, where the target resolution corresponding to the target-segment reference ramp signal vramp_i is q i . The pixel signal quantization module 30 is used for providing the target resolution q according to the target segment reference ramp signal Vramp_i i Quantizing the pixel signal Vin to generate a second quantized result, wherein the second quantized result is q i Number of bitsWord code value, quantization time of the second quantization stage isAnd obtaining an actual quantized result of the pixel signal Vin based on the first quantized result and the second quantized result by one clock period. The time required for the whole quantization process is +. >With a clock period of 2, the time required for the whole quantization process of the conventional readout circuit n Compared with the traditional readout circuit, the readout circuit provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter.
The embodiment of the application also provides an image sensor, which comprises the readout circuit.
Further, as shown in fig. 7, when the analog-to-digital converter includes the slope adjustment module 202, the readout circuit further includes a plurality of first switches 102, a plurality of slope adjustment modules 202, and a plurality of pixel signal quantization modules 30. The first slope generator 101 is electrically connected to each first switch 102, the plurality of first switches 102 are electrically connected to the plurality of pixel signal quantization modules 30 in a one-to-one correspondence, the second slope generator 201 is electrically connected to each slope adjustment module 202, and the plurality of slope adjustment modules 202 are electrically connected to the plurality of pixel signal quantization modules 30 in a one-to-one correspondence.
Further, as shown in fig. 8, when the analog-to-digital converter includes M ramp generators 203, the readout circuit further includes a plurality of first switches 102, a plurality of pixel signal quantization modules 30, and a plurality of second switch modules 204. The first ramp generator 101 is electrically connected to each first switch 102, the first switches 102 are electrically connected to the pixel signal quantization modules 30 in a one-to-one correspondence, the M ramp generators 203 are electrically connected to each second switch module 204, and the second switch modules 204 are electrically connected to the pixel signal quantization modules 30 in a one-to-one correspondence.
The image sensor provided by the embodiment of the application has the characteristics of high quantization speed and low power consumption, and the specific working principle is described with reference to the readout circuit and the working principle of the analog-to-digital converter, and is not repeated here.
The embodiment of the application also provides an analog-to-digital conversion method which is applied to the analog-to-digital converter described in any one of the above, and comprises the following steps:
s1, the first ramp generating module 10 outputs a first ramp signal Vcoarse.
Specifically, the first ramp signal Vcoarse is a linear ramp signal with a certain slope, and the value of the slope can be set according to actual requirements.
S2, the pixel signal quantization module 30 quantizes the pixel signal Vin according to the first ramp signal Vcoarse with a p resolution, and generates a first quantization result.
Specifically, the first quantization result is a p-bit digital code value, and the quantization process is referred to as a first quantization stage, where the quantization time of the first quantization stage is 2 p For a clock cycle.
S3, the second slope generation module 20 outputs M sections of reference slope signals;
wherein the slope of the ith section of reference slope signal in the M section of reference slope signal is less than or equal to the slope of the (i+1) th section of reference slope signal, and the ith section of reference slope signal corresponds to q i The resolution quantizes the pixel signal Vin, and the (i+1) th stage reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal Vin, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter.
S4, the pixel signal quantization module 30 determines an i-th section reference ramp signal Vramp_i as a target section reference ramp signal in the M-section reference ramp signals according to the first quantization result, and the target resolution corresponding to the target section reference ramp signal Vramp_i is q i 。
S5, the pixel signal quantization module 30 uses the target resolution q according to the target segment reference ramp signal Vramp_i i The pixel signal Vin is quantized to generate a second quantization result.
Specifically, the second quantization result is q i The digital code value of the bit refers to the quantization process as a second quantization stage, and the quantization time of the second quantization stage isFor a clock cycle. And obtaining an actual quantized result corresponding to the pixel signal Vin based on the first quantized result and the second quantized result.
The time required for the whole quantization process isWith a clock period of 2, the time required for the whole quantization process of the conventional SS ADC n Compared with the traditional SS ADC, the analog-to-digital converter provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter.
Example 1
Setting the highest resolution n of the analog-to-digital converter to 12 bits, the resolution p of the first quantization stage to 2 bits, let m=2 p The resolution corresponding to the m=4, 4 segments of reference ramp signals is 10 bits, 9 bits, 8 bits, respectively. Meanwhile, it is assumed that the pixel signal Vin to be quantized is within the third step range of the first ramp signal Vcoarse, as shown in fig. 10.
First, the first quantization stage is performed, the upper 2 bits of the counter start counting, the output of the comparator is flipped when the first ramp signal Vcoarse runs to the third step, at which time the counter stops counting, and the upper 2 bits of the counter store the first quantization result. Then enter the second quantization stage, feed back the first quantization result stored in the upper 2 bits to the corresponding switch of the slope adjustment module 202 or the corresponding switch of the second switch module 204, control the corresponding switch to connect the 3 rd segment reference ramp signal vramp_3 to the comparator, then compare the 3 rd segment reference ramp signal vramp_3 with the pixel signal Vin, and start counting the lower 9 bits of the counter. Until the 3 rd stage reference ramp signal Vramp_3 and the pixel signal Vin are equal, the output of the comparator is reversed, the counter stops counting, and the lower 9 bits of the counter are stored And a second quantization result. And combining the first quantization result and the second quantization result into an 11-bit digital code, thus finishing the quantization process. The time required for the whole quantization process is: 2 2 +2 9 =516 clock cycles. If a conventional SS ADC is used, the time required to complete an 11bit quantization is: 2 11 =2048 clock cycles. Therefore, the quantization time required by the analog-to-digital converter provided by the embodiment of the application is only about 1/4 of that of the traditional SS ADC. Compared with the two-step multi-slope ADC, the analog-to-digital converter provided by the embodiment of the application properly reduces the resolution of the analog-to-digital converter when the large pixel signal is quantized, and improves the speed when the large pixel signal is quantized. Assuming that the two-step multi-ramp ADC adopts a 2-bit coarse quantization and a 10-bit fine quantization mode, the average time required for completing one quantization is 2 2 +2 10 =1028 clock cycles; the analog-to-digital converter provided by the embodiment of the application has the average time required for completing one quantization ofThe quantization speed of the two-step multi-slope ADC is improved by about 31% compared with the quantization speed of the two-step multi-slope ADC, and the corresponding power consumption is reduced in an equal proportion.
Example two
Setting the highest resolution n of the analog-to-digital converter to 12 bits, setting the resolution p of the first quantization stage to 3 bits, with M < 2 p The resolutions corresponding to the reference ramp signals of the m=4 and the 4 segments are 9bit, 8bit and 7bit respectively, meanwhile, the pixel signal Vin to be quantized is assumed to be larger and falls in the reference ramp range of the 4 th segment, as shown in fig. 12.
First, the first quantization stage is performed, the upper 3 bits of the counter start counting, the output of the comparator is flipped when the first ramp signal Vcoarse runs to the 6 th step, at this time, the counter stops counting, and the upper 3 bits of the counter store the first quantization result. Then proceed to the second quantization stage where the reference ramp signal with lower resolution is selected for quantization because the quantized pixel signal is larger. Feeding back the first quantized result stored in the upper 3 bits to the switch corresponding to the slope adjustment module 202 or the switch corresponding to the second switch module 204And controlling a corresponding switch to connect the 4 th section reference ramp signal Vramp_4 to the comparator, comparing the 4 th section reference ramp signal Vramp_4 with the pixel signal Vin, and starting counting by 7 bits below the counter. Until the 4 th stage reference ramp signal vramp_4 and the pixel signal Vin are equal, the output of the comparator is flipped, the counter stops counting, and the lower 7 bits of the counter store the second quantization result. And combining the first quantization result and the second quantization result into a 10-bit digital code, thus finishing the quantization process. The time required for the whole quantization process is: (2 3 +2 7 ) =136 clock cycles; if the conventional SS ADC is adopted, the time required for completing the 10bit quantization once is: 2 10 =1024 clock cycles. The quantization time required for the analog-to-digital converter provided by the embodiment of the application is reduced by about 87% compared with that of the conventional SS ADC. Compared with the two-step multi-slope ADC, the analog-to-digital converter provided by the embodiment of the application properly reduces the resolution of the analog-to-digital converter when quantizing large pixel signals, improves the quantization speed and reduces the number of reference slope signals.
Assuming that the two-step multi-ramp ADC uses the same 3-bit coarse quantization, 9-bit fine quantization, it requires a number of ramp generators of (2 3 +1) =9, and the application requires a maximum of 5 ramp generators and a minimum of 2 ramp generators, thereby achieving the effects of reducing the chip area and reducing the power consumption.
In summary, in the analog-to-digital converter provided by the embodiment of the application, the quantization process is divided into the first quantization stage and the second quantization stage, the M-segment reference ramp signal is provided in the second quantization stage, and the M-segment reference ramp signal is set as a multi-slope and multi-resolution ramp signal, so that the resolution of the analog-to-digital converter is adjusted under the condition of strong light, the quantization speed is improved, and the power consumption is reduced.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (15)
1. The analog-to-digital converter is characterized by comprising a first slope generation module, a second slope generation module and a pixel signal quantization module; the first slope generation module and the second slope generation module are electrically connected with the pixel signal quantization module;
the first slope generation module is used for providing a first slope signal;
the pixel signal quantization module is used for quantizing a pixel signal with p resolution according to the first ramp signal to generate a first quantization result;
The second ramp generation module is used for providing M sections of reference ramp signals;
wherein the slope of the ith section reference ramp signal in the M section reference ramp signals is less than or equal to the slope of the (i+1) th section reference ramp signal, and the ith section reference ramp signal corresponds to q i The pixel signal is quantized by resolution, and the (i+1) th segment of reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal, q i ≥q i+1 ，q 1 +p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module is further configured to determine a target segment reference ramp signal from the M-segment reference ramp signals according to the first quantization result, and quantize the pixel signal according to the target segment reference ramp signal with a target resolution corresponding to the target segment reference ramp signal, to generate a second quantization result.
2. The analog-to-digital converter of claim 1, wherein said second ramp generation module comprises a second ramp generator and a slope adjustment module; the second slope generator is electrically connected with the pixel signal quantization module through the slope adjustment module;
the second ramp generator is used for providing a second ramp signal;
The slope adjustment module is used for generating the M sections of reference slope signals according to the second slope signals.
3. The analog-to-digital converter of claim 2, wherein said slope adjustment module includes N ramp sampling capacitors and N control switches;
the N slope sampling capacitors are connected in parallel, the first end of the Nth slope sampling capacitor is electrically connected with the second slope generator, and the second end of the Nth slope sampling capacitor is electrically connected with the pixel signal quantization module; the latter (N-1) control switches are electrically connected between the first ends of two adjacent slope sampling capacitors, and the first control switch is electrically connected between the first end of the first slope sampling capacitor and a reference potential;
the slope adjustment module samples the second slope signal based on the equivalent capacitors with different capacitance values and generates the M sections of reference slope signals, and N is an integer greater than or equal to 2.
4. An analog to digital converter as claimed in claim 3, in which the capacitance of the kth said ramp sampling capacitor satisfies the formula ck=2 k-2 C1, wherein Ck is the capacitance value of the kth slope sampling capacitor, C1 is the capacitance value of the first slope sampling capacitor, and k is an integer greater than or equal to 2 and less than or equal to N.
5. The analog-to-digital converter of claim 1, wherein the second ramp generation module comprises M ramp generators and a second switch module comprising M second switches; each of the ramp generators is electrically connected to the pixel signal quantization module through one of the second switches to provide the M-segment reference ramp signal.
6. The analog-to-digital converter of claim 1, wherein the first ramp generation module comprises a first ramp generator and a first switch, the first ramp generator being electrically connected to the pixel signal quantization module through the first switch;
the first ramp generator is used for providing the first ramp signal;
the first switch is used for being switched on or off according to a first control signal; the first ramp generator is capable of providing the first ramp signal to the pixel signal quantization module when the first switch is turned on.
7. The analog-to-digital converter of claim 1, wherein said pixel signal quantization module comprises a comparison unit and a counting unit; the comparison unit is respectively and electrically connected with the first slope generation module, the second slope generation module and the counting unit;
The comparing unit is used for receiving the pixel signal and the first slope signal, comparing the pixel signal with the first slope signal and outputting a first comparison signal;
the comparing unit is further configured to receive the pixel signal and the target segment reference ramp signal, compare the pixel signal and the target segment reference ramp signal, and output a second comparison signal;
the counting unit is used for counting at p resolution when the comparison unit compares the pixel signal with the first ramp signal and stopping counting when the first comparison signal output by the comparison unit is inverted, so as to obtain the first quantization result;
the counting unit is used for counting the pixel signal and the target segment reference ramp signal with the target resolution when the comparison unit compares the pixel signal with the target segment reference ramp signal, and stopping counting when a second comparison signal output by the comparison unit is overturned, so that the second quantization result is obtained.
8. The analog-to-digital converter of claim 7, wherein said comparing unit comprises a comparator; the positive input end of the comparator is electrically connected with the first slope generation module and the second slope generation module respectively, the negative input end of the comparator is used for receiving the pixel signals, and the output end of the comparator is electrically connected with the counting unit; and/or the counting unit comprises a counter, and the counter is electrically connected with the output end of the comparator; the counter is configured to output the first quantization result and the second quantization result to obtain an actual quantization result of the pixel signal based on the first quantization result and the second quantization result.
9. An analog-to-digital converter as claimed in any one of claims 1 to 8, wherein when M = 2 P When the quantization voltage range of each of the M sections of reference ramp signals isV is the quantized voltage range of the analog-to-digital converter;
when M is less than 2 p And the quantization time of each section of reference ramp signal in the M sections of reference ramp signals is the same.
10. An analog to digital converter as claimed in claim 9, in which when M < 2 p In this case, the quantization time of each of the M reference ramp signals is
11. An analog to digital converter as claimed in claim 9, in whichIn that when M < 2 p At the time of 2 of the first ramp signal p Dividing the steps into M step groups corresponding to the M sections of reference ramp signals one by one, wherein the ith step group in the M step groups corresponds to the ith section of reference ramp signals, the number of steps corresponding to the first step group to the Mth step group increases progressively, and the number s of the (i+1) th step group i+1 ＝2 t s i T is an integer greater than or equal to 0, s i Is the number of i-th step groups.
12. A readout circuit comprising an analog-to-digital converter as claimed in any one of claims 1 to 11.
13. An image sensor comprising the readout circuit of claim 12.
14. The image sensor of claim 13, wherein when the analog-to-digital converter includes the slope adjustment module, the readout circuit further includes a plurality of first switches, a plurality of the slope adjustment modules, and a plurality of the pixel signal quantization modules;
the first slope generators are respectively and electrically connected with each first switch, the plurality of first switches are respectively and electrically connected with the plurality of pixel signal quantization modules in a one-to-one correspondence manner, the second slope generators are respectively and electrically connected with each slope adjustment module, and the plurality of slope adjustment modules are respectively and electrically connected with the plurality of pixel signal quantization modules in a one-to-one correspondence manner; or alternatively
When the analog-to-digital converter comprises M ramp generators, the readout circuit further comprises a plurality of first switches, a plurality of pixel signal quantization modules and a plurality of second switch modules;
the first slope generators are respectively and electrically connected with each first switch, the first switches are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner, the M slope generators are respectively and electrically connected with each second switch module, and the second switch modules are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner.
15. An analog-to-digital conversion method applied to an analog-to-digital converter according to any one of claims 1-11, comprising:
the first slope generation module outputs a first slope signal;
the pixel signal quantization module quantizes the pixel signal according to the first ramp signal with p resolution to generate a first quantization result;
the second slope generation module outputs M sections of reference slope signals;
wherein the slope of the ith section reference ramp signal in the M section reference ramp signals is less than or equal to the slope of the (i+1) th section reference ramp signal, and the ith section reference ramp signal corresponds to q i The pixel signal is quantized by resolution, and the (i+1) th segment of reference ramp signal corresponds to q i+1 Resolution quantizes the pixel signal, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module determines a target segment reference ramp signal in the M-segment reference ramp signal according to the first quantization result, and is used for quantizing the pixel signal according to the target segment reference ramp signal and a target resolution corresponding to the target segment reference ramp signal to generate a second quantization result.
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| CN117713835B (en) * | 2024-02-05 | 2024-04-26 | 安徽大学 | Two-step column-level low-noise CIS analog-to-digital converter and CIS chip |
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