CN217307783U - Analog-to-digital converter, readout circuit and image sensor - Google Patents
Analog-to-digital converter, readout circuit and image sensor Download PDFInfo
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Abstract
The application is suitable for the field of design of analog integrated circuits, and provides an analog-to-digital converter, a reading circuit and an image sensor. A first ramp generation module in the analog-to-digital converter is used for providing a first ramp signal. The pixel signal quantization module is used for quantizing the pixel signal with p resolution according to the first ramp signal and generating a first quantization result. The second ramp generation module is used for providing M sections of reference ramp signals, wherein the M sections of reference ramp signals adopt modes of various resolutions and various slopes; the pixel signal quantization module is further configured to determine a target segment reference ramp signal from the M segment reference ramp signals according to the first quantization result, and quantize the pixel signal at a target resolution corresponding to the target segment reference ramp signal according to the target segment reference ramp signal to generate a second quantization result. The analog-to-digital converter provided by the embodiment of the application solves the problem that the existing SS ADC is slow in quantization speed.
Description
Technical Field
The application belongs to the field of analog integrated circuit design, and particularly relates to an analog-to-digital converter, a reading circuit and an image sensor.
Background
A Complementary Metal-Oxide-Semiconductor (CMOS) image sensor has gradually occupied a leading position in the field of image acquisition due to its advantages of low power consumption, low cost, and the like. Another major advantage of the CMOS image sensor is that it can integrate a pixel array, an amplifier, an analog-to-digital converter, and even a digital signal processing system on one chip, and has a high integration level. Analog-to-Digital Converter (ADC) is an important component of the readout circuit of the CMOS image sensor, and can be generally classified into three categories according to its type: the CMOS image sensor comprises a pixel-level ADC, a column-level ADC and a chip-level ADC, wherein the column-level ADC makes good compromise on pixel fill factor, chip area, speed and power consumption, so that the CMOS image sensor is widely applied to low-power-consumption, high-speed and high-resolution CMOS image sensors.
The most widely used column-level ADC in CMOS image sensors is the monoclinic ADC (ss ADC) because of its simple circuitry, easy implementation, and small chip area and power consumption consumed by the column-independent circuitry. However, for an SS ADC with n bits of resolution, 2 is required to perform one quantization n Since the quantization speed is slow for each clock cycle, the SS ADC is not suitable for use in a high frame rate, high resolution CMOS image sensor.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides an analog-to-digital converter which can solve the problem that the existing SS ADC is low in quantization speed.
In a first aspect, an embodiment of the present application provides an analog-to-digital converter, which includes a first ramp generating module, a second ramp generating module, and a pixel signal quantizing module; the first slope generation module and the second slope generation module are electrically connected with the pixel signal quantization module;
the first ramp generation module is used for providing a first ramp signal;
the pixel signal quantization module is used for quantizing the pixel signals with p resolution according to the first ramp signal to generate a first quantization result;
the second ramp generation module is configured to provide M segments of reference ramp signals, where a slope of an ith segment of reference ramp signal in the M segments of reference ramp signals is less than or equal to a slope of an i +1 th segment of reference ramp signal, and the ith segment of reference ramp signal corresponds to a slope of a q +1 th segment of reference ramp signal i Quantizing the pixel signal with resolution, wherein the i +1 th segment of the reference ramp signal corresponds to q i+1 Resolution quantizing said pixel signals, q i ≥q i+1 ， q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module is further configured to determine a target segment reference ramp signal in the M segment reference ramp signals according to the first quantization result, and quantize the pixel signal according to the target segment reference ramp signal at a target resolution corresponding to the target segment reference ramp signal, so as to generate a second quantization result.
In one possible implementation manner of the first aspect, the second ramp generation module includes a second ramp generator and a slope adjustment module; the second slope generator is electrically connected with the pixel signal quantization module through the slope adjusting module;
the second ramp generator is used for providing a second ramp signal;
the slope adjusting module is used for generating the M-segment reference ramp signals according to the second ramp signal.
In one possible implementation manner of the first aspect, the slope adjustment module includes N ramp sampling capacitors and N control switches;
the N ramp sampling capacitors are connected in parallel, the first end of the Nth ramp sampling capacitor is electrically connected with the second ramp generator, and the second end of the Nth ramp sampling capacitor is electrically connected with the pixel signal quantization module; the last (N-1) control switches are electrically connected between the first ends of two adjacent slope sampling capacitors, and the first control switch is electrically connected between the first end of the first slope sampling capacitor and a reference potential;
the slope adjusting module samples the second ramp signal based on the equivalent capacitances with different capacitance values and generates the M segments of reference ramp signals, and N is an integer greater than or equal to 2.
In one possible implementation manner of the first aspect, the capacitance value of the kth ramp sampling capacitor satisfies the formula Ck-2 k-2 And C1, wherein Ck is the capacitance value of the kth ramp sampling capacitor, C1 is the capacitance value of the first ramp sampling capacitor, and k is an integer greater than or equal to 2 and less than or equal to N.
In a possible implementation manner of the first aspect, the second ramp generation module includes M ramp generators and a second switch module, and the second switch module includes M second switches; each of the ramp generators is electrically connected with the pixel signal quantization module through one of the second switches to provide the M-segment reference ramp signals.
In a possible implementation manner of the first aspect, the first ramp generating module includes a first ramp generator and a first switch, and the first ramp generator is electrically connected to the pixel signal quantizing module through the first switch;
the first ramp generator is used for providing the first ramp signal;
the first switch is used for being switched on or switched off according to a first control signal; when the first switch is turned on, the first ramp generator can provide the first ramp signal to the pixel signal quantization module.
In one possible implementation manner of the first aspect, the pixel signal quantization module includes a comparison unit and a counting unit; the comparison unit is electrically connected with the first slope generation module, the second slope generation module and the counting unit respectively;
the comparison unit is used for receiving the pixel signal and the first ramp signal, comparing the pixel signal with the first ramp signal and outputting a first comparison signal;
the comparison unit is further configured to receive the pixel signal and the target segment reference ramp signal, compare the pixel signal and the target segment reference ramp signal, and output a second comparison signal;
the counting unit is used for counting at a p resolution when the comparison unit compares the pixel signal with the first ramp signal, and stopping counting when the first comparison signal output by the comparison unit is inverted to obtain the first quantization result;
the counting unit is used for counting at the target resolution when the comparison unit compares the pixel signal with the target segment reference ramp signal, and stopping counting when a second comparison signal output by the comparison unit is inverted to obtain the second quantization result.
In a possible implementation manner of the first aspect, the comparing unit includes a comparator; the positive input end of the comparator is electrically connected with the first slope generating module and the second slope generating module respectively, the negative input end of the comparator is used for receiving the pixel signal, and the output end of the comparator is electrically connected with the counting unit; and/or the counting unit comprises a counter which is electrically connected with the output end of the comparator; the counter is configured to output the first quantization result and the second quantization result to obtain an actual quantization result of the pixel signal based on the first quantization result and the second quantization result.
In one possible implementation manner of the first aspect, when M is 2 p Then, the quantized voltage range of each reference ramp signal in the M reference ramp signals is
V is the quantization voltage range of the analog-to-digital converter;
when M < 2 p And the quantization time of each reference slope signal in the M reference slope signals is the same.
In a possible implementation manner of the first aspect, when M < 2 p The quantization time of each reference slope signal in the M reference slope signals is
In a possible implementation manner of the first aspect, when M < 2 p 2 of said first ramp signal p The steps are divided into M step groups which are in one-to-one correspondence with the M sections of reference slope signals, wherein the ith step group in the M step groups corresponds to the ith section of reference slope signals, the number of the steps corresponding to the first step group to the Mth step group is increased progressively, and the number s of the (i +1) th step groups i+1 ＝2 t s i T is an integer greater than or equal to 0, s i The number of ith step groups.
In a second aspect, embodiments of the present application provide a readout circuit including an analog-to-digital converter as described in any one of the above.
In a third aspect, an embodiment of the present application provides an image sensor including the readout circuit described above.
In one possible implementation manner of the third aspect, when the analog-to-digital converter includes the slope adjustment module, the readout circuit further includes a plurality of first switches, a plurality of the slope adjustment modules, and a plurality of the pixel signal quantization modules;
the first slope generator is respectively and electrically connected with each first switch, the first switches are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner, the second slope generator is respectively and electrically connected with each slope adjustment module, and the slope adjustment modules are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner; or
When the analog-to-digital converter includes M ramp generators, the readout circuit further includes a plurality of the first switches, a plurality of the pixel signal quantization modules, and a plurality of second switch modules;
the first ramp generator is electrically connected with each first switch, the first switches are electrically connected with the pixel signal quantization modules in a one-to-one correspondence mode, the M ramp generators are electrically connected with the second switch modules in a respective one-to-one correspondence mode, and the second switch modules are electrically connected with the pixel signal quantization modules in a one-to-one correspondence mode.
In a fourth aspect, an embodiment of the present application provides an analog-to-digital conversion method applied to an analog-to-digital converter described in any one of the foregoing items, including:
the first ramp generation module outputs a first ramp signal;
the pixel signal quantization module quantizes the pixel signal according to the first ramp signal in p resolution to generate a first quantization result;
the second ramp generation module outputs M sections of reference ramp signals, wherein the slope of the ith section of reference ramp signal in the M sections of reference ramp signals is less than or equal to that of the (i +1) th section of reference ramp signal, and the ith section of reference ramp signal corresponds to q i Quantizing the pixel signal with resolution, wherein the i +1 th segment of the reference ramp signal corresponds to q i+1 Resolution quantizing said pixel signal, q i ≥q i+1 ，q 1+ p＝n，i＝1、 2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module determines a target segment reference ramp signal in the M segments of reference ramp signals according to the first quantization result, and is used for quantizing the pixel signal according to the target segment reference ramp signal by using a target resolution corresponding to the target segment reference ramp signal to generate a second quantization result.
Compared with the prior art, the embodiment of the application has the advantages that:
the embodiments of the present applicationAn analog-to-digital converter is provided, wherein a first ramp generating module is used for providing a first ramp signal. The pixel signal quantization module is used for quantizing the pixel signal with p resolution according to the first ramp signal to generate a first quantization result, the first quantization result is a p-bit digital code value, the quantization process is called a first quantization stage, and the quantization time of the first quantization stage is 2 p One clock cycle. The second ramp generating module is used for providing M sections of reference ramp signals, wherein the slope of the ith section of reference ramp signal in the M sections of reference ramp signals is less than or equal to that of the (i +1) th section of reference ramp signal, and the ith section of reference ramp signal corresponds to q i Resolution, i +1 th segment reference ramp signal corresponds to q i+1 Resolution, q i ≥q i+1 ， q 1+ p＝n，i＝1、2、…、M-1，M≤2 p And n is the highest resolution of the analog-to-digital converter. The pixel signal quantization module is used for determining the ith segment of reference ramp signal as a target segment of reference ramp signal in the M segments of reference ramp signals according to the first quantization result, and the target resolution corresponding to the target segment of reference ramp signal is q i The pixel signal quantization module is used for obtaining a target resolution q according to the target segment reference ramp signal i Quantizing the pixel signal to generate a second quantization result, q i The quantization process is referred to as a second quantization stage, the quantization time of which is
And obtaining an actual quantization result corresponding to the pixel signal based on the first quantization result and the second quantization result in one clock cycle. The time required for the whole quantization process is
One clock cycle, and the time required for the entire quantization process of the conventional SS ADC is 2 n Compared with the conventional SS ADC, the analog-to-digital converter provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter in each clock period.
It is understood that the beneficial effects of the second to fourth aspects can be seen from the description of the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic circuit diagram of a conventional SS ADC;
FIG. 2 is a schematic diagram of the operation of a conventional SS ADC;
FIG. 3 is a diagram illustrating the relationship between the dominant noise and pixel signal in an image sensor;
fig. 4 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 7 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 8 is a schematic structural diagram of an analog-to-digital converter according to another embodiment of the present application;
fig. 9 is a schematic diagram illustrating an operation of an analog-to-digital converter according to another embodiment of the present application;
FIG. 10 is a diagram illustrating an ADC quantization process according to another embodiment of the present application;
fig. 11 is a schematic diagram illustrating an operation of an analog-to-digital converter according to another embodiment of the present application;
fig. 12 is a schematic diagram of a quantization process of an analog-to-digital converter according to another embodiment of the present application.
10. A first ramp generating module; 101. a first ramp generator; 102. a first switch; 20. a second ramp generating module; 201. a second ramp generator; 202. a slope adjustment module; 203. a ramp generator; 204. a second switch module; 2041. a second switch; 30. a pixel signal quantization module; 301. a comparison unit; 302. a counting unit.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when …" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
Fig. 1 is a schematic circuit diagram of a conventional SS ADC, and fig. 2 is a schematic operation diagram of the conventional SS ADC. As shown in fig. 1 and fig. 2, the ramp generator generates a ramp signal Vrampi, a positive input terminal of the comparator receives the ramp signal Vrampi, and a negative input terminal of the comparator receives the pixel signal Vin; the ramp signal Vrampi can traverse the whole quantization voltage range and is compared with the pixel signal Vin, the counter starts counting, when the ramp signal Vrampi is larger than the pixel signal Vin, the comparator turns over, the counter stops counting, and the counting result is the digital code value after the pixel signal Vin is quantized.
As can be seen from the above description, for an SS ADC with n bits of resolution, 2 is required to perform one quantization n Since the quantization speed is slow for each clock cycle, the SS ADC is not suitable for use in a high frame rate, high resolution CMOS image sensor.
The noise sources in image sensors are mainly two: one is shot noise of photons, which is equal to the square root of the number of electrons in the pixel; the other is quantization noise, which is lower the higher the resolution of the analog-to-digital converter. The relationship between the dominant noise and the pixel signal in the image sensor can be represented by fig. 3, and it can be seen from fig. 3 that: in dim light, shot noise is small, and quantization noise plays a leading role; in the case of strong light, shot noise gradually dominates, and the influence of quantization noise gradually becomes smaller, and at this time, the requirement for the resolution of the analog-to-digital converter is reduced, so that it can be considered that the resolution of the analog-to-digital converter is switched to increase the quantization speed when the illumination becomes strong, and the power consumption is reduced.
In view of the above problem, the present embodiment provides an analog-to-digital converter, as shown in fig. 4, which includes a first ramp generating module 10, a second ramp generating module 20, and a pixel signal quantizing module 30. The first ramp generating module 10 and the second ramp generating module 20 are both electrically connected to the pixel signal quantizing module 30.
Specifically, the first ramp generating module 10 is configured to provide a first ramp signal Vcoarse, where the first ramp signal Vcoarse is a linear ramp signal with a certain slope.
The pixel signal quantization module 30 is configured to quantize the pixel signal Vin with p resolution according to the first ramp signal, and generate a first quantization result. The first quantization result is a p-bit digital code value, and the quantization process is referred to as a first quantization stage, the first quantization stage corresponds to a coarse quantization stage in the prior art, and the quantization time of the first quantization stage is 2 p One clock cycle.
The second ramp generating module 20 is configured to provide M segments of reference ramp signals, where a slope of an i-th segment of the reference ramp signals in the M segments of reference ramp signals is less than or equal to a slope of an i + 1-th segment of the reference ramp signals, and the i-th segment of the reference ramp signals corresponds to q i The pixel signal Vin is quantized by resolution, and the i +1 th segment of the reference ramp signal corresponds to the q segment i+1 The resolution quantizes the pixel signal Vin, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p And n is the highest resolution of the analog-to-digital converter.
The pixel signal quantization module 30 is configured to determine, according to the first quantization result, the i-th segment of the reference ramp signal Vramp _ i as a target segment of the reference ramp signal, where a target resolution corresponding to the target segment of the reference ramp signal Vramp _ i is q i 。
The pixel signal quantization module 30 is used for reference according to the target segmentRamp signal Vramp _ i at target resolution q i The pixel signal Vin is quantized to generate a second quantization result. The second quantization result is q i The quantization process is referred to as a second quantization stage, which corresponds to a prior art fine quantization stage, and the quantization time of the second quantization stage is
One clock cycle. And obtaining an actual quantization result corresponding to the pixel signal Vin based on the first quantization result and the second quantization result.
The time required for the whole quantization process is
One clock cycle, and the time required for the entire quantization process of the conventional SS ADC is 2 n Compared with the conventional SS ADC, the analog-to-digital converter provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter in one clock period.
It should be noted that the quantization mentioned in the pixel signal quantization module 30 includes a comparison process and a counting process. The quantization referred to in describing the reference ramp signal only includes a comparison process. The skilled person can operate as is practical.
As shown in fig. 5, the second ramp generating module 20 includes a second ramp generator 201 and a slope adjusting module 202. The second ramp generator 201 is electrically connected to the pixel signal quantization module 30 through a slope adjustment module 202.
Specifically, the second ramp generator 201 is configured to provide a second ramp signal Vramp, where the second ramp signal Vramp is a linear ramp signal having a certain slope.
The slope adjustment module 202 is configured to generate M segments of reference ramp signals according to the second ramp signal Vramp.
Compared with the method that a plurality of reference ramp signals are generated by a plurality of ramp generators, the slope adjusting module 202 in the application can generate M sections of reference ramp signals according to the second ramp signal Vramp, so that the using number of the ramp generators is reduced, the M sections of reference ramp signals can be generated only by one ramp generator, the chip area is saved, and the power consumption is reduced.
It should be noted that a designer may set a specific value of the slope of the second ramp signal Vramp generated by the second ramp generator 202 according to actual requirements.
As shown in FIG. 5, the slope adjustment module 202 includes N ramp sampling capacitors C1-CN and N control switches S1-SN. The N ramp sampling capacitors C1-CN are connected in parallel, and a first end of the nth ramp sampling capacitor CN is electrically connected to the second ramp generator 201, and a second end of the nth ramp sampling capacitor CN is electrically connected to the pixel signal quantization module 30. The last (N-1) control switches S2-SN are electrically connected between the first ends of two adjacent ramp sampling capacitors, and the first control switch S1 is electrically connected between the first end of the first ramp sampling capacitor C1 and the reference potential. The slope adjustment module 202 samples the second ramp signal Vramp based on the equivalent capacitors with different capacitance values and generates M segments of reference ramp signals, where N is an integer greater than or equal to 2.
It should be noted that, in practical applications, the reference potential may be a ground potential, that is, the first control switch S1 is connected between the first terminal of the first ramp sampling capacitor C1 and the ground potential.
Specifically, the N control switches S1-SN are used to form equivalent capacitors with different capacitance values according to the first quantization result, and the process is as follows:
in the first stage, the control switch S1 is closed, the control switch S2 is opened, the remaining control switches S3-SN are closed, which is equivalent to connecting the ramp sampling capacitors C2-CN in parallel and then in series with the first ramp sampling capacitor C1, the formed equivalent capacitor is used as a sampling capacitor to sample the second ramp signal Vramp, so as to obtain a 1 st segment of reference ramp signal, and the slope of the 1 st segment of reference ramp signal is denoted as K1.
In the second stage, the control switches S1-S2 are closed, the control switch S3 is opened, the other control switches S4-SN are closed, namely the ramp sampling capacitors C3-CN are connected in parallel, the ramp sampling capacitors C1-C2 are connected in parallel, the two parallel connection capacitors are connected in series to form an equivalent capacitor which is used as a sampling capacitor to sample the second ramp signal Vramp, the 2 nd-stage reference ramp signal is obtained, the slope of the 2 nd-stage reference ramp signal is marked as K2, and K1 is less than K2.
In the third stage, the control switches S1-S3 are closed, the control switch S4 is opened, the other control switches S5-SN are closed, namely slope sampling capacitors C4-CN are connected in parallel, slope sampling capacitors C1-C3 are connected in parallel, the two parallel connection capacitors are connected in series to form an equivalent capacitor which is used as a sampling capacitor to sample a second slope signal Vramp to obtain a 3 rd segment of reference slope signal, the slope of the 3 rd segment of reference slope signal is marked as K3, and K2 is less than K3;
and by analogy, obtaining M sections of reference slope signals, wherein M and N are in one-to-one correspondence.
It should be noted that, as can be understood by those skilled in the art, in the process of forming the mth stage reference ramp signal, the control switch S1 needs to be opened, and the remaining control switches S2-SN are closed, which is equivalent to connecting the ramp sampling capacitors C1-CN in parallel to form an equivalent capacitor as a sampling capacitor to sample the second ramp signal Vramp. Wherein, the second ramp signal Vramp is sampled based on the same point.
Further, if the slopes of the M segments of reference ramp signals are equal, the slopes of the M segments of reference ramp signals can be equal only by adjusting the control switches of each segment to be identical.
Furthermore, if the slope of the ith segment of reference ramp signal in the M segments of reference ramp signals is smaller than the slope of the (i +1) th segment of reference ramp signal, the capacitance value of the kth ramp sampling capacitor is made to satisfy the formula Ck of 2 k-2 And C1, wherein Ck is the capacitance value of the kth slope sampling capacitor, C1 is the capacitance value of the first slope sampling capacitor, and k is an integer greater than or equal to 2 and less than or equal to N.
As shown in fig. 6, the second ramp generating module 20 includes M ramp generators 203 and a second switching module 204. The second switch module 204 includes M second switches 2041. Each ramp generator 203 is electrically connected to the pixel signal quantization module 30 through a second switch 2041 to provide M segments of reference ramp signals Vramp _1, Vramp _2, …, Vramp _ M.
Specifically, the M second switches 2041 in the second switch module 204 are configured to be turned on or off according to the first quantization result to determine the target segment reference ramp signal Vramp _ i in the M segment reference ramp signals.
For example, when the second switch module 204 receives the first quantization result, the first quantization result controls the ith second switch 2041 of the M second switches 2041 to be closed and the remaining second switches 2041 to be opened, and the ith segment of the reference ramp signal Vramp _ i generated by the ith ramp generator 203 is provided to the pixel signal quantization module 30, so that the ith segment of the reference ramp signal Vramp _ i is the target segment of the reference ramp signal.
As shown in fig. 4, 5 and 6, the first ramp generating module 10 includes a first ramp generator 101 and a first switch 102. The first ramp generator 101 is electrically connected to the pixel signal quantization module 30 through a first switch 102.
In particular, the first ramp generator 101 is configured to provide a first ramp signal Vcoarse.
The first switch 102 is used for switching on or off according to a first control signal. When the first switch 102 is turned on, the first ramp generator 101 can provide the first ramp signal Vcoarse to the pixel signal quantization module 30, so that the pixel signal quantization module 30 is configured to quantize the pixel signal Vin with p resolution according to the first ramp signal Vcoarse, and generate a first quantization result.
It should be noted that, a designer may set a specific value of the slope of the first ramp signal Vcoarse generated by the first ramp generator 101 according to actual requirements. The first control signal may be generated by a controller electrically connected to the analog-to-digital converter.
As shown in fig. 4, the pixel signal quantization module 30 includes a comparison unit 301 and a counting unit 302. The comparison unit 301 is electrically connected to the first ramp generation module 10, the second ramp generation module 20, and the counting unit 302, respectively.
Specifically, the comparing unit 301 in the pixel signal quantization module 30 receives the first ramp signal Vcoarse and the pixel signal Vin, and compares the first ramp signal Vcoarse with the pixel signal VinAnd comparing and outputting a first comparison signal, wherein the counting unit 302 starts counting at a high p bit, and when the first comparison signal output by the comparison unit 301 is inverted, the counting unit 302 stops counting to obtain a first quantization result, wherein the first quantization result is a p-bit numerical code value. The pixel signal quantization module 30 determines the i-th segment of the reference ramp signal Vramp _ i as the target segment of the reference ramp signal in the M segments of the reference ramp signals according to the first quantization result, and the target resolution corresponding to the target segment of the reference ramp signal Vramp _ i is q i The comparing unit 301 in the pixel signal quantization module 30 receives the target segment reference ramp signal Vramp _ i and the pixel signal Vin, compares the target segment reference ramp signal Vramp _ i and the pixel signal Vin, and outputs a second comparison signal, when the counting unit 302 is low q i The bit starts to count, and when the second comparison signal output by the comparison unit 301 is inverted, the counting unit 302 stops counting to obtain a second quantization result, where the second quantization result is q i And the numerical value code value of the bit is used for obtaining an actual quantization result corresponding to the pixel signal Vin based on the first quantization result and the second quantization result.
It should be noted that, when the first ramp signal Vcoarse does not reach the pixel signal Vin, the first comparison signal output by the comparison unit 301 is at a low level. When the first ramp signal Vcoarse reaches the pixel signal Vin, the first comparison signal is inverted, and the first comparison signal output by the comparison unit 301 becomes a high level.
Similarly, when the target segment reference ramp signal Vramp _ i does not reach the pixel signal Vin, the second comparison signal output by the comparison unit 301 is at a low level. When the target segment reference ramp signal Vramp _ i reaches the pixel signal Vin, the second comparison signal is inverted, and the second comparison signal output by the comparison unit 301 becomes a high level.
As shown in fig. 4, the comparison unit 301 includes a comparator. The positive input end of the comparator is electrically connected to the first ramp generating module 10 and the second ramp generating module 20, respectively, and is configured to receive the first ramp signal Vcoarse and the target segment reference ramp signal Vramp _ i, the negative input end of the comparator is configured to receive the pixel signal Vin, and the output end of the comparator is electrically connected to the counting unit 302 and is configured to output the first comparison signal and the second comparison signal, and instruct the counting unit 302 to operate.
The counting unit 302 includes a counter. The counter is electrically connected with the output end of the comparator. The counter is used for counting when the comparator starts to compare, stopping counting when the result output by the comparator is inverted, and finally outputting the first quantization result and the second quantization result so as to obtain the actual quantization result of the pixel signal Vin based on the first quantization result and the second quantization result.
Based on the above description, when M is 2 p The quantized voltage range of each reference ramp signal in the M reference ramp signals is
V is the quantization voltage range of the analog-to-digital converter.
When M < 2 p In time, the quantization time of each reference ramp signal in the M reference ramp signals is the same.
Further, as shown in fig. 9, when M is 2 p The first ramp signal Vcoarse averages the quantization voltage range of the analog-to-digital converter by 2 p Each step corresponds to a section of reference ramp signal, and the quantization range of each section of reference ramp signal is equal to one step height of the first ramp signal Vcoarse.
For a two-step multi-ramp ADC, assuming that it is p bits for coarse quantization and q bits for fine quantization, the time it takes to complete one quantization is (2) p +2 q ) One clock cycle. As described above, the resolutions of the M reference ramp signals generated in the embodiment of the present application may be different, and according to the relationship between the shot noise and the quantization noise along with the change of the light intensity, when the pixel signal is large and the shot noise is dominant, the resolution of the analog-to-digital converter is appropriately reduced, so as to further increase the quantization speed and reduce the power consumption. Since the quantization range of each reference ramp signal is equal to the entire quantization range
Therefore, the analog-to-digital converter provided by the embodiment of the application needs to complete one-time quantizationAt a time of
In practical application, the allocation modes of the reference ramp signal and the partial slope can be flexibly selected according to requirements of imaging quality, frame rate, chip area, power consumption and the like. Because the number of the reference ramp signals is the power exponent of the resolution of the first quantization stage, and with the increase of the resolution of the first quantization stage, when the analog-to-digital converter comprises M ramp generators, the number of the ramp generators is also increased exponentially, which can increase the chip area and power consumption, the resolution of the first quantization stage is generally selected from 2-3 bits, the resolution of the second quantization stage is at least not lower than 6 bits, the resolution of the whole analog-to-digital converter is ensured to be at least not lower than 8-9 bits under strong light, and the image quality is not seriously reduced while the quantization speed is improved.
Further, when M < 2 p Then, the quantization time of each reference ramp signal in the M reference ramp signals is the same, and the quantization time is
As shown in fig. 11, 2 of the first ramp signal Vcoarse p The steps are divided into M step groups which are in one-to-one correspondence with the M sections of reference slope signals, wherein the ith step group in the M step groups corresponds to the ith section of reference slope signals, the number of the steps corresponding to the first step group to the Mth step group is increased progressively, and the number s of the (i +1) th step group i+1 ＝2 t s i T is an integer greater than or equal to 0, s i The number of ith step groups.
For a two-step multi-ramp ADC, assuming it is coarsely quantized to p bits and finely quantized to q bits, it needs (2) p +1 ramp generators, the time required to complete one quantization is (2) p +2 q ) One clock cycle. The analog-to-digital converter provided by the embodiment of the application properly reduces the resolution of the reference ramp signal based on the characteristic that the shot noise and the quantization noise change along with the light intensity under the strong light condition, namely when the pixel signal is larger, so that the analog-to-digital converter canThere is a larger quantization range within the same quantization time, reducing the number of reference ramp signals, i.e. when the analog-to-digital converter comprises ramp generators, the number of ramp generators may be reduced.
In practical application, the resolution of the first quantization stage and the distribution mode of the reference ramp signal slope can be flexibly selected according to requirements of imaging quality, frame rate, chip area, power consumption and the like. The analog-to-digital converter provided by the embodiment of the application overcomes the defects of large chip area and large power consumption of the traditional two-step multi-slope ADC, so that the resolution of the first quantization stage can be expanded, for example, the resolution of the first quantization stage is 3-5 bits, the resolution of the second quantization stage is not lower than 5 bits at least, the resolution of the whole analog-to-digital converter is not lower than 8-10 bits at least under strong light, and the image quality is not seriously reduced while the quantization speed is improved.
Embodiments of the present application further provide a readout circuit including an analog-to-digital converter as described in any one of the above. The analog-to-digital converter in the readout circuit divides the quantization process into a first quantization stage and a second quantization stage, wherein the first quantization stage: the first ramp generating module 10 is configured to provide a first ramp signal Vcoarse, the pixel signal quantizing module 30 is configured to quantize the pixel signal Vin with p resolution according to the first ramp signal to generate a first quantization result, where the first quantization result is a p-bit digital code value, and a quantization time of the first quantization stage is 2 p One clock cycle. And a second quantization stage: the second ramp generating module 20 is configured to provide M segments of reference ramp signals, where a slope of an i-th segment of the reference ramp signals in the M segments of reference ramp signals is less than or equal to a slope of an i + 1-th segment of the reference ramp signals, and the i-th segment of the reference ramp signals corresponds to q i The pixel signal Vin is quantized with resolution, and the i +1 th segment of the reference ramp signal corresponds to the q-th segment i+1 Resolution quantizes the pixel signal Vin, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p And n is the highest resolution of the analog-to-digital converter. The pixel signal quantization module 30 is configured to determine an i-th segment of the reference ramp signal Vram from the M segments of the reference ramp signal according to the first quantization resultp _ i is a target segment reference ramp signal, and the target resolution corresponding to the target segment reference ramp signal Vramp _ i is q i . The pixel signal quantization module 30 is used for quantizing the target resolution q according to the target segment reference ramp signal Vramp _ i i Quantizing the pixel signal Vin to generate a second quantization result, wherein the second quantization result is q i Digital code values of bits, quantization time of the second quantization stage being
And obtaining an actual quantization result of the pixel signal Vin based on the first quantization result and the second quantization result in one clock cycle. The time required for the whole quantization process is
One clock cycle, and the time required for the entire quantization process of the conventional readout circuit is 2 n Compared with the traditional reading circuit, the reading circuit provided by the embodiment of the application has the advantages that the quantization speed is increased, the quantization time is shortened, and the power consumption is correspondingly reduced by adjusting the resolution of the analog-to-digital converter in one clock period.
The embodiment of the application also provides an image sensor which comprises the readout circuit.
Further, as shown in fig. 7, when the analog-to-digital converter includes the slope adjusting module 202, the readout circuit further includes a plurality of first switches 102, a plurality of slope adjusting modules 202, and a plurality of pixel signal quantizing modules 30. The first ramp generator 101 is electrically connected to each first switch 102, the plurality of first switches 102 are electrically connected to the plurality of pixel signal quantization modules 30 in a one-to-one correspondence manner, the second ramp generator 201 is electrically connected to each slope adjustment module 202, and the plurality of slope adjustment modules 202 are electrically connected to the plurality of pixel signal quantization modules 30 in a one-to-one correspondence manner.
Further, as shown in fig. 8, when the analog-to-digital converter includes M ramp generators 203, the readout circuit further includes a plurality of first switches 102, a plurality of pixel signal quantization modules 30, and a plurality of second switch modules 204. The first ramp generator 101 is electrically connected to each first switch 102, the first switches 102 are electrically connected to the pixel signal quantization modules 30 in a one-to-one correspondence manner, the M ramp generators 203 are electrically connected to each second switch module 204, and the second switch modules 204 are electrically connected to the pixel signal quantization modules 30 in a one-to-one correspondence manner.
The image sensor provided by the embodiment of the application has the characteristics of high quantization speed and low power consumption, and for a specific working principle, reference is made to the description of the working principle of the readout circuit and the analog-to-digital converter, which is not described herein again.
An embodiment of the present application further provides an analog-to-digital conversion method, applied to the analog-to-digital converter described in any one of the above, including:
s1, the first ramp generating module 10 outputs a first ramp signal Vcoarse.
Specifically, the first ramp signal Vcoarse is a linear ramp signal having a certain slope, and the value of the slope may be set according to actual requirements.
S2, the pixel signal quantization module 30 quantizes the pixel signal Vin with p resolution according to the first ramp signal Vcoarse, and generates a first quantization result.
Specifically, the first quantization result is a digital code value of p bits, the quantization process is referred to as a first quantization stage, and the quantization time of the first quantization stage is 2 p One clock cycle.
S3, the second ramp generating module 20 outputs M segments of reference ramp signals, wherein the slope of the i-th segment of reference ramp signal in the M segments of reference ramp signals is less than or equal to the slope of the i + 1-th segment of reference ramp signal, and the i-th segment of reference ramp signal corresponds to q i The pixel signal Vin is quantized with resolution, and the i +1 th segment of the reference ramp signal corresponds to the q-th segment i+1 Resolution quantizes the pixel signal Vin, q i ≥q i+1 ，q 1+ p＝n，i＝1、 2、…、M-1，M≤2 p And n is the highest resolution of the analog-to-digital converter.
S4, the pixel signal quantization module 30 determines the i-th segment Vramp _ i as the target segment Vramp _ i of the M segments of reference ramp signals according to the first quantization resultThe target resolution corresponding to the segment reference ramp signal Vramp _ i is q i 。
S5, the pixel signal quantization module 30 generates the target resolution q according to the target segment reference ramp signal Vramp _ i i The pixel signal Vin is quantized to generate a second quantization result.
Specifically, the second quantization result is q i The quantization process is referred to as a second quantization stage, the quantization time of which is
One clock cycle. And obtaining an actual quantization result corresponding to the pixel signal Vin based on the first quantization result and the second quantization result.
The time required for the whole quantization process is
One clock cycle, and the time required for the entire quantization process of the conventional SS ADC is 2 n Compared with the conventional SS ADC, the analog-to-digital converter provided by the embodiment of the application improves the quantization speed, reduces the quantization time and correspondingly reduces the power consumption by adjusting the resolution of the analog-to-digital converter in one clock period.
Example one
Setting the highest resolution n of the analog-to-digital converter to be 12 bits, setting the resolution p of the first quantization stage to be 2 bits, and setting M to be 2 p When M is 4, the resolutions corresponding to the 4-segment reference ramp signals are 10bit, 9bit and 8bit, respectively. Meanwhile, it is assumed that the pixel signal Vin to be quantized is within the third step range of the first ramp signal Vcoarse, as shown in fig. 10.
First, a first quantization stage is performed, the counter starts counting at the high 2 bits, the output of the comparator is inverted when the first ramp signal Vcoarse runs to the third step, at this time, the counter stops counting, and the high 2 bits of the counter store the first quantization result. Then, the second quantization stage is entered, the first quantization result stored with the high 2 bits is fed back to the switch corresponding to the slope adjustment module 202 or the switch corresponding to the second switch module 204,and controlling a corresponding switch to connect the 3 rd segment of reference ramp signal Vramp _3 to a comparator, comparing the 3 rd segment of reference ramp signal Vramp _3 with the pixel signal Vin, and starting counting by the lower 9 bits of a counter. Until the 3 rd segment reference ramp signal Vramp _3 and the pixel signal Vin are equal, the output of the comparator is inverted, the counter stops counting, and the lower 9 bits of the counter store the second quantization result. And combining the first quantization result and the second quantization result into an 11-bit digital code, namely finishing the quantization process. The time required for the entire quantization process is: 2 2 +2 9 516 clock cycles. If a conventional SS ADC is used, the time required to complete one quantization of 11 bits is: 2 11 2048 clock cycles. Therefore, the quantization time required by the analog-to-digital converter proposed in the embodiment of the present application is only about 1/4 of the conventional SS ADC. Compared with a two-step multi-ramp ADC, the analog-to-digital converter provided by the embodiment of the application properly reduces the resolution of the analog-to-digital converter when the large pixel signal is quantized, and improves the speed when the large pixel signal is quantized. Assuming that the two-step multi-ramp ADC adopts a 2-bit coarse quantization and a 10-bit fine quantization mode, the average time required for completing one quantization is 2 2 +2 10 1028 clock cycles; according to the analog-to-digital converter provided by the embodiment of the application, the average time required for completing one quantization is
The quantization speed of the two-step multi-ramp ADC is increased by about 31% in each clock period, and the corresponding power consumption is reduced in an equal proportion.
Example two
Setting the highest resolution n of the A/D converter to 12 bits, setting the resolution p of the first quantization stage to 3 bits, and making M < 2 p When M is 4, the resolutions corresponding to the 4 segments of reference ramp signals are 9bit, 8bit and 7bit, respectively, and it is assumed that the pixel signal Vin to be quantized is large and falls within the 4 th segment of reference ramp range, as shown in fig. 12.
Firstly, a first quantization stage is carried out, the counter starts counting at the high 3 bits, the output of the comparator is overturned when the first ramp signal Vcoarse runs to the 6 th step, and at the momentThe counter stops counting and the counter stores the first quantization result 3 bits higher. Then, the quantization is performed in the second quantization stage, and the reference ramp signal with lower resolution is selected for quantization because the quantized pixel signal is larger. The first quantization result stored by the high 3 bits is fed back to the switch corresponding to the slope adjustment module 202 or the switch corresponding to the second switch module 204, the corresponding switch is controlled to connect the 4 th segment of the reference ramp signal Vramp _4 to the comparator, the 4 th segment of the reference ramp signal Vramp _4 is compared with the pixel signal Vin, and the counter starts counting at the low 7 bits. Until the 4 th segment reference ramp signal Vramp _4 and the pixel signal Vin are equal, the output of the comparator is inverted, the counter stops counting, and the lower 7 bits of the counter store the second quantization result. And combining the first quantization result and the second quantization result into a 10-bit digital code, thus finishing the quantization process. The time required for the entire quantization process is: (2 3 +2 7 ) 136 clock cycles; whereas if a conventional SS ADC is used, the time required to complete a 10bit quantization is: 2 10 1024 clock cycles. The quantization time required by the analog-to-digital converter provided by the embodiment of the application is reduced by about 87% compared with the conventional SS ADC. Compared with a two-step multi-ramp ADC, the analog-to-digital converter provided by the embodiment of the application properly reduces the resolution of the analog-to-digital converter when a large pixel signal is quantized, improves the quantization speed, and reduces the number of reference ramp signals.
Assuming that the two-step multi-ramp ADC adopts the same 3-bit coarse quantization and 9-bit fine quantization modes, the number of ramp generators required by the two-step multi-ramp ADC is (2) 3 +1) is 9, and this application needs 5 ramp generators at most, needs 2 ramp generators at least, has reached the effect that reduces chip area and reduce power consumption.
To sum up, the analog-to-digital converter provided in the embodiment of the present application divides a quantization process into a first quantization stage and a second quantization stage, provides M segments of reference ramp signals in the second quantization stage, and sets the M segments of reference ramp signals as multi-slope and multi-resolution ramp signals, so as to adjust the resolution of the analog-to-digital converter under a strong light condition, improve the quantization speed, and reduce the power consumption.
In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (14)
1. An analog-to-digital converter is characterized by comprising a first slope generation module, a second slope generation module and a pixel signal quantization module; the first slope generation module and the second slope generation module are electrically connected with the pixel signal quantization module;
the first ramp generation module is used for providing a first ramp signal;
the pixel signal quantization module is used for quantizing the pixel signal with p resolution according to the first ramp signal to generate a first quantization result;
the second ramp generating module is configured to provide M segments of reference ramp signals, where a slope of an i-th segment of reference ramp signal in the M segments of reference ramp signals is less than or equal to a slope of an i + 1-th segment of reference ramp signal, and the i-th segment of reference ramp signal corresponds to a q-th segment of reference ramp signal i Quantizing the pixel signal with resolution, wherein the i +1 th segment of the reference ramp signal corresponds to q i+1 Resolution quantizing said pixel signal, q i ≥q i+1 ，q 1+ p＝n，i＝1、2、…、M-1，M≤2 p N is the highest resolution of the analog-to-digital converter;
the pixel signal quantization module is further configured to determine a target segment reference ramp signal in the M segment reference ramp signals according to the first quantization result, and quantize the pixel signal according to the target segment reference ramp signal at a target resolution corresponding to the target segment reference ramp signal, so as to generate a second quantization result.
2. The analog-to-digital converter of claim 1, wherein the second ramp generation module comprises a second ramp generator and a slope adjustment module; the second slope generator is electrically connected with the pixel signal quantization module through the slope adjusting module;
the second ramp generator is used for providing a second ramp signal;
the slope adjusting module is used for generating the M-segment reference ramp signals according to the second ramp signal.
3. The analog-to-digital converter of claim 2, wherein the slope adjustment module comprises N ramp sampling capacitors and N control switches;
the N ramp sampling capacitors are connected in parallel, the first end of the Nth ramp sampling capacitor is electrically connected with the second ramp generator, and the second end of the Nth ramp sampling capacitor is electrically connected with the pixel signal quantization module; the last (N-1) control switches are electrically connected between the first ends of two adjacent slope sampling capacitors, and the first control switch is electrically connected between the first end of the first slope sampling capacitor and a reference potential;
the slope adjusting module samples the second ramp signal based on the equivalent capacitances with different capacitance values and generates the M segments of reference ramp signals, and N is an integer greater than or equal to 2.
4. An analog-to-digital converter as claimed in claim 3, characterized in that the capacitance of the kth ramp sampling capacitor satisfies the formula Ck-2 k-2 C1, where Ck is the capacitance of the kth ramp sampling capacitor, and C1 is the first oneThe capacitance value of the capacitor is sampled in a slope mode, and k is an integer which is larger than or equal to 2 and smaller than or equal to N.
5. The analog-to-digital converter of claim 1, wherein the second ramp generation module comprises M ramp generators and a second switch module, the second switch module comprising M second switches; each of the ramp generators is electrically connected with the pixel signal quantization module through one of the second switches to provide the M-segment reference ramp signals.
6. The analog-to-digital converter of claim 1, wherein the first ramp generating module comprises a first ramp generator and a first switch, the first ramp generator being electrically connected to the pixel signal quantizing module through the first switch;
the first ramp generator is used for providing the first ramp signal;
the first switch is used for being switched on or switched off according to a first control signal; when the first switch is turned on, the first ramp generator can provide the first ramp signal to the pixel signal quantization module.
7. The analog-to-digital converter according to claim 1, wherein the pixel signal quantization module includes a comparison unit and a counting unit; the comparison unit is electrically connected with the first slope generation module, the second slope generation module and the counting unit respectively;
the comparison unit is used for receiving the pixel signal and the first ramp signal, comparing the pixel signal with the first ramp signal and outputting a first comparison signal;
the comparison unit is further configured to receive the pixel signal and the target segment reference ramp signal, compare the pixel signal and the target segment reference ramp signal, and output a second comparison signal;
the counting unit is used for counting at a p resolution when the comparison unit compares the pixel signal with the first ramp signal, and stopping counting when the first comparison signal output by the comparison unit is inverted to obtain the first quantization result;
the counting unit is used for counting at the target resolution when the comparison unit compares the pixel signal with the target segment reference ramp signal, and stopping counting when a second comparison signal output by the comparison unit is inverted to obtain the second quantization result.
8. The analog-to-digital converter of claim 7, wherein the comparison unit comprises a comparator; a positive input end of the comparator is electrically connected with the first ramp generating module and the second ramp generating module respectively, a negative input end of the comparator is used for receiving the pixel signal, and an output end of the comparator is electrically connected with the counting unit; and/or the counting unit comprises a counter which is electrically connected with the output end of the comparator; the counter is configured to output the first quantization result and the second quantization result to obtain an actual quantization result of the pixel signal based on the first quantization result and the second quantization result.
9. An analog-to-digital converter as claimed in any one of claims 1 to 8, characterized in that when M-2 p The quantized voltage range of each reference slope signal in the M reference slope signals is
V is the quantization voltage range of the analog-to-digital converter;
when M < 2 p And the quantization time of each reference slope signal in the M reference slope signals is the same.
10. The analog-to-digital converter of claim 9, wherein when M < 2 p Each of the M reference ramp signalsThe quantization times of the ramp signals are all
11. The analog-to-digital converter of claim 9, wherein when M < 2 p 2 of said first ramp signal p The steps are divided into M step groups which are in one-to-one correspondence with the M sections of reference slope signals, wherein the ith step group in the M step groups corresponds to the ith section of reference slope signals, the number of the steps corresponding to the first step group to the Mth step group is increased progressively, and the number s of the (i +1) th step groups i+1 ＝2 t s i T is an integer greater than or equal to 0, s i The number of ith step groups.
12. A readout circuit comprising an analog-to-digital converter according to any of claims 1 to 11.
13. An image sensor comprising the readout circuit of claim 12.
14. The image sensor of claim 13, wherein when the analog-to-digital converter includes the slope adjustment module, the readout circuit further includes a plurality of first switches, a plurality of the slope adjustment modules, and a plurality of the pixel signal quantization modules;
the first slope generator is electrically connected with each first switch respectively, the first switches are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner, the second slope generator is electrically connected with each slope adjusting module respectively, and the slope adjusting modules are electrically connected with the pixel signal quantization modules in a one-to-one correspondence manner; or
When the analog-to-digital converter includes M ramp generators, the readout circuit further includes a plurality of the first switches, a plurality of the pixel signal quantization modules, and a plurality of second switch modules;
the first ramp generator is electrically connected with each first switch, the first switches are electrically connected with the pixel signal quantization modules in a one-to-one correspondence mode, the M ramp generators are electrically connected with the second switch modules in a respective one-to-one correspondence mode, and the second switch modules are electrically connected with the pixel signal quantization modules in a one-to-one correspondence mode.
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