JP2018073413A5 - - Google Patents

Download PDF

Info

Publication number
JP2018073413A5
JP2018073413A5 JP2017204581A JP2017204581A JP2018073413A5 JP 2018073413 A5 JP2018073413 A5 JP 2018073413A5 JP 2017204581 A JP2017204581 A JP 2017204581A JP 2017204581 A JP2017204581 A JP 2017204581A JP 2018073413 A5 JP2018073413 A5 JP 2018073413A5
Authority
JP
Japan
Prior art keywords
dram
dpu
rows
computing
stochastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017204581A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018073413A (ja
JP6920169B2 (ja
Filing date
Publication date
Priority claimed from US15/426,015 external-priority patent/US10180808B2/en
Application filed filed Critical
Publication of JP2018073413A publication Critical patent/JP2018073413A/ja
Publication of JP2018073413A5 publication Critical patent/JP2018073413A5/ja
Application granted granted Critical
Publication of JP6920169B2 publication Critical patent/JP6920169B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2017204581A 2016-10-27 2017-10-23 Ｄｒａｍ基盤の確率論的コンピューティングシステム Active JP6920169B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662413973P 2016-10-27 2016-10-27
US62/413,973 2016-10-27
US15/426,015 2017-02-06
US15/426,015 US10180808B2 (en) 2016-10-27 2017-02-06 Software stack and programming for DPU operations

Publications (3)

Publication Number Publication Date
JP2018073413A JP2018073413A (ja) 2018-05-10
JP2018073413A5 true JP2018073413A5 (enExample) 2020-12-03
JP6920169B2 JP6920169B2 (ja) 2021-08-18

Family

ID=62021467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017204581A Active JP6920169B2 (ja) 2016-10-27 2017-10-23 Ｄｒａｍ基盤の確率論的コンピューティングシステム

Country Status (5)

Country Link
US (1) US10180808B2 (enExample)
JP (1) JP6920169B2 (enExample)
KR (1) KR102268179B1 (enExample)
CN (1) CN108010551B (enExample)
TW (1) TWI718336B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
KR20200057475A (ko) 2018-11-16 2020-05-26 삼성전자주식회사 연산 회로를 포함하는 메모리 장치 및 그것을 포함하는 뉴럴 네트워크 시스템
WO2020159800A1 (en) 2019-01-28 2020-08-06 Rambus Inc. Memory-integrated neural network
US10949214B2 (en) * 2019-03-29 2021-03-16 Intel Corporation Technologies for efficient exit from hyper dimensional space in the presence of errors
US11074008B2 (en) * 2019-03-29 2021-07-27 Intel Corporation Technologies for providing stochastic key-value storage
US11157692B2 (en) * 2019-03-29 2021-10-26 Western Digital Technologies, Inc. Neural networks using data processing units
CN110275498A (zh) * 2019-06-28 2019-09-24 泉州信息工程学院 一种基于互联网与深度学习的智能制造方法和系统及设备
CN112684977B (zh) * 2019-10-18 2024-05-28 旺宏电子股份有限公司 存储器装置及其存储器内计算方法
US12159219B2 (en) * 2020-08-19 2024-12-03 Micron Technology, Inc. Neuron using posits
CN115668224B (zh) * 2020-06-29 2024-06-11 美光科技公司 使用posit的神经形态运算
CN114201421B (zh) * 2022-02-17 2022-05-10 苏州浪潮智能科技有限公司 一种数据流处理方法、存储控制节点及可读存储介质
US20230205500A1 (en) * 2023-03-07 2023-06-29 Lemon Inc. Computation architecture synthesis
KR102733671B1 (ko) 2023-08-14 2024-11-25 서울과학기술대학교 산학협력단 반도체 소자, 이를 포함하는 반도체 장치 및 그의 제조 방법
KR102752637B1 (ko) * 2023-12-05 2025-01-10 경북대학교 산학협력단 스토캐스틱 컴퓨팅 기반의 확률수 생성기 및 이를 이용한 스토캐스틱 컴퓨팅 회로
KR20250145258A (ko) 2024-03-28 2025-10-13 경희대학교 산학협력단 Dram의 비트 단위 논리 연산을 수행하는 pim 연산 장치 및 pim 연산 방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1120373A (zh) * 1993-03-17 1996-04-10 蔡卡得公司 基于随机存储存贮器(ram)的可配置阵列
US5847577A (en) * 1995-02-24 1998-12-08 Xilinx, Inc. DRAM memory cell for programmable logic devices
JPH11338767A (ja) * 1998-05-22 1999-12-10 Mitsubishi Heavy Ind Ltd 画像処理用機能メモリ装置
US6745219B1 (en) 2000-06-05 2004-06-01 Boris Zelkin Arithmetic unit using stochastic data processing
US9552047B2 (en) * 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US6507530B1 (en) * 2001-09-28 2003-01-14 Intel Corporation Weighted throttling mechanism with rank based throttling for a memory system
US8127075B2 (en) 2007-07-20 2012-02-28 Seagate Technology Llc Non-linear stochastic processing storage device
US8352384B2 (en) 2008-03-04 2013-01-08 Massachusetts Institute Of Technology Combinational stochastic logic
US8341362B2 (en) * 2008-04-02 2012-12-25 Zikbit Ltd. System, method and apparatus for memory with embedded associative section for computations
US8103598B2 (en) 2008-06-20 2012-01-24 Microsoft Corporation Compiler for probabilistic programs
US20140223439A1 (en) 2010-02-22 2014-08-07 Analog Devices, Inc. Superscalar control for a probability computer
US8645286B2 (en) 2010-02-23 2014-02-04 Prior Knowledge, Inc. Configurable circuitry for solving stochastic problems
WO2013062596A1 (en) * 2011-10-28 2013-05-02 Hewlett-Packard Development Company, L.P. Row shifting shiftable memory
US9251467B2 (en) 2013-03-03 2016-02-02 Microsoft Technology Licensing, Llc Probabilistic parsing
KR102168652B1 (ko) * 2013-12-16 2020-10-23 삼성전자주식회사 감지 증폭기, 그것을 포함하는 반도체 메모리 장치 및 그것의 읽기 방법
US9455020B2 (en) * 2014-06-05 2016-09-27 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
US9697877B2 (en) * 2015-02-05 2017-07-04 The Board Of Trustees Of The University Of Illinois Compute memory
US9922696B1 (en) * 2016-10-28 2018-03-20 Samsung Electronics Co., Ltd. Circuits and micro-architecture for a DRAM-based processing unit

Similar Documents

Publication Publication Date Title
JP2018073413A5 (enExample)
JP2018073402A5 (enExample)
JP7244999B2 (ja) ディスターブ・ロウをケアするメモリ装置及びその動作方法
TWI629686B (zh) 用於同時存取非揮發性記憶體之多個分區之裝置及方法
US9778848B2 (en) Method and apparatus for improving read performance of a solid state drive
EP3061008B1 (en) Data storage device supporting accelerated database operations
US8244972B2 (en) Optimizing EDRAM refresh rates in a high performance cache architecture
JP2018073452A5 (enExample)
JP2021128752A5 (enExample)
CN109219850A (zh) 存储器中的延迟回写
US12235778B2 (en) Memory system of artificial neural network based on artificial neural network data locality
KR20160063726A (ko) 메모리 장치 및 이를 포함하는 메모리 시스템
US20250377825A1 (en) Electronic device including npu and dram for performing inference of an artificial neural network
US20220189538A1 (en) Memory system
Jung et al. ConGen: An application specific DRAM memory controller generator
US20220137866A1 (en) Memory device for an artificial neural network
WO2016206529A1 (zh) 一种存储器的控制方法、装置及计算机存储介质
CN106055495A (zh) 用于控制半导体装置的方法
US20250036306A1 (en) Memory controller circuit and system for artificial neural network and method thereof
EP2979193B1 (en) Shared memory system
US12236996B2 (en) Memory device and refresh method thereof
KR102728101B1 (ko) 인공신경망을 위한 시스템 및 메모리
KR102706330B1 (ko) 인공신경망을 위한 메모리 제어부, 프로세서 및 시스템
CN117789785A (zh) 存储器件及其操作方法
US20170185292A1 (en) Memory Management of High-Performance Memory