JP2018049928A5

JP2018049928A5 -

Info

Publication number: JP2018049928A5
Application number: JP2016184257A
Authority: JP
Filing date: 2016-09-21
Publication date: 2019-02-14
Anticipated expiration: 2036-09-21

Description

しかしながら、特許文献１のＳｉＣ半導体装置では、より低飽和電流として高い耐量が得られるように、ｐ型ベース領域のうちのＪＦＥＴ部分の不純物濃度を濃くしたり、ＪＦＥＴ部分において隣り合うｐ型ベース領域の間隔を狭くすると、ＪＦＥＴ抵抗が増大する。このため、低オン抵抗値と低飽和電流を両立することができなくなる。 However, in the SiC semiconductor device of Patent Document 1, the impurity concentration of the JFET portion in the p-type base region is increased or the adjacent p-type base region in the JFET portion so as to obtain a high withstand amount as a lower saturation current. When narrowing the interval, JFET resistance increases. For this reason, it becomes impossible to achieve both a low on-resistance value and a low saturation current.

同様に、上記各実施形態で説明したＳｉＣ半導体装置を構成する各部の寸法や不純物濃度については一例を示したに過ぎない。各部の寸法や不純物濃度については、高濃度ｎ型層２０や低濃度ｐ型層３０およびＪＦＥＴ部２ａのピンチオフ条件等に基づいて、適宜設定すれば良い。 Similarly, the dimensions and impurity concentrations of the respective parts constituting the SiC semiconductor device described in the above embodiments are merely examples. The dimensions and impurity concentration of each part may be appropriately set based on the pinch-off conditions of the high-concentration n-type layer 20, the low-concentration p-type layer 30, and the JFET portion 2a.

Claims

A first or second conductivity type substrate (1) made of a semiconductor;
A drift layer (2) made of a first conductivity type semiconductor formed on the substrate and having a lower impurity concentration than the substrate;
A second conductivity type region (3, 5, 6, 8, 71) made of a second conductivity type semiconductor formed on the drift layer;
A JFET portion (2a) formed on the drift layer and disposed between the second conductivity type regions;
A source region (7) formed on the second conductivity type region and made of a first conductivity type semiconductor having a higher concentration than the drift layer;
A part of the second conductivity type region as a channel region, a gate insulating film (10) formed on the channel region;
A gate electrode (11) formed on the gate insulating film;
An interlayer insulating film (12) covering the gate electrode and the gate insulating film and having contact holes formed therein;
A source electrode (13) electrically connected to the source region through the contact hole;
A drain electrode (14) formed on the back side of the substrate;
The channel region is formed by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to be applied to the drain electrode, and through the source region and the JFET portion. , Comprising an inversion type semiconductor element for passing a current between the source electrode and the drain electrode,
A depletion layer extending from the second conductivity type region to the JFET portion when the normal operation voltage is applied as the drain voltage between the JFET portion and the second conductivity type region. A depletion layer adjusting layer (20, 30) that causes the depletion layer to pinch off the JFET portion when a current is passed through the JFET portion while being suppressed and a voltage higher than the normal operation voltage is applied as the drain voltage. Formed ,
The second conductivity type region is
A deep layer (3) formed on the drift layer;
A base region (6) connected to the deep layer and connected to the source electrode and forming the channel region;
The deep layer protrudes from the base region to the center line side of the gate electrode,
The JFET part is sandwiched between the deep layers,
The depletion layer adjustment layer is a semiconductor device formed between the JFET portion and the deep layer .

2. The semiconductor device according to claim 1 , wherein the depletion layer adjustment layer is a first conductivity type high concentration layer (20) having an impurity concentration higher than that of the JFET portion.

The semiconductor device according to claim 2 , wherein the high-concentration layer is also formed between the drift layer and the JFET portion and between the drift layer and the deep layer.

The depletion layer adjustment layer is also formed between the drift layer and the JFET portion and between the drift layer and the deep layer, and among the depletion layer adjustment layer, the drift layer, the JFET portion, formed portion between and between the drift layer and the deep layer, to claim 1, wherein the impurity concentration than the deep layer is the low concentration layer of the second conductivity type low (30) The semiconductor device described.

2. The semiconductor device according to claim 1 , wherein the depletion layer adjustment layer is a second conductivity type low concentration layer (30) having an impurity concentration lower than that of the JFET portion.

The semiconductor device according to claim 5 , wherein the low concentration layer is also formed between the drift layer and the JFET portion and between the drift layer and the deep layer.

The depletion layer adjustment layer is also formed between the drift layer and the JFET portion and between the drift layer and the deep layer, and among the depletion layer adjustment layer, the drift layer, the JFET portion, 6. The semiconductor device according to claim 5 , wherein a portion formed between the drift layer and the deep layer is a high concentration layer (20) having an impurity concentration higher than that of the JFET portion.

The semiconductor device according to claim 4 , wherein the low-concentration layer has a second conductivity type impurity concentration lower than that of the deep layer.

The semiconductor device according to claim 1, wherein the deep layer is thicker than the base region.

On the deep layer, the depletion layer adjusting layer, and the JFET portion, a first conductivity type current spreading layer (4) having a width wider than that of the JFET portion is provided. The semiconductor device according to claim 1, further comprising a second conductivity type connection layer (5) for connecting the deep layer and the base region.

A gate trench (9) penetrating the source region and the base region and reaching the current spreading layer is formed;
The semiconductor device according to claim 10 , wherein a trench gate structure is configured by forming the gate insulating film and the gate electrode in the gate trench.

The trench gate structure is formed in a stripe shape by extending a plurality of trench gates with one direction as a longitudinal direction,
The semiconductor device according to claim 11 , wherein a plurality of the JFET portions are extended with a direction intersecting the trench gate structure as a longitudinal direction.

It said semiconductor The semiconductor device according to any one of claims 1 to 12 which is a wide band gap semiconductor.

Providing a first or second conductivity type substrate (1) made of a semiconductor;
Forming a drift layer (2) made of a first conductivity type semiconductor having a lower impurity concentration than the substrate on the substrate;
Forming a deep layer (3) made of a second conductivity type semiconductor on the drift layer;
After removing a part of the deep layer to form a trench (3a), the trench is filled with a depletion layer adjusting layer (20, 30) made of a semiconductor and a JFET portion (2a) made of a first conductivity type semiconductor. By forming the JFET portion sandwiched between the deep layers while forming the depletion layer adjustment layer on the side of the deep layer,
On the deep layer, the depletion layer adjustment layer, and the JFET portion, a current spreading layer (4) made of a first conductivity type semiconductor that is wider than the JFET portion and connected to the JFET portion is formed Forming a connection layer (5) made of a second conductivity type semiconductor connected to the deep layer on the deep layer;
Forming a base region (6) made of a second conductivity type semiconductor coupled to the coupling layer on the current spreading layer and the coupling layer;
Forming a source region (7) made of a first conductivity type semiconductor having a higher concentration than the drift layer on the base region;
Forming a part of the base region as a channel region and forming a gate insulating film (10) on the channel region;
Forming a gate electrode (11) on the gate insulating film;
Forming an interlayer insulating film (12) covering the gate electrode and the gate insulating film and having a contact hole formed;
Forming a source electrode (13) electrically connected to the source region through the contact hole;
Forming a drain electrode (14) on the back side of the substrate; and a method of manufacturing a semiconductor device including an inversion semiconductor element.

Forming the depletion layer adjustment layer and the JFET portion,
Forming a semiconductor layer (60) for forming the depletion layer adjusting layer on the deep layer;
Forming the trench in the deep layer together with the semiconductor layer;
Forming the depletion layer adjusting layer on at least a side surface of the deep layer in the trench by flowing the semiconductor layer by annealing;
The method for manufacturing a semiconductor device according to claim 14 , further comprising: embedding the trench by the JFET portion together with the depletion layer adjustment layer.

Flattening the surfaces of the deep layer, the depletion layer adjustment layer, and the JFET portion after forming the depletion layer adjustment layer and the JFET portion,
The method of manufacturing a semiconductor device according to claim 14 , wherein the current spreading layer and the coupling layer are formed after the planarization.

Forming the current spreading layer and the coupling layer includes:
Forming the current spreading layer by epitaxial growth;
Wherein a position away from the JFET portion and the depletion adjusting layer of the current spreading layer, a second conductivity type impurity to claims 14 and includes a forming, the said connecting layer by ion implantation 16 The manufacturing method of the semiconductor device as described in any one of these.

Providing a first or second conductivity type substrate (1) made of a semiconductor;
Forming a drift layer (2) made of a first conductivity type semiconductor having a lower impurity concentration than the substrate on the substrate;
Forming a deep layer (3) made of a second conductivity type semiconductor on the drift layer;
After removing a part of the deep layer to form the first trench (3a), the first trench is formed into a depletion layer adjusting layer (20, 30) made of a semiconductor and a JFET portion made of a first conductivity type semiconductor ( 2a), forming the JFET portion sandwiched between the deep layers while forming the depletion layer adjustment layer on the side surfaces of the deep layer;
Forming a current spreading layer (4) made of a first conductivity type semiconductor connected to the JFET portion on the deep layer, the depletion layer adjusting layer, and the JFET portion;
Forming a base region (6) made of a second conductivity type semiconductor on the current spreading layer;
Forming a source region (7) made of a first conductivity type semiconductor having a higher concentration than the drift layer on the base region;
Forming a second trench (70) penetrating the source region, the base region and the current spreading layer to reach the deep layer;
Forming a second conductivity type layer (71) connected to the deep layer in the second trench;
Forming a part of the base region as a channel region and forming a gate insulating film (10) on the channel region;
Forming a gate electrode (11) on the gate insulating film;
Forming an interlayer insulating film (12) covering the gate electrode and the gate insulating film and having a contact hole formed;
Forming a source electrode (13) electrically connected to the source region and the second conductivity type layer through the contact hole;
Forming a drain electrode (14) on the back side of the substrate; and a method of manufacturing a semiconductor device including an inversion semiconductor element.