JP7167717B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device having a semiconductor element of a MOS structure, and is particularly suitable when applied to a SiC semiconductor device using silicon carbide (hereinafter referred to as SiC) as a semiconductor material.

2. Description of the Related Art Conventionally, a semiconductor device having a semiconductor element of MOS structure has been proposed. For example, as a semiconductor device with a MOS structure, there is a MOSFET having a trench gate structure with a high channel density so that a large current can flow. In this MOSFET, a p-type base region and an n-type source region are sequentially formed on an n-type drift layer formed on an n ⁺ -type substrate. A plurality of trench gate structures are formed to reach the drift layer.

In such a MOSFET with a trench gate structure, a structure is proposed in which a p-type electric field relaxation layer formed from the p-type base region to a position deeper than the trench gate structure is provided so as to intersect the trench gate structure. (See Patent Document 1). In such a structure, the n-type drift layer between the p-type electric field relaxation layers can be used as a JFET section, and current can flow through the JFET section when the semiconductor element is turned on. Since both sides of the JFET portion are sandwiched between the p-type electric field relaxation layers, it is possible to suppress the rise of the electric field and improve the withstand voltage. can be Therefore, the ratio of the JFET portion to the total area of the JFET portion and the p-type electric field relaxation layer can be increased, the JFET resistance can be reduced, and the on-resistance can be reduced.

In addition, by narrowing the width of the JFET portion, the rise of the electric field is further suppressed, and by increasing the n-type impurity concentration of the JFET portion in order to reduce the JFET resistance, the breakdown voltage is improved and the on-resistance is reduced. We are trying to achieve both reduction.

Japanese Patent No. 4793437

However, as a result of intensive studies by the present inventors, it has been confirmed that the pinch-off voltage of the MOSFET is lower than the voltage normally expected. Specifically, the pinch-off voltage is usually determined as the drain voltage Vd when the channel portion is pinched off, and is about 10 to 15 [V], but it was confirmed by simulation that the voltage is lower than that. . FIG. 8 is a diagram showing the results. As shown in this figure, the pinch-off voltage was obtained when the drain voltage Vd was about 6 [V].

Since the pinch-off voltage is drain voltage Vd<10 [V], the decrease in pinch-off voltage means that the JFET section is pinched off before the channel. That is, it is considered that the JFET portion functions as a channel. Hereinafter, a normal channel formed on the side surface of the trench gate structure will be referred to as a gate channel, and a channel formed by the JFET portion will be referred to as a JFET channel.

Since the JFET channel is a normally-on type, it does not affect the threshold voltage Vth of the MOSFET, but it greatly affects the saturation current. That is, the JFET channel is more susceptible to short channel effects than the gate channel. Specifically, the p-type electric field relaxation layer is formed on both sides of the JFET portion, and the depletion layer spreads inside the p-type electric field relaxation layer. The dimension in the direction of current flow in the portion where This causes a short channel effect in the JFET channel.

Due to this short-channel effect, when the pinch-off voltage is exceeded, the drain current Id increases as shown in FIG. It becomes easy to become the non-saturation characteristic that it does. It is known that when the saturation current has non-saturation characteristics, the mirror period when the gate voltage rises or falls is not flattened, and an extra charge is formed between the gate and the source, resulting in a long switching time. It is As a result, a problem arises in that the switching loss increases even though the on-resistance is reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a trench gate structure semiconductor device capable of reducing switching loss by improving non-saturation characteristics and shortening switching time.

In order to achieve the above object, a semiconductor device according to claim 1 comprises a semiconductor substrate (1) of a first or second conductivity type, and a first semiconductor substrate (1) formed on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate. A first conductivity type layer (2) made of a conductivity type semiconductor, and a linear portion formed on the first conductivity type layer and having at least one longitudinal direction as viewed from the normal direction of the semiconductor substrate and a second-conductivity-type electric field-blocking layer (4) made of a second-conductivity-type semiconductor configured to have a A JFET portion (3) made of a semiconductor of one conductivity type, and a current spreading layer (5) formed on the electric field blocking layer and the JFET portion and made of a semiconductor of a first conductivity type having a concentration higher than that of the first conductivity type layer. and a base region (6) made of a semiconductor of the second conductivity type formed on the current spreading layer, and a first conductivity type impurity concentration higher than that of the first conductivity type layer formed on the base region. a source region (8) made of a semiconductor of a first conductivity type and a gate insulating film (12) formed in a gate trench (11) formed deeper than the base region from the surface of the source region, covering the inner wall surface of the gate trench; ) and a gate electrode (13) disposed on the gate insulating film, a trench gate structure in which a plurality of gate electrodes are arranged in stripes with the longitudinal direction intersecting one direction; and an interlayer insulating film (14) covering the gate insulating film and formed with a contact hole, a source electrode (15) in ohmic contact with the source region through the contact hole, and a drain formed on the back side of the semiconductor substrate. A semiconductor element is provided which includes an electrode (16). In such a configuration, a channel region is formed in the base region located on the side surface of the trench gate structure based on the application of the gate voltage to the gate electrode, the semiconductor element is turned on, and the application of the gate voltage is stopped. An operation to turn off the element is performed. The width L _JFET and the first conductivity type impurity concentration N _JFET of the JFET portion are defined by Vp as the pinch-off voltage in the channel region, Vbi as the built-in voltage of the semiconductor, q [C] as the elementary charge, and the semiconductor that constitutes the JFET portion. ε is the dielectric constant of , N _DP [cm ⁻³ ] is the second conductivity type impurity concentration of the electric field blocking layer, and the set value is a value larger than the gate voltage applied to the gate electrode during normal operation of the semiconductor device is set to a value that satisfies the following equation, where Vgx is Vgx.

Therefore, the mirror voltage during the mirror period can be kept substantially constant, the switching time can be shortened, and the switching loss can be reduced. Therefore, a semiconductor device having a trench gate structure capable of reducing switching loss by improving non-saturation characteristics and shortening switching time can be provided.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment; FIG. 2 is a perspective cross-sectional view of the SiC semiconductor device shown in FIG. 1; FIG. FIG. 2 is a graph showing drain voltage Vd-drain current Id characteristics of the SiC semiconductor device shown in FIG. 1; FIG. 10 is a diagram showing the result of examining turn-off waveforms by simulation for each of the conventional structure and the structure of the first embodiment; FIG. 10 is a diagram showing the results of examining the relationship between the width L of the _JFET portion and the pinch-off voltage Vp by changing the p-type impurity concentration of the p-type base region; FIG. 10 is a diagram showing the relationship between the width L _JFET of the JFET portion and the n-type impurity concentration N _JFET that can prevent pinch-off; 2 is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1; FIG. FIG. 7B is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device continued from FIG. 7A; 7C is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device continued from FIG. 7B; FIG. 7D is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 7C; FIG. 7D is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device continued from FIG. 7D; FIG. 7E is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 7E; FIG. 7F is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device continued from FIG. 7F; FIG. FIG. 10 is a graph showing drain voltage Vd-drain current Id characteristics of a conventional SiC semiconductor device;

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. In this embodiment, a SiC semiconductor device using SiC as a semiconductor material will be described as an example. The SiC semiconductor device of the present embodiment is formed by forming the inverted vertical MOSFET of the trench gate structure shown in FIGS. 1 and 2 as a semiconductor element. The vertical MOSFETs shown in these figures are formed in the cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming the peripheral breakdown voltage structure so as to surround the cell region. Only vertical MOSFETs are shown here. 1 and 2, the width direction of the vertical MOSFET is the X direction, the depth direction of the vertical MOSFET that intersects the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET is The horizontal direction, that is, the direction normal to the XY plane will be described as the Z direction.

As shown in FIGS. 1 and 2, an SiC semiconductor device uses an n ⁺ -type substrate 1 made of SiC as a semiconductor substrate. An n ⁻ -type layer 2 made of SiC is formed on the main surface of an n ⁺ -type substrate 1 . The n ⁺ -type substrate 1 has a (0001) Si surface, for example, an n-type impurity concentration of 5.9×10 ¹⁸ /cm ³ and a thickness of 100 μm. The n ⁻ -type layer 2 has, for example, an n-type impurity concentration of 7.0×10 ¹⁵ to 1.0×10 ¹⁶ /cm ³ and a thickness of 8.0 μm.

A JFET portion 3 made of SiC and an electric field blocking layer 4 are formed on the n ^{− -type} layer 2 ^. ing.

The JFET portion 3 and the electric field blocking layer 4 constitute a saturation current suppressing layer, and both have linear portions extending in the X direction and alternately and repeatedly arranged in the Y direction. . That is, when viewed from the direction normal to the main surface of n ⁺ -type substrate 1, at least a portion of JFET portion 3 and electric field blocking layer 4 each have a plurality of strips, that is, strips, which are arranged alternately. layout.

In this embodiment, the JFET portion 3 is formed below the electric field blocking layer 4 . Therefore, the striped portions of the JFET portion 3 are connected to each other under the electric field blocking layer 4, and each striped portion of the JFET portion 3 has a plurality of electric field blocking layers. It is placed between 4.

Each portion of the striped portion of the JFET portion 3, that is, each strip-shaped portion, has a width of, for example, 0.4 μm or more, preferably 0.8 μm or more, and a pitch of 0.6 to 2, which is the formation interval. 0 μm. The JFET portion 3 has a thickness of 0.8 μm, for example, and an n-type impurity concentration higher than that of the n ⁻ -type layer 2, for example, 0.5×10 ¹⁷ to 2.0×10 ¹⁷ . / cm ³ . This JFET portion 3 is of a normally-on type, and serves as a portion through which current flows when the vertical MOSFET is turned on. Therefore, the JFET portion 3 can also be regarded as a channel. The channel formed by the JFET portion 3 corresponds to the JFET channel.

The electric field blocking layer 4 is a portion constituting a lower part of the electric field relaxation layer, and is composed of a p-type impurity layer. As described above, the electric field blocking layer 4 is striped. Each strip-shaped portion of the striped electric field blocking layer 4 has a width, depth, and p-type impurities so as not to be completely depleted even if the drain voltage Vd becomes a high voltage when the MOSFET is switched on and off. Density is set. For example, each strip-shaped portion of electric field blocking layer 4 has a width of 0.6 μm, a thickness of 0.8 μm, and a p-type impurity concentration of 5.0×10 ¹⁷ to 1.0×10 ¹⁸ /cm ³ . there is In the case of this embodiment, the electric field blocking layer 4 has a constant p-type impurity concentration in the depth direction. The surface of the electric field blocking layer 4 opposite to the n ⁻ -type layer 2 is flush with the surface of the JFET portion 3 .

Furthermore, an n-type current spreading layer 5 made of SiC is formed on the JFET portion 3 and the electric field blocking layer 4 . The n ^- type current spreading layer 5 is a layer that allows the current flowing through the channel to diffuse in the X direction, as will be described later. In this embodiment, the n-type current spreading layer 5 extends in the Y direction, has an n-type impurity concentration equal to or higher than that of the JFET portion 3, and has a thickness of 0.5 μm, for example. ing. The n-type current spreading layer 5 has an n-type impurity concentration of 2.0×10 ¹⁶ to 5.0×10 ¹⁷ /cm ³ .

Here, for convenience, the drift layer is divided into the n ⁻ -type layer 2, the JFET portion 3, and the n-type current spreading layer 5 for explanation. Concatenated.

A p-type base region 6 made of SiC is formed on the n-type current spreading layer 5 . In addition, below the p-type base region 6, specifically, between the surfaces of the JFET portion 3 and the electric field blocking layer 4 and the p-type base region 6, where the n-type current spreading layer 5 is not formed, , a p-type deep layer 7 is formed. The p-type deep layer 7 is a portion forming an upper part of the electric field relaxation layer. In this embodiment, the p-type deep layer 7 extends in a direction intersecting with the longitudinal direction of the striped portion of the JFET portion 3 and the electric field blocking layer 4, here the Y direction as the longitudinal direction. The layout is such that a plurality of layers are arranged alternately with the n-type current spreading layers 5 in the direction. Through this p-type deep layer 7, the p-type base region 6 and the electric field blocking layer 4 are electrically connected. The formation pitch of the n-type current spreading layer 5 and the p-type deep layer 7 is matched with the formation pitch of the trench gate structure, which will be described later.

Furthermore, an n-type source region 8 is formed on the p-type base region 6 . The n-type source region 8 is formed in a portion of the p-type base region 6 corresponding to a trench gate structure, which will be described later, and formed on both sides of the trench gate structure.

The p-type base region 6 is thinner than the electric field blocking layer ⁴ and has a lower p-type ^impurity concentration. 4 to 0.6 μm. The p-type deep layer 7 has a thickness equal to that of the n-type current spreading layer 5 and has an arbitrary p-type impurity concentration, but is equal to, for example, the electric field blocking layer 4 .

The n-type source region 8 is a region for making contact with a source electrode 15 which will be described later, and has a higher concentration of n-type impurities than the n ⁻ -type layer 2 . The n-type source region 8 has, for example, an n-type impurity concentration of 1.0×10 ¹⁸ to 5.0×10 ¹⁹ /cm ³ and a thickness of 0.3 to 0.7 μm.

Furthermore, a position on the p-type base region 6 corresponding to the p-type deep layer 7, in other words, a position different from the n-type source region 8 and on the opposite side of the trench gate structure with the n-type source region 8 interposed therebetween. , a p-type coupling layer 10 is formed. The p-type coupling layer 10 is a layer for electrical connection by coupling the p-type base region 6 and a source electrode 15 to be described later.

The p-type coupling layer 10 is a portion that is brought into contact with the source electrode 15 as a contact region. For example, the p-type coupling layer 10 has a high p-type impurity concentration of 5.0×10 ¹⁷ to 1.0×10 ²⁰ /cm ³ and a thickness of 0.2 to 0.3 μm. .

Furthermore, the p-type base region 6 and the n-type source region 8 have a width of, for example, 0.4 μm and a depth of 0.4 μm so as to penetrate the n-type source region 8 and the p-type base region 6 and reach the n-type current spreading layer 5 . A gate trench 11 is formed which is 0.2 to 0.4 μm deeper than the total film thickness. The p-type base region 6 and the n-type source region 8 are arranged so as to be in contact with the side surfaces of the gate trench 11 . The gate trench 11 has a strip-shaped layout with the X direction in FIG. is formed by A plurality of gate trenches 11 are formed in stripes arranged at equal intervals in the X direction, and a p-type base region 6 and an n-type source region 8 are arranged therebetween. A p-type deep layer 7 and a p-type coupling layer 10 are arranged at intermediate positions of each gate trench 11 .

At the side of this gate trench 11, the p-type base region 6 forms a channel region connecting between the n-type source region 8 and the n-type current spreading layer 5 during operation of the vertical MOSFET. This channel region corresponds to the gate channel. The inner wall surface of the gate trench 11 including this channel region is covered with a gate insulating film 12 . A gate electrode 13 made of doped Poly-Si is formed on the surface of the gate insulating film 12, and the inside of the gate trench 11 is filled with the gate insulating film 12 and the gate electrode 13 to form a trench gate structure. It is

A source electrode 15 and a gate wiring layer (not shown) are formed on the surface of the n-type source region 8 and the surface of the gate electrode 13 with an interlayer insulating film 14 interposed therebetween. The source electrode 15 and the gate wiring layer are composed of a plurality of metals such as Ni/Al. Of the plurality of metals, at least n-type SiC, more specifically, the portion in contact with n-type source region 8 is made of a metal capable of ohmic contact with n-type SiC. At least the portion of the plurality of metals that contacts p-type SiC, specifically the p-type coupling layer 10, is made of a metal capable of making ohmic contact with p-type SiC. Although the source electrode 15 is electrically insulated from the SiC portion by being formed on the interlayer insulating film 14, the n-type source region 8 and the p-type electrode 15 are electrically isolated from the SiC portion through the contact holes formed in the interlayer insulating film 14. It is in electrical contact with the tie layer 10 . Since the p-type base region 6, the p-type deep layer 7 and the electric field blocking layer 4 are connected through the p-type coupling layer 10, all of them are set to the source potential.

On the other hand, a drain electrode 16 electrically connected to the n ⁺ -type substrate 1 is formed on the back side of the n ⁺ -type substrate 1 . With such a structure, a vertical MOSFET having an n-channel type inverted trench gate structure is formed. A cell region is configured by arranging a plurality of cells of such vertical MOSFETs. A SiC semiconductor device is constructed by constructing a peripheral breakdown voltage structure, such as a guard ring (not shown), so as to surround the cell region in which such a vertical MOSFET is formed.

A SiC semiconductor device having a vertical MOSFET configured in this way applies, for example, a gate voltage Vg of 20 V to the gate electrode 13 with a source voltage Vs of 0 V and a drain voltage Vd of 1 to 1.5 V. It is operated by applying voltage. That is, the vertical MOSFET forms a channel region in the p-type base region 6 in contact with the gate trench 11 by applying the gate voltage Vg. Thereby, the n-type source region 8 and the n-type current spreading layer 5 are electrically connected. Therefore, the vertical MOSFET is turned on, from the n ⁺ -type substrate 1, through the n ⁻ -type layer 2, the JFET portion 3, and the drift layer composed of the n-type current spreading layer 5, further from the channel region to the n-type source region 8 , the current flows between the drain and the source. In addition, by stopping the application of the gate voltage Vg, the channel region disappears, the n-type source region 8 and the n-type current spreading layer 5 become non-conductive, the vertical MOSFET is turned off, and the drain-source Current flow between is stopped.

At this time, the SiC semiconductor device of this embodiment includes the JFET portion 3 and the electric field blocking layer 4 . Therefore, during the operation of the vertical MOSFET, the JFET portion 3 and the electric field blocking layer 4 function as a saturation current suppressing layer, exhibiting a saturation current suppressing effect, thereby achieving a low on-resistance and maintaining a low saturation current. It becomes possible to Specifically, since the striped portion of the JFET portion 3 and the electric field blocking layer 4 are alternately and repeatedly formed, the following operation is performed.

First, when the drain voltage Vd is a voltage applied during normal operation, such as 1 to 1.5 V, the depletion layer extending from the electric field blocking layer 4 side to the JFET portion 3 is formed in a stripe shape in the JFET portion 3. It stretches only to a width smaller than the width of the part that has been made. Therefore, even if the depletion layer extends into the JFET portion 3, a current path is secured. Further, since the n-type impurity concentration of the JFET portion 3 is higher than that of the n ⁻ -type layer 2 and the current path can be configured to have a low resistance, a low on-resistance can be achieved.

Further, when the drain voltage Vd becomes higher than the voltage during normal operation due to a load short circuit or the like, the depletion layer extending from the electric field blocking layer 4 side to the JFET portion 3 extends beyond the width of the striped portion of the JFET portion 3. . Then, the JFET portion 3 is immediately pinched off before the n-type current spreading layer 5 is pinched off. At this time, the relationship between the drain voltage Vd and the width of the depletion layer is determined based on the width of the striped portion of the JFET portion 3 and the n-type impurity concentration. Therefore, the width of the striped portion of the JFET portion 3 and the n-type impurity concentration are set so that the JFET portion 3 is pinched off when the voltage becomes slightly higher than the drain voltage Vd during normal operation. is doing. Therefore, the JFET section 3 can be pinched off even with a low drain voltage Vd. In this way, by immediately pinching off the JFET unit 3 when the drain voltage Vd becomes higher than the voltage during normal operation, it is possible to maintain a low saturation current, and furthermore, it is possible to maintain a low saturation current. It is possible to improve the resistance of the SiC semiconductor device.

In this way, the JFET portion 3 and the electric field blocking layer 4 function as a saturation current suppressing layer and exhibit a saturation current suppressing effect, thereby providing a SiC semiconductor device capable of achieving both a low on-resistance and a low saturation current. becomes possible.

Furthermore, by providing the electric field blocking layers 4 so as to sandwich the JFET section 3, a structure is formed in which the striped portions of the JFET section 3 and the electric field blocking layers 4 are alternately and repeatedly formed. Therefore, even if the drain voltage Vd becomes a high voltage, the extension of the depletion layer extending from below to the n ⁻ -type layer 2 is suppressed by the electric field blocking layer 4, and extension to the trench gate structure can be prevented. can. Therefore, the electric field suppressing effect of reducing the electric field applied to the gate insulating film 12 can be exhibited, and the destruction of the gate insulating film 12 can be suppressed. . Since the depletion layer can be prevented from extending to the trench gate structure in this way, the n ⁻ -type layer 2 and the JFET portion 3, which form part of the drift layer, can have a relatively high n-type impurity concentration. On-resistance can be achieved.

In addition, in the SiC semiconductor device of the present embodiment, the widths and impurity concentrations of the JFET portion 3 and the electric field blocking layer 4 are set so that the JFET channel is not pinched off until the drain voltage Vd reaches the pinch-off voltage of the gate channel. be. In other words, as described above, when the drain voltage Vd becomes higher than the voltage during normal operation due to a load short-circuit or the like, the JFET portion 3 is immediately pinched off, but the condition is set so that it is not pinched off at the voltage during normal operation. There is. Specifically, the following formula is satisfied.

なお、数式１において、Ｖｐはピンチオフ電圧である。Ｖｂｉは半導体材料の内蔵電圧であり、本実施の場合はＪＦＥＴ部３において電界ブロック層４とのＰＮ接合による空乏層広がり分相当の電圧である。ｑは素電荷［Ｃ］、Ｎ_ＪＦＥＴはＪＦＥＴ部３のｎ型不純物濃度［ｃｍ^－３］である。Ｌ_ＪＦＥＴはＪＦＥＴ部３のうちのストライプ状とされている部分の各部の幅［ｃｍ］である。εｓｉｃは、ＳｉＣの誘電率である。Ｎ_ＤＰは電界ブロック層４のｐ型不純物濃度［ｃｍ^－３］である。また、Ｖｇｘは、通常作動時に印加されるゲート電圧を想定した設定値である。設定値は、縦型ＭＯＳＦＥＴの駆動時にゲート電極１３に対して印加されるゲート電圧よりも大きな電圧としてあるが、仕様に応じて適宜設定されれば良い。例えば、縦型ＭＯＳＦＥＴの駆動時にゲート電極１３に印加されるゲート電圧が１５［Ｖ］とされるのであれば、例えばＶｇｘを２０［Ｖ］に設定している。

Note that in Equation 1, Vp is the pinch-off voltage. Vbi is a built-in voltage of the semiconductor material, and in this embodiment, it is a voltage corresponding to the spread of the depletion layer due to the PN junction with the electric field blocking layer 4 in the JFET section 3 . q is the elementary charge [C], and N _JFET is the n-type impurity concentration [cm ⁻³ ] of the JFET portion 3 . L _JFET is the width [cm] of each portion of the striped portion of the JFET portion 3 . εsic is the dielectric constant of SiC. N _DP is the p-type impurity concentration [cm ⁻³ ] of the electric field blocking layer 4 . Vgx is a set value assuming the gate voltage applied during normal operation. The set value is a voltage higher than the gate voltage applied to the gate electrode 13 when driving the vertical MOSFET, but it may be set as appropriate according to the specifications. For example, if the gate voltage applied to the gate electrode 13 when driving the vertical MOSFET is 15 [V], Vgx is set to 20 [V].

Thus, by setting the width and impurity concentration of the JFET portion 3 and the electric field blocking layer 4 so as to satisfy Equation 1, the pinch off occurs at the gate channel, and the pinch off voltage of the vertical MOSFET is equal to the pinch off voltage of the gate channel. voltage. Therefore, it is possible to prevent non-saturation characteristics from occurring in the saturation region.

Specifically, as shown in FIG. 3, the pinch-off voltage becomes a value that increases corresponding to the gate voltage Vg. It shows a saturation characteristic in which the current Id does not rise much. This indicates that the gate channel is pinched off, and that the saturation region does not have non-saturation characteristics.

When the gate channel is pinched off in this way, the mirror period when the gate voltage rises or falls can be flattened and shortened. For example, when the turn-off waveforms of the conventional structure of Patent Document 1 and the structure of the present embodiment were investigated by simulation, the results shown in FIG. 4 were obtained.

Ideally, the conditions for good switching characteristics are that the mirror voltage is constant during the mirror period and that the mirror period is short. However, as shown in FIG. 4, in the case of the structure of Patent Document 1, the mirror voltage is not constant during the mirror period, but becomes inclined, and the mirror period is also long. In such a state, the switching time becomes long and the switching loss increases.

On the other hand, in the case of the structure of the present embodiment, as shown in FIG. 4, the mirror voltage during the mirror period is substantially constant and the mirror period is short as compared with the case of Patent Document 1. was becoming

Specifically, the timing at which the drain voltage Vd begins to rise is the start timing of the mirror period, and the timing at which the gate voltage Vg becomes constant and begins to further decrease is the end timing of the mirror period. Strictly speaking, the gate voltage Vg in a constant state is assumed to be the median value of the variation because the gate voltage Vg varies without becoming a constant value. Comparing the start timing of the mirror period with the potential difference ΔVg of the gate voltage Vg in the constant state, the structure of the present embodiment has a smaller potential difference ΔVg than the structure of Patent Document 1. This indicates that the fluctuation of the mirror voltage during the mirror period is small and the mirror voltage is almost constant. Also, dVg/dt, which corresponds to the amount of change in the gate voltage Vg per unit time, is high, and it can be seen that the transition to the mirror voltage is quicker and the mirror period is shortened.

By making the mirror voltage substantially constant during the mirror period in this manner, the switching time can be shortened, and the switching loss can be reduced. Therefore, an SiC semiconductor device having a trench gate structure capable of reducing switching loss by improving non-saturation characteristics and shortening switching time can be obtained.

The width L _JFET of the JFET portion 3 and the n-type impurity concentration N _JFET which can obtain such an effect vary slightly depending on the p-type impurity concentration of the p-type base region 6 . However, basically, if one of the width L _JFET and the n-type impurity concentration N _JFET of the JFET portion 3 is determined, the other is also determined. For example, when the n-type impurity concentration N _JFET of the JFET portion 3 is 1.0×10 ¹⁷ /cm ³ , assuming that the built-in voltage Vbi is constant at 3 [V], the width L of the _JFET portion 3 and the pinch-off A relationship with the voltage Vp was investigated. The p-type impurity concentration of the p-type base region 6 was set to 5.0×10 ¹⁷ /cm ³ and 1.0×10 ¹⁸ /cm ³ . FIG. 5 is a diagram showing the results.

Although the relationship shown in this figure changes slightly according to the change of the p-type base region 6, it is generally the same, and the pinch-off voltage Vp increases as the width L of the _JFET portion 3 increases. Assuming that the set value Vgx=20, for example, the JFET portion 3 can be prevented from being pinched off if the width L of the _JFET portion 3 is 0.4 μm or more.

Further, the width L _JFET of the JFET portion 3 that can prevent pinch-off changes according to the n-type impurity concentration N _JFET of the JFET portion 3 . FIG. 6 shows the result of examining these relationships by simulation. As shown in this figure, the width L _JFET of the JFET portion 3 may be reduced as the n-type impurity concentration N _JFET of the JFET portion 3 increases. Therefore, in FIG. 6, the width L _JFET and the n-type impurity concentration N _JFET of the JFET portion 3 are adjusted so that the area is above the curve connecting the points plotted when the set value Vgx=20 obtained by the simulation is obtained. If set, the JFET portion 3 can be prevented from pinching off.

5.0×10 ¹⁶ /cm ³ is assumed to be the lowest value for the n-type impurity concentration N _JFET of the JFET portion 3, but the width L _JFET required at this time is 0.8 μm. there were. Therefore, within the range assumed for the n-type impurity concentration N _JFET of the JFET portion 3, if the width L _JFET is 0.8 μm or more, the JFET portion 3 does not pinch off in the vertical MOSFET having the structure of this embodiment. can be done.

As described above, in the present embodiment, the drain voltage Vd becomes the pinch-off voltage of the gate channel in the structure in which the electric field blocking layer 4 is formed to obtain a low saturation current and a low on-resistance while obtaining a withstand voltage. The JFET portion 3 is prevented from being pinched off until the time. As a result, the gate channel is pinched off, and the pinch-off voltage of the vertical MOSFET can be the pinch-off voltage of the gate channel. Therefore, it is possible to prevent non-saturation characteristics from occurring in the saturation region.

Therefore, the mirror voltage during the mirror period can be kept substantially constant, the switching time can be shortened, and the switching loss can be reduced. Therefore, an SiC semiconductor device having a trench gate structure capable of reducing switching loss by improving non-saturation characteristics and shortening switching time can be obtained.

Next, a method for manufacturing a SiC semiconductor device having a vertical MOSFET having an n-channel type inverted trench gate structure according to the present embodiment will be described with reference to cross-sectional views during manufacturing steps shown in FIGS. 7A to 7G. explain.

[Steps shown in FIG. 7A]
First, an n ⁺ -type substrate 1 is prepared as a semiconductor substrate. Then, an n ⁻ -type layer 2 made of SiC is formed on the main surface of n ⁺ -type substrate 1 by epitaxial growth using a CVD (chemical vapor deposition) apparatus (not shown). At this time, a so-called epi-substrate in which an n ⁻ -type layer 2 is grown in advance on the main surface of the n ⁺ -type substrate 1 may be used. Then, the JFET portion 3 is formed by epitaxially growing the JFET portion 3 made of SiC on the n ⁻ -type layer 2 or by implanting n-type impurity ions into the n ⁻ -type layer 2 . At this time, the width L _JFET and the n-type impurity concentration N _JFET of the JFET portion 3 portion 3 are set so as to satisfy Equation 1 above.

The epitaxial growth is performed by introducing a gas, such as a nitrogen gas, as an n-type dopant, in addition to silane and propane, which are raw material gases of SiC.

[Steps shown in FIG. 7B]
After disposing a mask 17 on the surface of the JFET portion 3, the mask 17 is patterned to open a region where the electric field blocking layer 4 is to be formed. Then, the electric field blocking layer 4 is formed by ion-implanting a p-type impurity. After that, the mask 17 is removed.

Although the electric field blocking layer 4 is formed by ion implantation here, the electric field blocking layer 4 may be formed by a method other than ion implantation. For example, the JFET portion 3 is selectively anisotropically etched to form a recess at a position corresponding to the electric field blocking layer 4 , and a p-type impurity layer is epitaxially grown thereon. The electric field blocking layer 4 is formed by flattening the p-type impurity layer in the portion where it is formed. Thus, the electric field blocking layer 4 can also be formed by epitaxial growth. When p-type SiC is epitaxially grown, a p-type dopant gas such as trimethylaluminum (TMA) may be introduced in addition to the source gas of SiC.

[Steps shown in FIG. 7C]
Subsequently, n-type current spreading layer 5 is formed by epitaxially growing n-type SiC on JFET portion 3 and electric field blocking layer 4 . Then, a mask (not shown) is placed on the n-type current spreading layer 5 so as to open a region where the p-type deep layer 7 is to be formed. After that, the p-type deep layer 7 is formed by ion-implanting p-type impurities from above the mask.

An example of forming the p-type deep layer 7 by ion implantation has been shown, but it can also be formed by a method other than ion implantation. For example, similarly to the electric field blocking layer 4, after forming a recess in the n-type current spreading layer 5, a p-type impurity layer is epitaxially grown, and the p-type impurity layer is planarized to form a p-type deep layer. 7 may be formed. Alternatively, the n-type current spreading layer 5 may be formed by ion implantation or the like after the p-type deep layer 7 is formed.

[Steps shown in FIG. 7D]
A p-type base region 6 and an n-type source region 8 are epitaxially grown in this order on the n-type current spreading layer 5 and the p-type deep layer 7 using a CVD apparatus (not shown). For example, in the same CVD apparatus, first, the p-type deep layer 7 is formed by epitaxial growth in which a p-type dopant gas is introduced. Subsequently, after stopping the introduction of the p-type dopant gas, the n-type source region 8 is formed by epitaxial growth while introducing the n-type dopant gas.

[Steps shown in FIG. 7E]
A mask (not shown) is placed on the n-type source region 8 with an opening at the position where the p-type coupling layer 10 is to be formed. After ion-implanting p-type impurities from above the mask, heat treatment at 1500° C. or higher is performed for activation. Either one or both of boron (B) and aluminum (Al) is used as an element to be ion-implanted. As a result, the p-type coupling layer 10 can be formed by implanting the p-type impurity ions into the n-type source region 8 .

[Steps shown in FIG. 7F]
After forming a mask (not shown) on the n-type source region 8 and the like, a region of the mask where the gate trench 11 is to be formed is opened. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using a mask to form the gate trench 11 .

[Steps shown in FIG. 7G]
Thereafter, the gate insulating film 12 is formed by, for example, thermal oxidation after removing the mask, and covers the inner wall surface of the gate trench 11 and the surface of the n-type source region 8 with the gate insulating film 12 . Then, after depositing Poly-Si doped with p-type impurities or n-type impurities, this is etched back to leave Poly-Si at least in the gate trench 11, thereby forming the gate electrode 13. Next, as shown in FIG. This completes the trench gate structure.

Although not shown, the following steps are performed. That is, an interlayer insulating film 14 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 13 and the gate insulating film 12 . A contact hole is formed in the interlayer insulating film 14 using a mask (not shown) to expose the n-type source region 8 and the p-type deep layer 7 . Then, after forming an electrode material composed of, for example, a laminated structure of a plurality of metals on the surface of the interlayer insulating film 14, the electrode material is patterned to form the source electrode 15 and the gate wiring layer. Further, a drain electrode 16 is formed on the back side of the n ⁺ -type substrate 1 . Thus, the SiC semiconductor device according to this embodiment is completed.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be appropriately modified within the scope of the claims.

(1) For example, various dimensions such as the impurity concentration, thickness, width, etc. of each part constituting the SiC semiconductor device shown in the above embodiments are merely examples.

(2) In addition, the electric field blocking layer 4 may be connected to some part to have a source potential. In each cell of the vertical MOSFET, the p-type deep layer 7, the p-type base region 6 and It does not have to be connected to the source electrode 15 via the p-type coupling layer 10 . However, with such a configuration, it is possible to fix the electric field blocking layer 4 to the source potential in each cell.

If the portion to be connected for fixing the electric field blocking layer 4 to the source potential becomes far, the current path from the electric field blocking layer 4 to the source electrode 15 becomes long when the vertical MOSFET is driven for high-speed switching, and the electric field The charge/discharge time through the block layer 4 is lengthened. This lengthens the switching time and increases the switching loss. On the other hand, if the electric field blocking layer 4 is fixed to the source potential in each cell, the current path from the electric field blocking layer 4 to the source electrode 15 can be shortened, and the charging/discharging time through the electric field blocking layer 4 can be shortened. Therefore, switching time can be shortened, and switching loss can be reduced.

(3) In addition, in the above-described embodiment, an n-channel type vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type is described as an example, but the conductivity type of each component is An inverted p-channel type vertical MOSFET may be used. Further, in the above description, a vertical MOSFET is used as an example of a semiconductor element, but the present invention can also be applied to an IGBT having a similar structure. In the case of an n-channel type IGBT, the conductivity type of the n ⁺ -type substrate 1 is simply changed from n-type to p-type in each of the above-described embodiments, and other structures and manufacturing methods are the same as in each of the above-described embodiments. is.

(4) In the above embodiments, a semiconductor device using SiC as a semiconductor material has been described. The present invention can also be applied to In that case, for Equation 1 described above, instead of the dielectric constant εsic of SiC, a dielectric constant ε corresponding to the semiconductor material used may be applied.

3 JFET portion 4 electric field blocking layer 5 n-type current spreading layer 6 p-type base region 8 n-type source region 11 gate trench 13 gate electrode 15 source electrode 16 drain electrode

Claims (3)

A semiconductor device comprising an inverted semiconductor element,
a semiconductor substrate (1) of first or second conductivity type;
a first conductivity type layer (2) formed on the semiconductor substrate and made of a first conductivity type semiconductor having an impurity concentration lower than that of the semiconductor substrate;
A second conductivity type semiconductor formed on the first conductivity type layer and configured to have a linear portion having at least one longitudinal direction as viewed from the normal direction of the semiconductor substrate. a second conductivity type electric field blocking layer (4);
a JFET portion (3) made of a first conductivity type semiconductor formed on the first conductivity type layer and sandwiched between the electric field blocking layers;
a current spreading layer (5) formed on the electric field blocking layer and the JFET portion and made of a semiconductor of a first conductivity type having a concentration higher than that of the first conductivity type layer;
a base region (6) made of a semiconductor of a second conductivity type formed on the current spreading layer;
a source region (8) formed on the base region and made of a first conductivity type semiconductor having a first conductivity type impurity concentration higher than that of the first conductivity type layer;
a gate insulating film (12) covering an inner wall surface of the gate trench (11) formed from the surface of the source region to a depth deeper than the base region; and a gate electrode disposed on the gate insulating film. (13), a trench gate structure in which a plurality of gates are arranged in a stripe shape with a direction intersecting with the one direction as a longitudinal direction;
an interlayer insulating film (14) covering the gate electrode and the gate insulating film and having a contact hole formed therein;
a source electrode (15) in ohmic contact with the source region through the contact hole;
a drain electrode (16) formed on the back surface side of the semiconductor substrate;
A channel region is formed in the base region located on the side surface of the trench gate structure based on the application of the gate voltage to the gate electrode to turn on the semiconductor element, and the semiconductor element is turned on by stopping the application of the gate voltage. perform the operation to turn off the element,
The width L _JFET and the first conductivity type impurity concentration N _JFET of the JFET portion constitute the JFET portion with Vp as the pinch-off voltage in the channel region, Vbi as the built-in voltage of the semiconductor, and q [C] as the elementary charge. _ε is the dielectric ^constant of the semiconductor; Let Vgx be the set value to be

A semiconductor device that is set to a value that satisfies A cell region is configured by arranging a plurality of cells of the semiconductor elements,
In each of the semiconductor elements of the plurality of cells,
a second conductivity type deep layer (7) formed on the electric field blocking layer and the JFET portion together with the current spreading layer and electrically connected to the electric field blocking layer;
a connection layer (10) formed on the opposite side of the trench gate structure with the source region interposed therebetween and made of a semiconductor of a second conductivity type for connecting the base region to the source electrode;
the base region is formed on the current spreading layer and the deep layer,
2. The semiconductor device according to claim 1, wherein said electric field blocking layer is electrically connected to said deep layer in each of said plurality of cells. The JFET portion has the first conductivity type impurity concentration N _JFET is 0.5×10 ¹⁷ ~2.0 x 10 ¹⁷ / cm ³ and the width L _JFET 3. The semiconductor device according to claim 1, wherein the thickness is 0.8 μm or more.

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